Initial public release.
This commit is contained in:
Joe Kearney
parent
7b169e8116
commit
dac4af8d25
255 changed files with 68595 additions and 2 deletions
542
2020TPCAppNoDFU.cydsn/system_psoc6_cm4.c
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542
2020TPCAppNoDFU.cydsn/system_psoc6_cm4.c
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/***************************************************************************//**
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* \file system_psoc6_cm4.c
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* \version 2.20
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*
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* The device system-source file.
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#include <stdbool.h>
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#include "system_psoc6.h"
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#include "cy_device.h"
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#include "cy_device_headers.h"
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#include "cy_syslib.h"
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#include "cy_wdt.h"
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#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
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#include "cy_ipc_sema.h"
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#include "cy_ipc_pipe.h"
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#include "cy_ipc_drv.h"
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#if defined(CY_DEVICE_PSOC6ABLE2)
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#include "cy_flash.h"
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#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
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#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
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/*******************************************************************************
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* SystemCoreClockUpdate()
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*******************************************************************************/
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/** Default HFClk frequency in Hz */
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#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL)
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/** Default PeriClk frequency in Hz */
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#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL)
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/** Default SlowClk system core frequency in Hz */
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#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL)
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/** IMO frequency in Hz */
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#define CY_CLK_IMO_FREQ_HZ (8000000UL)
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/** HVILO frequency in Hz */
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#define CY_CLK_HVILO_FREQ_HZ (32000UL)
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/** PILO frequency in Hz */
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#define CY_CLK_PILO_FREQ_HZ (32768UL)
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/** WCO frequency in Hz */
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#define CY_CLK_WCO_FREQ_HZ (32768UL)
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/** ALTLF frequency in Hz */
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#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
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/**
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* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
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* which is the system clock frequency supplied to the SysTick timer and the
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* processor core clock.
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* This variable implements CMSIS Core global variable.
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* Refer to the [CMSIS documentation]
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* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
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* for more details.
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* This variable can be used by debuggers to query the frequency
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* of the debug timer or to configure the trace clock speed.
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*
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* \attention Compilers must be configured to avoid removing this variable in case
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* the application program is not using it. Debugging systems require the variable
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* to be physically present in memory so that it can be examined to configure the debugger. */
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uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
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/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
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uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
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/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
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uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
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/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
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#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
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uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
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#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
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/* SCB->CPACR */
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#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
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/*******************************************************************************
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* SystemInit()
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*******************************************************************************/
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/* CLK_FLL_CONFIG default values */
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#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
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#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
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#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
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#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
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/*******************************************************************************
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* SystemCoreClockUpdate (void)
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*******************************************************************************/
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/* Do not use these definitions directly in your application */
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#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
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#define CY_DELAY_1K_THRESHOLD (1000u)
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#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
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#define CY_DELAY_1M_THRESHOLD (1000000u)
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#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
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uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
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uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
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CY_DELAY_1K_THRESHOLD;
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uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
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CY_DELAY_1M_THRESHOLD);
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uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
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((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
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#define CY_ROOT_PATH_SRC_IMO (0UL)
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#define CY_ROOT_PATH_SRC_EXT (1UL)
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#if (SRSS_ECO_PRESENT == 1U)
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#define CY_ROOT_PATH_SRC_ECO (2UL)
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#endif /* (SRSS_ECO_PRESENT == 1U) */
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#if (SRSS_ALTHF_PRESENT == 1U)
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#define CY_ROOT_PATH_SRC_ALTHF (3UL)
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#endif /* (SRSS_ALTHF_PRESENT == 1U) */
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#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
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#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
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#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
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#if (SRSS_ALTLF_PRESENT == 1U)
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#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
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#endif /* (SRSS_ALTLF_PRESENT == 1U) */
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#if (SRSS_PILO_PRESENT == 1U)
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#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
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#endif /* (SRSS_PILO_PRESENT == 1U) */
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/*******************************************************************************
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* Function Name: SystemInit
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****************************************************************************//**
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* \cond
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* Initializes the system:
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* - Restores FLL registers to the default state for single core devices.
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* - Unlocks and disables WDT.
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* - Calls Cy_PDL_Init() function to define the driver library.
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* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
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* - Calls \ref SystemCoreClockUpdate().
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* \endcond
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*******************************************************************************/
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void SystemInit(void)
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{
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Cy_PDL_Init(CY_DEVICE_CFG);
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#ifdef __CM0P_PRESENT
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#if (__CM0P_PRESENT == 0)
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/* Restore FLL registers to the default state as they are not restored by the ROM code */
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uint32_t copy = SRSS->CLK_FLL_CONFIG;
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copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
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SRSS->CLK_FLL_CONFIG = copy;
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copy = SRSS->CLK_ROOT_SELECT[0u];
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copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
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SRSS->CLK_ROOT_SELECT[0u] = copy;
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SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
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SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
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SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
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SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
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/* Unlock and disable WDT */
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Cy_WDT_Unlock();
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Cy_WDT_Disable();
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#endif /* (__CM0P_PRESENT == 0) */
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#endif /* __CM0P_PRESENT */
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Cy_SystemInit();
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SystemCoreClockUpdate();
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#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
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#ifdef __CM0P_PRESENT
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#if (__CM0P_PRESENT == 0)
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/* Allocate and initialize semaphores for the system operations. */
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static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
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(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
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#else
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(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
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#endif /* (__CM0P_PRESENT) */
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#else
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(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
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#endif /* __CM0P_PRESENT */
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/********************************************************************************
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*
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* Initializes the system pipes. The system pipes are used by BLE and Flash.
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*
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* If the default startup file is not used, or SystemInit() is not called in your
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* project, call the following three functions prior to executing any flash or
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* EmEEPROM write or erase operation:
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* -# Cy_IPC_Sema_Init()
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* -# Cy_IPC_Pipe_Config()
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* -# Cy_IPC_Pipe_Init()
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* -# Cy_Flash_Init()
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*
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*******************************************************************************/
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/* Create an array of endpoint structures */
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static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
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Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
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static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
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static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
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{
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/* .ep0ConfigData */
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{
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/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
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/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
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/* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
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/* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
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/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
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},
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/* .ep1ConfigData */
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{
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/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
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/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
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/* .ipcNotifierMuxNumber */ 0u,
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/* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
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/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
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},
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/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
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/* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
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/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
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};
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if (cy_device->flashPipeRequired != 0u)
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{
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Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
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}
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#if defined(CY_DEVICE_PSOC6ABLE2)
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Cy_Flash_Init();
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#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
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#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
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}
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/*******************************************************************************
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* Function Name: Cy_SystemInit
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****************************************************************************//**
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*
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* The function is called during device startup. Once project compiled as part of
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* the PSoC Creator project, the Cy_SystemInit() function is generated by the
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* PSoC Creator.
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*
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* The function generated by PSoC Creator performs all of the necessary device
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* configuration based on the design settings. This includes settings from the
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* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
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* configuration that is necessary.
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*
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*******************************************************************************/
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__WEAK void Cy_SystemInit(void)
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{
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/* Empty weak function. The actual implementation to be in the PSoC Creator
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* generated strong function.
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*/
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}
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/*******************************************************************************
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* Function Name: SystemCoreClockUpdate
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****************************************************************************//**
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*
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* Gets core clock frequency and updates \ref SystemCoreClock, \ref
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* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
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*
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* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
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* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
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*
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*******************************************************************************/
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void SystemCoreClockUpdate (void)
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{
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uint32_t srcFreqHz;
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uint32_t pathFreqHz;
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uint32_t fastClkDiv;
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uint32_t periClkDiv;
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uint32_t rootPath;
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uint32_t srcClk;
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/* Get root path clock for the high-frequency clock # 0 */
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rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
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/* Get source of the root path clock */
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srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
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/* Get frequency of the source */
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switch (srcClk)
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{
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case CY_ROOT_PATH_SRC_IMO:
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srcFreqHz = CY_CLK_IMO_FREQ_HZ;
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break;
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case CY_ROOT_PATH_SRC_EXT:
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srcFreqHz = CY_CLK_EXT_FREQ_HZ;
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break;
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#if (SRSS_ECO_PRESENT == 1U)
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case CY_ROOT_PATH_SRC_ECO:
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srcFreqHz = CY_CLK_ECO_FREQ_HZ;
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break;
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#endif /* (SRSS_ECO_PRESENT == 1U) */
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#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
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case CY_ROOT_PATH_SRC_ALTHF:
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srcFreqHz = cy_BleEcoClockFreqHz;
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break;
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#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
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case CY_ROOT_PATH_SRC_DSI_MUX:
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{
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uint32_t dsi_src;
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dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
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switch (dsi_src)
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{
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case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
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srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
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break;
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case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
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srcFreqHz = CY_CLK_WCO_FREQ_HZ;
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break;
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#if (SRSS_ALTLF_PRESENT == 1U)
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case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
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srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
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break;
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#endif /* (SRSS_ALTLF_PRESENT == 1U) */
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#if (SRSS_PILO_PRESENT == 1U)
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case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
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srcFreqHz = CY_CLK_PILO_FREQ_HZ;
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break;
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#endif /* (SRSS_PILO_PRESENT == 1U) */
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default:
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srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
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break;
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}
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}
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break;
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default:
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srcFreqHz = CY_CLK_EXT_FREQ_HZ;
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break;
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}
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if (rootPath == 0UL)
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{
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/* FLL */
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bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
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bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
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bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
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(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
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if ((fllOutputAuto && fllLocked) || fllOutputOutput)
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{
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uint32_t fllMult;
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uint32_t refDiv;
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uint32_t outputDiv;
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fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
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refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
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outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
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pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
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}
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else
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{
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pathFreqHz = srcFreqHz;
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}
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}
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else if (rootPath == 1UL)
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{
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/* PLL */
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bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL]));
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bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]));
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bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) ||
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(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])));
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if ((pllOutputAuto && pllLocked) || pllOutputOutput)
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{
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uint32_t feedbackDiv;
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uint32_t referenceDiv;
|
||||
uint32_t outputDiv;
|
||||
|
||||
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
|
||||
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
|
||||
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
|
||||
|
||||
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
pathFreqHz = srcFreqHz;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Direct */
|
||||
pathFreqHz = srcFreqHz;
|
||||
}
|
||||
|
||||
/* Get frequency after hf_clk pre-divider */
|
||||
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
|
||||
cy_Hfclk0FreqHz = pathFreqHz;
|
||||
|
||||
/* Fast Clock Divider */
|
||||
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
|
||||
|
||||
/* Peripheral Clock Divider */
|
||||
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
|
||||
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
|
||||
|
||||
pathFreqHz = pathFreqHz / fastClkDiv;
|
||||
SystemCoreClock = pathFreqHz;
|
||||
|
||||
/* Sets clock frequency for Delay API */
|
||||
cy_delayFreqHz = SystemCoreClock;
|
||||
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
|
||||
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
|
||||
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SystemInitFpuEnable
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Enables the FPU if it is used. The function is called from the startup file.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SystemInitFpuEnable(void)
|
||||
{
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
uint32_t interruptState;
|
||||
interruptState = Cy_SysLib_EnterCriticalSection();
|
||||
SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
|
||||
__DSB();
|
||||
__ISB();
|
||||
Cy_SysLib_ExitCriticalSection(interruptState);
|
||||
#endif /* (__FPU_USED) && (__FPU_USED == 1U) */
|
||||
}
|
||||
|
||||
|
||||
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SysIpcPipeIsrCm4
|
||||
****************************************************************************//**
|
||||
*
|
||||
* This is the interrupt service routine for the system pipe.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SysIpcPipeIsrCm4(void)
|
||||
{
|
||||
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_MemorySymbols
|
||||
****************************************************************************//**
|
||||
*
|
||||
* The intention of the function is to declare boundaries of the memories for the
|
||||
* MDK compilers. For the rest of the supported compilers, this is done using
|
||||
* linker configuration files. The following symbols used by the cymcuelftool.
|
||||
*
|
||||
*******************************************************************************/
|
||||
#if defined (__ARMCC_VERSION)
|
||||
__asm void Cy_MemorySymbols(void)
|
||||
{
|
||||
/* Flash */
|
||||
EXPORT __cy_memory_0_start
|
||||
EXPORT __cy_memory_0_length
|
||||
EXPORT __cy_memory_0_row_size
|
||||
|
||||
/* Working Flash */
|
||||
EXPORT __cy_memory_1_start
|
||||
EXPORT __cy_memory_1_length
|
||||
EXPORT __cy_memory_1_row_size
|
||||
|
||||
/* Supervisory Flash */
|
||||
EXPORT __cy_memory_2_start
|
||||
EXPORT __cy_memory_2_length
|
||||
EXPORT __cy_memory_2_row_size
|
||||
|
||||
/* XIP */
|
||||
EXPORT __cy_memory_3_start
|
||||
EXPORT __cy_memory_3_length
|
||||
EXPORT __cy_memory_3_row_size
|
||||
|
||||
/* eFuse */
|
||||
EXPORT __cy_memory_4_start
|
||||
EXPORT __cy_memory_4_length
|
||||
EXPORT __cy_memory_4_row_size
|
||||
|
||||
/* Flash */
|
||||
__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
|
||||
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
|
||||
__cy_memory_0_row_size EQU 0x200
|
||||
|
||||
/* Flash region for EEPROM emulation */
|
||||
__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
|
||||
__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
|
||||
__cy_memory_1_row_size EQU 0x200
|
||||
|
||||
/* Supervisory Flash */
|
||||
__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
|
||||
__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
|
||||
__cy_memory_2_row_size EQU 0x200
|
||||
|
||||
/* XIP */
|
||||
__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
|
||||
__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
|
||||
__cy_memory_3_row_size EQU 0x200
|
||||
|
||||
/* eFuse */
|
||||
__cy_memory_4_start EQU __cpp(0x90700000)
|
||||
__cy_memory_4_length EQU __cpp(0x100000)
|
||||
__cy_memory_4_row_size EQU __cpp(1)
|
||||
}
|
||||
|
||||
#endif /* defined (__ARMCC_VERSION) */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
Loading…
Add table
Add a link
Reference in a new issue