From dac4af8d252809b83f01be48247f2bd90db60757 Mon Sep 17 00:00:00 2001 From: Joe Kearney Date: Sat, 1 Feb 2025 19:22:12 -0600 Subject: [PATCH] Initial public release. --- .gitignore | 31 + .gitmodules | 6 + 2020TPC Nonvolatile Memory.xlsx | Bin 0 -> 7818 bytes 2020TPC.cywrk | 24 + 2020TPCApp0.cydsn/2020TPCApp0.cydwr | 711 ++ 2020TPCApp0.cydsn/2020TPCApp0.cyprj | 3572 +++++++++ 2020TPCApp0.cydsn/TopDesign/TopDesign.cysch | Bin 0 -> 132677 bytes 2020TPCApp0.cydsn/cy8c6xx7_cm0plus.icf | 218 + 2020TPCApp0.cydsn/cy8c6xx7_cm0plus.ld | 402 + 2020TPCApp0.cydsn/cy8c6xx7_cm0plus.scat | 207 + 2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.icf | 219 + 2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.ld | 408 ++ 2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.scat | 213 + 2020TPCApp0.cydsn/cy_ble_config.h | 66 + 2020TPCApp0.cydsn/cy_si_config.h | 131 + 2020TPCApp0.cydsn/cy_si_keystorage.c | 198 + 2020TPCApp0.cydsn/cy_si_keystorage.h | 110 + 2020TPCApp0.cydsn/debug.c | 162 + 2020TPCApp0.cydsn/debug.h | 82 + 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+1,31 @@ +# Ignore file for the KTag 2020TPC PSoC Creator workspace. + +*.log +*/codegentemp/* +*/CortexM0p/* +*/CortexM4/ARM_GCC_541/* +*/Export/* +*/Generated_Source/* +/2020TPC.cywrk.* + +/2020TPCApp0.cydsn/2020TPCApp0_timing.html +/2020TPCApp0.cydsn/2020TPCApp0.cycdx +/2020TPCApp0.cydsn/2020TPCApp0.cyfit +/2020TPCApp0.cydsn/2020TPCApp0.cyprj.* +/2020TPCApp0.cydsn/2020TPCApp0.rpt + +/2020TPCApp1.cydsn/2020TPCApp1_timing.html +/2020TPCApp1.cydsn/2020TPCApp1.cycdx +/2020TPCApp1.cydsn/2020TPCApp1.cyfit +/2020TPCApp1.cydsn/2020TPCApp1.cyprj.* +/2020TPCApp1.cydsn/2020TPCApp1.rpt +/2020TPCApp1.cydsn/2020TPCApp1.svd + +/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU_timing.html +/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU.cycdx +/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU.cyfit +/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU.cyprj.* +/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU.rpt +/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU.svd + +/Keys/*.txt diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..5794282 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b/2020TPCApp0.cydsn/cy8c6xx7_cm0plus.icf new file mode 100644 index 0000000..71ba887 --- /dev/null +++ b/2020TPCApp0.cydsn/cy8c6xx7_cm0plus.icf @@ -0,0 +1,218 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.icf +* \version 2.20 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCApp0.cydsn/cy8c6xx7_cm0plus.ld b/2020TPCApp0.cydsn/cy8c6xx7_cm0plus.ld new file mode 100644 index 0000000..1f50d64 --- /dev/null +++ b/2020TPCApp0.cydsn/cy8c6xx7_cm0plus.ld @@ -0,0 +1,402 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.ld +* \version 2.20 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x24000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCApp0.cydsn/cy8c6xx7_cm0plus.scat b/2020TPCApp0.cydsn/cy8c6xx7_cm0plus.scat new file mode 100644 index 0000000..6c49340 --- /dev/null +++ b/2020TPCApp0.cydsn/cy8c6xx7_cm0plus.scat @@ -0,0 +1,207 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm0plus.scat +;* \version 2.20 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00024000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_FLASH FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.icf b/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.icf new file mode 100644 index 0000000..0f831e7 --- /dev/null +++ b/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,219 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.icf +* \version 2.20 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +place at start of IROM1_region { block RO }; +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.ld b/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.ld new file mode 100644 index 0000000..90f6fca --- /dev/null +++ b/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,408 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.20 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x23800 + flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.scat b/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.scat new file mode 100644 index 0000000..d45ccea --- /dev/null +++ b/2020TPCApp0.cydsn/cy8c6xx7_cm4_dual.scat @@ -0,0 +1,213 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.scat +;* \version 2.20 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08024000 +#define RAM_SIZE 0x00023800 +; Flash +#define FLASH_START 0x10080000 +#define FLASH_SIZE 0x00080000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_FLASH FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/cy_ble_config.h b/2020TPCApp0.cydsn/cy_ble_config.h new file mode 100644 index 0000000..2f382ef --- /dev/null +++ b/2020TPCApp0.cydsn/cy_ble_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** +* \file cy_ble_config.h +* \version 2.80 +* +* \brief +* The user BLE configuration file. Allows redefining the configuration #define(s) +* generated by the BLE customizer. +* +******************************************************************************** +* \copyright +* Copyright 2017-2023, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef CY_BLE_CONF_H +#define CY_BLE_CONF_H + +#include "ble/cy_ble_defines.h" + +/** + * The BLE_config.h file is generated by the BLE customizer and includes all common + * configuration defines (CY_BLE_CONFIG_***). + */ +#include "BLE_config.h" + +#include +#ifndef CY_IP_MXBLESS + #error "The BLE middleware is not supported on this device" +#endif + +/** + * The BLE Interrupt Notification Feature - Exposes BLE interrupt notifications + * to an application that indicates a different link layer and radio state + * transition to the user from the BLESS interrupt context. + * This callback is triggered at the beginning of a received BLESS interrupt + * (based on the registered interrupt mask). After this feature is enabled, + * the following APIs are available: + * Cy_BLE_RegisterInterruptCallback() and Cy_BLE_UnRegisterInterruptCallback(). + * + * The valid value: 1u - enable / 0u - disable. + * + * BLE Dual mode requires an additional define IPC channel and IPC Interrupt + * structure to send notification from the controller core to host core. + * Use the following defines: + * #define CY_BLE_INTR_NOTIFY_IPC_CHAN (9..15) + * #define CY_BLE_INTR_NOTIFY_IPC_INTR (9..15) + * #define CY_BLE_INTR_NOTIFY_IPC_INTR_PRIOR (0..7) + */ +#define CY_BLE_INTR_NOTIFY_FEATURE_ENABLE (0u) + + +/** + * To redefine the config #define(s) generated by the BLE customizer, + * use the construction #undef... #define. + * + * #undef CY_BLE_CONFIG_ENABLE_LL_PRIVACY + * #define CY_BLE_CONFIG_ENABLE_LL_PRIVACY (1u) + * + */ + + +#endif /* !defined(CY_BLE_CONF_H)*/ + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/cy_si_config.h b/2020TPCApp0.cydsn/cy_si_config.h new file mode 100644 index 0000000..aa539d7 --- /dev/null +++ b/2020TPCApp0.cydsn/cy_si_config.h @@ -0,0 +1,131 @@ +/***************************************************************************//** +* \file cy_si_config.h +* \version 1.0.1 +* +* \brief +* Definitions for Secure Image. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY_SI_CONFIG_H_ +#define _CY_SI_CONFIG_H_ + +#include "cy_si_keystorage.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Macros +***************************************/ +/* +* Macros to define the secure image version and ID. +*/ +#define CY_SI_VERSION_MAJOR 1UL /**< Major version */ +#define CY_SI_VERSION_MINOR 0UL /**< Minor version */ +#define CY_SI_APP_VERSION ((CY_SI_VERSION_MAJOR << 24u) | (CY_SI_VERSION_MINOR << 16u)) /**< App Version */ +#define CY_SI_ID CY_PDL_DRV_ID(0x38u) /**< Secure Image ID */ +#define CY_SI_ID_INFO (uint32_t)( CY_SI_ID | CY_PDL_STATUS_INFO ) /**< Secure Image INFO ID */ +#define CY_SI_ID_WARNING (uint32_t)( CY_SI_ID | CY_PDL_STATUS_WARNING) /**< Secure Image WARNING ID */ +#define CY_SI_ID_ERROR (uint32_t)( CY_SI_ID | CY_PDL_STATUS_ERROR) /**< Secure Image ERROR ID */ +#define CY_SI_CHECKID(val) ((uint32_t)(val) & (CY_PDL_MODULE_ID_Msk << CY_PDL_MODULE_ID_Pos)) /**< Check ID macro */ + +/* +* Clock selection for Flash boot execution. +*/ +#define CY_SI_FLASHBOOT_CLK_25MHZ (0x00UL) /**< 25MHz clock selection for Flashboot */ +#define CY_SI_FLASHBOOT_CLK_8MHZ (0x01UL) /**< 8MHz clock selection for Flashboot */ +#define CY_SI_FLASHBOOT_CLK_50MHZ (0x02UL) /**< 50MHz clock selection for Flashboot */ + +/* +* Debugger wait window selection for Flash boot execution. +*/ +#define CY_SI_FLASHBOOT_WAIT_20MS (0x00UL) /**< 20ms debugger wait window for Flashboot */ +#define CY_SI_FLASHBOOT_WAIT_10MS (0x01UL) /**< 10ms debugger wait window for Flashboot */ +#define CY_SI_FLASHBOOT_WAIT_1MS (0x02UL) /**< 1ms debugger wait window for Flashboot */ +#define CY_SI_FLASHBOOT_WAIT_0MS (0x03UL) /**< 0ms debugger wait window for Flashboot */ +#define CY_SI_FLASHBOOT_WAIT_100MS (0x04UL) /**< 100ms debugger wait window for Flashboot */ + +/* +* Flash boot validation selection in chip NORMAL mode. +*/ +#define CY_SI_FLASHBOOT_VALIDATE_NO (0x00UL) /**< Do not validate app1 in NORMAL mode */ +#define CY_SI_FLASHBOOT_VALIDATE_YES (0x01UL) /**< Validate app1 in NORMAL mode */ + +/* +* Application format selection for secure boot. +*/ +#define CY_SI_APP_FORMAT_BASIC (0UL) /**< Basic application format (no header) */ +#define CY_SI_APP_FORMAT_CYPRESS (1UL) /**< Cypress application format (Cypress header) */ + + +/* +* Application type selection for secure boot. +*/ +#define CY_SI_APP_ID_FLASHBOOT (0x8001UL) /**< Flash boot ID Type */ +#define CY_SI_APP_ID_SECUREIMG (0x8002UL) /**< Secure image ID Type */ +#define CY_SI_APP_ID_BOOTLOADER (0x8003UL) /**< Bootloader ID Type */ + + +/*************************************** +* Constants +***************************************/ +#define CY_ARM_CM0P_CPUID (0xC6000000u) /** CM0+ partNo value from ARM CPUID[15:4] register shifted to [31:20] bits */ +#define CY_ARM_CM4_CPUID (0xC2400000u) /** CM4 partNo value from ARM CPUID[15:4] register shifted to [31:20] bits */ + +#define CY_SI_TOC_FLAGS_CLOCKS_MASK (0x00000003UL) /**< Mask for Flashboot clock selection */ +#define CY_SI_TOC_FLAGS_CLOCKS_POS (0UL) /**< Bit position of Flashboot clock selection */ +#define CY_SI_TOC_FLAGS_DELAY_MASK (0x0000001CUL) /**< Mask for Flashboot wait window selection */ +#define CY_SI_TOC_FLAGS_DELAY_POS (2UL) /**< Bit position of Flashboot wait window selection */ +#define CY_SI_TOC_FLAGS_APP_VERIFY_MASK (0x80000000UL) /**< Mask for Flashboot NORMAL mode app1 validation */ +#define CY_SI_TOC_FLAGS_APP_VERIFY_POS (31UL) /**< Bit position of Flashboot NORMAL mode app1 validation */ + +#define CY_SI_TOC2_MAGICNUMBER (0x01211220UL) /**< TOC2 identifier */ + +/*************************************** +* Structs +***************************************/ +/** Table of Content structure */ +typedef struct{ + volatile uint32_t objSize; /**< Object size (Bytes) */ + volatile uint32_t magicNum; /**< TOC ID (magic number) */ + volatile uint32_t userKeyAddr; /**< Secure key address in user Flash */ + volatile uint32_t smifCfgAddr; /**< SMIF configuration structure */ + volatile uint32_t appAddr1; /**< First user application object address */ + volatile uint32_t appFormat1; /**< First user application format */ + volatile uint32_t appAddr2; /**< Second user application object address */ + volatile uint32_t appFormat2; /**< Second user application format */ + volatile uint32_t shashObj; /**< Number of additional objects to be verified (S-HASH) */ + volatile uint32_t sigKeyAddr; /**< Signature verification key address */ + volatile uint32_t addObj[116]; /**< Additional objects to include in S-HASH */ + volatile uint32_t tocFlags; /**< Flags in TOC to control Flash boot options */ + volatile uint32_t crc; /**< CRC16-CCITT */ +}cy_stc_si_toc_t; + +/** User application header in Cypress format */ +typedef struct{ + volatile uint32_t objSize; /**< Object size (Bytes) */ + volatile uint32_t appId; /**< Application ID/version */ + volatile uint32_t appAttributes; /**< Attributes (reserved for future use) */ + volatile uint32_t numCores; /**< Number of cores */ + volatile uint32_t core0Vt; /**< (CM0+)VT offset - offset to the vector table from that entry */ + volatile uint32_t core1Vt; /**< (CM4)VT offset - offset to the vector table from that entry */ + volatile uint32_t core0Id; /**< CM0+ core ID */ + volatile uint32_t core1Id; /**< CM4 core ID */ +}cy_stc_user_appheader_t; + + +#if defined(__cplusplus) +} +#endif + +#endif /* _CY_SI_CONFIG_H_ */ + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/cy_si_keystorage.c b/2020TPCApp0.cydsn/cy_si_keystorage.c new file mode 100644 index 0000000..b88079d --- /dev/null +++ b/2020TPCApp0.cydsn/cy_si_keystorage.c @@ -0,0 +1,198 @@ +/***************************************************************************//** +* \file cy_si_keystorage.c +* \version 1.00 +* +* \brief +* Secure key storage for the secure image. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cy_si_keystorage.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** Secure Key Storage (Note: Ensure that the alignment matches the Protection unit configuration) */ +CY_ALIGN(1024) __USED const uint8_t CySecureKeyStorage[CY_SI_SECURE_KEY_ARRAY_SIZE][CY_SI_SECURE_KEY_LENGTH] = { + {0x00u}, /* Insert user key #1 values */ + {0x00u}, /* Insert user key #2 values */ + {0x00u}, /* Insert user key #3 values */ + {0x00u} /* Insert user key #4 values */ +}; + +/** Public key in SFlash */ +CY_SECTION(".cy_sflash_public_key") __USED const cy_si_stc_public_key_t cy_publicKey = +{ + .objSize = sizeof(cy_si_stc_public_key_t), + .signatureScheme = CY_SI_PUBLIC_KEY_RSA_2048, + .publicKeyStruct = + { + .moduloAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, moduloData), + .moduloSize = CY_SI_PUBLIC_KEY_SIZEOF_BYTE * CY_SI_PUBLIC_KEY_MODULOLENGTH, + .expAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, expData), + .expSize = CY_SI_PUBLIC_KEY_SIZEOF_BYTE * CY_SI_PUBLIC_KEY_EXPLENGTH, + .barrettAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, barrettData), + .inverseModuloAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, inverseModuloData), + .rBarAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, rBarData), + }, + /* Replace key data from this point */ + .moduloData = + { + 0x0Du, 0x10u, 0x58u, 0x3Fu, 0x4Fu, 0x25u, 0x70u, 0x63u, + 0x6Du, 0x3Bu, 0xE6u, 0x10u, 0x9Eu, 0x7Cu, 0x7Cu, 0x9Cu, + 0x02u, 0x8Bu, 0x43u, 0x07u, 0x61u, 0x91u, 0xF6u, 0xBFu, + 0x12u, 0x7Cu, 0x2Bu, 0xDAu, 0x45u, 0xD5u, 0x75u, 0xBEu, + 0xB5u, 0xF1u, 0xBDu, 0x36u, 0x3Au, 0xC1u, 0xD1u, 0x39u, + 0x20u, 0x11u, 0x99u, 0x22u, 0x2Fu, 0xE8u, 0xFEu, 0x98u, + 0xFBu, 0xCDu, 0x34u, 0xD4u, 0xE2u, 0x2Cu, 0xC5u, 0x7Cu, + 0xC5u, 0x50u, 0x62u, 0xFFu, 0xFDu, 0x61u, 0x14u, 0x90u, + 0xFAu, 0x43u, 0xBDu, 0xADu, 0xA3u, 0xD5u, 0x86u, 0x85u, + 0x4Du, 0xF1u, 0x24u, 0x62u, 0x5Au, 0xECu, 0x87u, 0x4Du, + 0xD0u, 0x18u, 0xB0u, 0xE1u, 0x4Fu, 0x40u, 0xDEu, 0x87u, + 0xBBu, 0x74u, 0xC5u, 0x5Du, 0x48u, 0x90u, 0x26u, 0x68u, + 0x5Cu, 0xECu, 0xC3u, 0x5Cu, 0xC7u, 0x03u, 0x8Au, 0x05u, + 0x2Eu, 0x37u, 0xB8u, 0xA0u, 0x05u, 0xC5u, 0x21u, 0x0Fu, + 0x76u, 0x9Cu, 0xEEu, 0x19u, 0x4Cu, 0x2Eu, 0x89u, 0xA2u, + 0x21u, 0x44u, 0x61u, 0x9Fu, 0x7Fu, 0xD2u, 0x51u, 0x72u, + 0xABu, 0x2Cu, 0xA5u, 0xC6u, 0x7Cu, 0x0Au, 0x9Bu, 0x06u, + 0x14u, 0xECu, 0x91u, 0x3Du, 0x5Eu, 0x08u, 0x71u, 0x6Au, + 0xFEu, 0xABu, 0x3Eu, 0x1Bu, 0x99u, 0x3Cu, 0xF0u, 0x12u, + 0x57u, 0x0Cu, 0xF2u, 0x42u, 0x78u, 0xA5u, 0x3Bu, 0xAAu, + 0x49u, 0x98u, 0x03u, 0x8Eu, 0x0Fu, 0x5Au, 0xC9u, 0xFCu, + 0x26u, 0xC9u, 0x93u, 0xB8u, 0xB8u, 0xEBu, 0x6Fu, 0xF1u, + 0x65u, 0x78u, 0x43u, 0x0Au, 0xE5u, 0xFBu, 0x2Bu, 0xCCu, + 0x8Bu, 0x2Cu, 0x31u, 0x0Du, 0xE1u, 0x49u, 0x06u, 0x25u, + 0xE3u, 0xFAu, 0x92u, 0x7Fu, 0xC7u, 0x96u, 0x35u, 0x17u, + 0x2Cu, 0xEEu, 0xEEu, 0x40u, 0xC1u, 0x18u, 0x1Cu, 0x5Cu, + 0x45u, 0x4Du, 0xE9u, 0xB5u, 0xFDu, 0x23u, 0x60u, 0x14u, + 0x5Fu, 0x78u, 0x88u, 0xB9u, 0x17u, 0xAAu, 0xD5u, 0xB4u, + 0x68u, 0xCCu, 0x5Cu, 0xE2u, 0x3Fu, 0xD7u, 0xD4u, 0x6Eu, + 0x29u, 0x2Au, 0xD7u, 0x6Fu, 0xE8u, 0x89u, 0xCBu, 0xE3u, + 0x97u, 0x54u, 0xBCu, 0x4Eu, 0x85u, 0xA7u, 0x63u, 0xAFu, + 0x8Au, 0xFDu, 0xB8u, 0xF2u, 0x8Bu, 0xA4u, 0x36u, 0xD4u, + }, + .expData = + { + 0x01u, 0x00u, 0x01u, 0x00u, + }, + .barrettData = + { + 0x44u, 0x94u, 0xA5u, 0xF4u, 0x4Fu, 0xCEu, 0x24u, 0xD0u, + 0x3Bu, 0xDCu, 0x6Eu, 0x1Cu, 0x72u, 0xE8u, 0x6Fu, 0x5Eu, + 0x32u, 0x38u, 0x0Bu, 0xEDu, 0x73u, 0x8Bu, 0x7Cu, 0x1Cu, + 0x8Au, 0x03u, 0x36u, 0x88u, 0xB0u, 0x20u, 0x7Au, 0x90u, + 0x7Bu, 0x0Du, 0x44u, 0xA2u, 0xF2u, 0x21u, 0x4Fu, 0xD9u, + 0xA3u, 0x31u, 0xD8u, 0x87u, 0xD6u, 0xC8u, 0x36u, 0x94u, + 0x9Eu, 0x32u, 0x01u, 0xD6u, 0x18u, 0x2Fu, 0x77u, 0x0Cu, + 0xD6u, 0xAAu, 0x9Bu, 0x15u, 0xD8u, 0x50u, 0x6Eu, 0x88u, + 0xD7u, 0x28u, 0x11u, 0x84u, 0xE3u, 0x7Au, 0x52u, 0x08u, + 0x12u, 0xB8u, 0x05u, 0xECu, 0x70u, 0x1Fu, 0xD7u, 0x0Au, + 0x53u, 0x18u, 0x62u, 0xEBu, 0x37u, 0x16u, 0x04u, 0x6Du, + 0x86u, 0x4Cu, 0x8Au, 0x1Au, 0x6Eu, 0xCEu, 0x5Au, 0xD4u, + 0x8Fu, 0x17u, 0xEBu, 0x20u, 0x03u, 0x36u, 0xACu, 0xDDu, + 0x74u, 0x16u, 0xB4u, 0xE7u, 0x40u, 0x81u, 0x82u, 0x7Bu, + 0x2Fu, 0x31u, 0x95u, 0x64u, 0xFDu, 0x6Eu, 0x75u, 0xB7u, + 0x8Bu, 0xC8u, 0x6Au, 0x5Au, 0x48u, 0x28u, 0x5Du, 0xAEu, + 0x0Au, 0x11u, 0x86u, 0xC0u, 0x5Au, 0x4Du, 0xDBu, 0x3Eu, + 0x85u, 0xCCu, 0xDFu, 0x0Bu, 0x0Eu, 0xCBu, 0x52u, 0xB7u, + 0x45u, 0xACu, 0x42u, 0xC2u, 0x39u, 0x1Fu, 0xE1u, 0x18u, + 0xFDu, 0x7Bu, 0x77u, 0x7Fu, 0xE9u, 0xFCu, 0x25u, 0x8Cu, + 0xB7u, 0x9Eu, 0x38u, 0x6Fu, 0x22u, 0xE6u, 0x6Du, 0xC5u, + 0xB8u, 0x79u, 0x15u, 0x0Fu, 0xD1u, 0xAFu, 0x3Du, 0xC2u, + 0xB1u, 0xD8u, 0x4Fu, 0x81u, 0x09u, 0xB7u, 0x02u, 0xF0u, + 0xCDu, 0x65u, 0xF9u, 0xDFu, 0x0Bu, 0x74u, 0x14u, 0xDEu, + 0x17u, 0xDDu, 0xE6u, 0x85u, 0x19u, 0x7Eu, 0x49u, 0x2Fu, + 0x82u, 0xBAu, 0x73u, 0x1Du, 0x44u, 0x84u, 0x4Du, 0x5Cu, + 0x5Fu, 0x5Bu, 0x6Du, 0x78u, 0x73u, 0xA3u, 0x6Fu, 0x07u, + 0x76u, 0xF3u, 0xCDu, 0x52u, 0xE3u, 0xC3u, 0x89u, 0xE8u, + 0xA6u, 0x8Au, 0xFAu, 0xF5u, 0x21u, 0xC3u, 0x25u, 0x16u, + 0xD5u, 0x10u, 0xFDu, 0x30u, 0x5Du, 0xC5u, 0xB9u, 0xCAu, + 0x2Bu, 0x5Au, 0x92u, 0xEDu, 0xE5u, 0xF4u, 0x3Bu, 0xBFu, + 0x08u, 0x06u, 0x8Au, 0x75u, 0x88u, 0x36u, 0xD2u, 0x34u, + 0x01u, 0x00u, 0x00u, 0x00u, + }, + .inverseModuloData = + { + 0x3Bu, 0x41u, 0xE5u, 0xABu, 0xC8u, 0x05u, 0x56u, 0xBFu, + 0xF8u, 0xF5u, 0xE6u, 0x9Au, 0x46u, 0xF3u, 0x01u, 0x17u, + 0xBEu, 0x0Eu, 0x81u, 0x9Bu, 0x54u, 0x2Fu, 0x2Eu, 0x3Du, + 0xCBu, 0xA6u, 0xC3u, 0x35u, 0x02u, 0x18u, 0x38u, 0x1Au, + 0x38u, 0x15u, 0x54u, 0x0Eu, 0xA4u, 0xCDu, 0xD1u, 0xEDu, + 0x10u, 0x8Eu, 0x6Eu, 0xB9u, 0xCDu, 0x2Fu, 0x8Cu, 0xD6u, + 0x56u, 0x95u, 0xE8u, 0x14u, 0x79u, 0xC6u, 0x32u, 0x02u, + 0xA6u, 0x03u, 0xA1u, 0x8Du, 0x26u, 0x47u, 0xA1u, 0x99u, + 0x96u, 0xECu, 0xA3u, 0x77u, 0x22u, 0xEAu, 0x25u, 0x72u, + 0xBCu, 0xB8u, 0x77u, 0xE9u, 0x11u, 0x78u, 0x8Cu, 0x55u, + 0xB9u, 0x8Eu, 0x90u, 0x19u, 0x3Cu, 0xFFu, 0x9Fu, 0x40u, + 0x46u, 0x6Du, 0x51u, 0x22u, 0x21u, 0x15u, 0x5Cu, 0x4Fu, + 0xCAu, 0x15u, 0xB0u, 0xE8u, 0x67u, 0x0Au, 0x2Cu, 0x4Au, + 0xB1u, 0x77u, 0xFAu, 0xE6u, 0x3Cu, 0xA6u, 0x02u, 0x2Fu, + 0x16u, 0x96u, 0xE3u, 0xADu, 0x29u, 0x83u, 0x4Au, 0x88u, + 0xB1u, 0x6Bu, 0x13u, 0x38u, 0xA4u, 0xB0u, 0xE8u, 0xA6u, + 0xDBu, 0xA5u, 0xFBu, 0x36u, 0x7Au, 0x10u, 0xB1u, 0x75u, + 0x93u, 0x00u, 0xECu, 0x2Bu, 0x1Du, 0x86u, 0xE0u, 0x4Fu, + 0x85u, 0xC8u, 0x70u, 0x23u, 0xEBu, 0x96u, 0x87u, 0x70u, + 0x39u, 0x58u, 0x2Du, 0xAEu, 0xC3u, 0xC9u, 0xB6u, 0xFDu, + 0x27u, 0xEEu, 0x5Fu, 0x14u, 0x4Du, 0xB6u, 0xFAu, 0x55u, + 0xC3u, 0x2Cu, 0xFAu, 0x2Au, 0x60u, 0x67u, 0x37u, 0xBAu, + 0xB3u, 0xA0u, 0x17u, 0x9Du, 0x5Cu, 0xDCu, 0x0Au, 0x82u, + 0xFEu, 0x0Eu, 0xC9u, 0xE7u, 0x36u, 0x09u, 0x38u, 0xF3u, + 0xA7u, 0x83u, 0x9Au, 0x71u, 0xD2u, 0x07u, 0x2Bu, 0x4Fu, + 0x4Eu, 0xABu, 0x49u, 0xE8u, 0x0Eu, 0xE0u, 0x1Cu, 0x48u, + 0x73u, 0x87u, 0x62u, 0xC9u, 0x95u, 0x17u, 0xCCu, 0xE6u, + 0xECu, 0x34u, 0x18u, 0xE0u, 0xF0u, 0xCFu, 0x64u, 0x48u, + 0xD9u, 0x92u, 0x1Au, 0x82u, 0x21u, 0x68u, 0xBCu, 0x70u, + 0x31u, 0xA3u, 0xE0u, 0xC9u, 0xAEu, 0xC8u, 0x94u, 0x83u, + 0x4Du, 0x95u, 0x3Bu, 0x4Cu, 0x65u, 0x8Eu, 0xC7u, 0x46u, + 0x91u, 0x3Cu, 0xF4u, 0xD1u, 0x0Bu, 0xA5u, 0x64u, 0x13u, + }, + .rBarData = + { + 0xF3u, 0xEFu, 0xA7u, 0xC0u, 0xB0u, 0xDAu, 0x8Fu, 0x9Cu, + 0x92u, 0xC4u, 0x19u, 0xEFu, 0x61u, 0x83u, 0x83u, 0x63u, + 0xFDu, 0x74u, 0xBCu, 0xF8u, 0x9Eu, 0x6Eu, 0x09u, 0x40u, + 0xEDu, 0x83u, 0xD4u, 0x25u, 0xBAu, 0x2Au, 0x8Au, 0x41u, + 0x4Au, 0x0Eu, 0x42u, 0xC9u, 0xC5u, 0x3Eu, 0x2Eu, 0xC6u, + 0xDFu, 0xEEu, 0x66u, 0xDDu, 0xD0u, 0x17u, 0x01u, 0x67u, + 0x04u, 0x32u, 0xCBu, 0x2Bu, 0x1Du, 0xD3u, 0x3Au, 0x83u, + 0x3Au, 0xAFu, 0x9Du, 0x00u, 0x02u, 0x9Eu, 0xEBu, 0x6Fu, + 0x05u, 0xBCu, 0x42u, 0x52u, 0x5Cu, 0x2Au, 0x79u, 0x7Au, + 0xB2u, 0x0Eu, 0xDBu, 0x9Du, 0xA5u, 0x13u, 0x78u, 0xB2u, + 0x2Fu, 0xE7u, 0x4Fu, 0x1Eu, 0xB0u, 0xBFu, 0x21u, 0x78u, + 0x44u, 0x8Bu, 0x3Au, 0xA2u, 0xB7u, 0x6Fu, 0xD9u, 0x97u, + 0xA3u, 0x13u, 0x3Cu, 0xA3u, 0x38u, 0xFCu, 0x75u, 0xFAu, + 0xD1u, 0xC8u, 0x47u, 0x5Fu, 0xFAu, 0x3Au, 0xDEu, 0xF0u, + 0x89u, 0x63u, 0x11u, 0xE6u, 0xB3u, 0xD1u, 0x76u, 0x5Du, + 0xDEu, 0xBBu, 0x9Eu, 0x60u, 0x80u, 0x2Du, 0xAEu, 0x8Du, + 0x54u, 0xD3u, 0x5Au, 0x39u, 0x83u, 0xF5u, 0x64u, 0xF9u, + 0xEBu, 0x13u, 0x6Eu, 0xC2u, 0xA1u, 0xF7u, 0x8Eu, 0x95u, + 0x01u, 0x54u, 0xC1u, 0xE4u, 0x66u, 0xC3u, 0x0Fu, 0xEDu, + 0xA8u, 0xF3u, 0x0Du, 0xBDu, 0x87u, 0x5Au, 0xC4u, 0x55u, + 0xB6u, 0x67u, 0xFCu, 0x71u, 0xF0u, 0xA5u, 0x36u, 0x03u, + 0xD9u, 0x36u, 0x6Cu, 0x47u, 0x47u, 0x14u, 0x90u, 0x0Eu, + 0x9Au, 0x87u, 0xBCu, 0xF5u, 0x1Au, 0x04u, 0xD4u, 0x33u, + 0x74u, 0xD3u, 0xCEu, 0xF2u, 0x1Eu, 0xB6u, 0xF9u, 0xDAu, + 0x1Cu, 0x05u, 0x6Du, 0x80u, 0x38u, 0x69u, 0xCAu, 0xE8u, + 0xD3u, 0x11u, 0x11u, 0xBFu, 0x3Eu, 0xE7u, 0xE3u, 0xA3u, + 0xBAu, 0xB2u, 0x16u, 0x4Au, 0x02u, 0xDCu, 0x9Fu, 0xEBu, + 0xA0u, 0x87u, 0x77u, 0x46u, 0xE8u, 0x55u, 0x2Au, 0x4Bu, + 0x97u, 0x33u, 0xA3u, 0x1Du, 0xC0u, 0x28u, 0x2Bu, 0x91u, + 0xD6u, 0xD5u, 0x28u, 0x90u, 0x17u, 0x76u, 0x34u, 0x1Cu, + 0x68u, 0xABu, 0x43u, 0xB1u, 0x7Au, 0x58u, 0x9Cu, 0x50u, + 0x75u, 0x02u, 0x47u, 0x0Du, 0x74u, 0x5Bu, 0xC9u, 0x2Bu, + }, + /* End of key data */ +}; + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/cy_si_keystorage.h b/2020TPCApp0.cydsn/cy_si_keystorage.h new file mode 100644 index 0000000..7a0496f --- /dev/null +++ b/2020TPCApp0.cydsn/cy_si_keystorage.h @@ -0,0 +1,110 @@ +/***************************************************************************//** +* \file cy_si_keystorage.h +* \version 1.00 +* +* \brief +* Secure key storage header for the secure image. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY_KEY_STORAGE_H_ +#define _CY_KEY_STORAGE_H_ + +#include +#include +#include "syslib/cy_syslib.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Macros +***************************************/ + +/** \addtogroup group_secure_image_macro +* \{ +*/ + +/** \defgroup group_secure_image_userkey_macros User Key Macros +* Macros used to define the user-defined key array. +* \{ +*/ +#define CY_SI_SECURE_KEY_LENGTH (256u) /**< Key length (Bytes) */ +#define CY_SI_SECURE_KEY_ARRAY_SIZE (4u) /**< Number of Keys */ +/** \} group_secure_image_userkey_macros */ + +/** \defgroup group_secure_image_pubkey_macros Public Key Macros +* Macros used to define the Public key. +* \{ +*/ +#define CY_SI_PUBLIC_KEY_RSA_2048 (0UL) /**< RSASSA-PKCS1-v1_5-2048 signature scheme */ +#define CY_SI_PUBLIC_KEY_RSA_1024 (1UL) /**< RSASSA-PKCS1-v1_5-1024 signature scheme */ +#define CY_SI_PUBLIC_KEY_STRUCT_OFFSET (8UL) /**< Offset to public key struct in number of bytes */ +#define CY_SI_PUBLIC_KEY_MODULOLENGTH (256UL) /**< Modulus length of the RSA key */ +#define CY_SI_PUBLIC_KEY_EXPLENGTH (32UL) /**< Exponent length of the RSA key */ +#define CY_SI_PUBLIC_KEY_SIZEOF_BYTE (8UL) /**< Size of Byte in number of bits */ +/** \} group_secure_image_pubkey_macros */ + +/** \} group_secure_image_macro */ + + +/*************************************** +* Structs +***************************************/ + +/** +* \addtogroup group_secure_image_data_structures +* \{ +*/ + +/** Public key definition structure as expected by the Crypto driver */ +typedef struct +{ + uint32_t moduloAddr; /**< Address of the public key modulus */ + uint32_t moduloSize; /**< Size (bits) of the modulus part of the public key */ + uint32_t expAddr; /**< Address of the public key exponent */ + uint32_t expSize; /**< Size (bits) of the exponent part of the public key */ + uint32_t barrettAddr; /**< Address of the Barret coefficient */ + uint32_t inverseModuloAddr; /**< Address of the binary inverse modulo */ + uint32_t rBarAddr; /**< Address of the (2^moduloLength mod modulo) */ +} cy_si_stc_crypto_public_key_t; + +/** Public key structure */ +typedef struct +{ + uint32_t objSize; /**< Public key Object size */ + uint32_t signatureScheme; /**< Signature scheme */ + cy_si_stc_crypto_public_key_t publicKeyStruct; /**< Public key definition struct */ + uint8_t moduloData[CY_SI_PUBLIC_KEY_MODULOLENGTH]; /**< Modulo data */ + uint8_t expData[CY_SI_PUBLIC_KEY_EXPLENGTH]; /**< Exponent data */ + uint8_t barrettData[CY_SI_PUBLIC_KEY_MODULOLENGTH + 4UL]; /**< Barret coefficient data */ + uint8_t inverseModuloData[CY_SI_PUBLIC_KEY_MODULOLENGTH]; /**< Binary inverse modulo data */ + uint8_t rBarData[CY_SI_PUBLIC_KEY_MODULOLENGTH]; /**< 2^moduloLength mod modulo data */ +} cy_si_stc_public_key_t; + +/** \} group_secure_image_data_structures */ + + +/*************************************** +* Globals +***************************************/ +/** Secure Key Storage (Note: Ensure that the alignment matches the Protection unit configuration) */ +extern const uint8_t CySecureKeyStorage[CY_SI_SECURE_KEY_ARRAY_SIZE][CY_SI_SECURE_KEY_LENGTH]; + +/** Public key in SFlash */ +extern const cy_si_stc_public_key_t cy_publicKey; + +#if defined(__cplusplus) +} +#endif + +#endif + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/debug.c b/2020TPCApp0.cydsn/debug.c new file mode 100644 index 0000000..1ae42b1 --- /dev/null +++ b/2020TPCApp0.cydsn/debug.c @@ -0,0 +1,162 @@ +/******************************************************************************* +* File Name: debug.c +* +* Version: 1.0 +* +* Description: +* This file contains functions for printf functionality +* and LED status notification. +* +* Hardware Dependency: +* CY8CKIT-062 PSoC6 BLE Pioneer Kit +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "project.h" +#include "debug.h" + + +#if (DEBUG_UART_ENABLED == ENABLED) + +#if defined(__ARMCC_VERSION) + +/* For MDK/RVDS compiler revise fputc function for printf functionality */ +struct __FILE +{ + int handle; +}; + +enum +{ + STDIN_HANDLE, + STDOUT_HANDLE, + STDERR_HANDLE +}; + +FILE __stdin = {STDIN_HANDLE}; +FILE __stdout = {STDOUT_HANDLE}; +FILE __stderr = {STDERR_HANDLE}; + +int fputc(int ch, FILE *file) +{ + int ret = EOF; + + switch( file->handle ) + { + case STDOUT_HANDLE: + UART_DEB_PUT_CHAR(ch); + ret = ch ; + break ; + + case STDERR_HANDLE: + ret = ch ; + break ; + + default: + file = file; + break ; + } + return ret ; +} + +#elif defined (__ICCARM__) /* IAR */ + +/* For IAR compiler revise __write() function for printf functionality */ +size_t __write(int handle, const unsigned char * buffer, size_t size) +{ + size_t nChars = 0; + (void) handle; + + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we + * don't we just return. (Remember, "handle" == -1 means that all + * handles should be flushed.) + */ + return (0); + } + + for (/* Empty */; size != 0; --size) + { + UART_DEB_PUT_CHAR(*buffer); + ++buffer; + ++nChars; + } + + return (nChars); +} + +#else /* (__GNUC__) GCC */ + +/* For GCC compiler revise _write() function for printf functionality */ +int _write(int file, char *ptr, int len) +{ + int i; + file = file; + for (i = 0; i < len; i++) + { + UART_DEB_PUT_CHAR(*ptr); + ++ptr; + } + return len; +} + + +#endif /* (__ARMCC_VERSION) */ + +#endif /* DEBUG_UART_ENABLED == ENABLED */ + +#if (DEBUG_LED_ENABLED == ENABLED) + +void InitLED(void) +{ + #if CYDEV_VDD_MV >= RGB_LED_MIN_VOLTAGE_MV + Cy_GPIO_SetDrivemode(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, CY_GPIO_DM_STRONG_IN_OFF); + Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_OFF); + Cy_GPIO_SetDrivemode(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM, CY_GPIO_DM_STRONG_IN_OFF); + Cy_GPIO_Write(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM, LED_OFF); + #else + Cy_GPIO_SetDrivemode(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, CY_GPIO_DM_STRONG_IN_OFF); + Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_OFF); + #endif +} + +void HibernateLED(void) +{ + #if CYDEV_VDD_MV >= RGB_LED_MIN_VOLTAGE_MV + Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_ON); + Cy_GPIO_Write(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM, LED_OFF); + #else + Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_ON); + #endif +} + +void BlinkLED(void) +{ + #if CYDEV_VDD_MV >= RGB_LED_MIN_VOLTAGE_MV + Cy_GPIO_Inv(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM); + Cy_GPIO_Inv(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM); + #else + Cy_GPIO_Inv(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM); + #endif +} + +void ConnectedLED(void) +{ + #if CYDEV_VDD_MV >= RGB_LED_MIN_VOLTAGE_MV + Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_OFF); + Cy_GPIO_Write(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM, LED_OFF); + #else + Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_OFF); + #endif +} + +#endif /* DEBUG_LED == ENABLED */ + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/debug.h b/2020TPCApp0.cydsn/debug.h new file mode 100644 index 0000000..5637adb --- /dev/null +++ b/2020TPCApp0.cydsn/debug.h @@ -0,0 +1,82 @@ +/***************************************************************************//** +* \file debug.h +* +* \version 1.0 +* +* Contains the function prototypes and constants for the UART debugging +* and LED status notification. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "project.h" + +#define ENABLED (1u) +#define DISABLED (0u) + +/*************************************** +* Conditional Compilation Parameters +***************************************/ +#define DEBUG_UART_ENABLED ENABLED +#define DEBUG_LED_ENABLED ENABLED + +/*************************************** +* API Constants +***************************************/ +#define LED_ON (0u) +#define LED_OFF (1u) +#define RGB_LED_MIN_VOLTAGE_MV (2700u) +#define ADV_TIMER_TIMEOUT (1u) + +/*************************************** +* External Function Prototypes +***************************************/ +#if (DEBUG_LED_ENABLED) + +void InitLED(void); +void HibernateLED(void); +void BlinkLED(void); +void ConnectedLED(void); + +#else + +#define InitLED() +#define HibernateLED() +#define BlinkLED() +#define ConnectedLED() + +#endif +/*************************************** +* Macros +***************************************/ +#if (DEBUG_UART_ENABLED == ENABLED) + #define DBG_PRINTF(...) (printf(__VA_ARGS__)) + #define UART_DEB_PUT_CHAR(ch) while(0UL == UART_DEB_Put(ch)) + + __STATIC_INLINE char8 UART_DEB_GET_CHAR(void) + { + uint32 rec; + rec = UART_DEB_Get(); + return((rec == CY_SCB_UART_RX_NO_DATA) ? 0u : (char8)(rec & 0xff)); + } + + #define UART_DEB_GET_TX_BUFF_SIZE() ( UART_DEB_GetNumInTxFifo() ) + #define UART_START() ( UART_DEB_Start() ) +#else + #define DBG_PRINTF(...) + #define UART_DEB_PUT_CHAR(ch) + #define UART_DEB_GET_CHAR(ch) (0u) + #ifndef UART_DEB_GET_TX_FIFO_SR_VALID + #define UART_DEB_GET_TX_FIFO_SR_VALID (0u) + #endif + #define UART_DEB_GET_TX_BUFF_SIZE(...) (0u) + #define UART_START() +#endif /* (DEBUG_UART_ENABLED == ENABLED) */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/dfu_cm0p.icf b/2020TPCApp0.cydsn/dfu_cm0p.icf new file mode 100644 index 0000000..2495c11 --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_cm0p.icf @@ -0,0 +1,251 @@ +/***************************************************************************//** +* \file dfu_cm0p.icf +* \version 3.0 +* +* The linker file for the the IAR compiler. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case, you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ + + +/******************************************************************************* +* Start of CM4 and CM0+ linker script common region +*******************************************************************************/ + +/*-Memory Regions-*/ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + + +define memory mem with size = 4G; + +/* Memory regions for all applications are defined here */ +define region FLASH_app0_core0 = mem:[from 0x10000000 size 0x10000]; +define region FLASH_app0_core1 = mem:[from 0x10010000 size 0x10000]; +define region FLASH_app1_core0 = mem:[from 0x10040000 size 0x10000]; +define region FLASH_app1_core1 = mem:[from 0x10050000 size 0x10000]; + +/* +* The region for DFU SDK metadata +* when it is outside of any application +*/ +define region FLASH_boot_meta = mem:[from 0x100FFA00 size 0x200]; + + +/* eFuse */ +define region ROM_EFUSE = mem:[from 0x90700000 size 0x100000]; + +/* SFlash NAR */ +define region SFLASH_NAR = mem:[from 0x16001A00 size 0x200]; + +/* SFlash User Data */ +define region SFLASH_USER_DATA = mem:[from 0x16000800 size 0x800]; + +/* SFlash Public Key, 6 SFlash rows */ +define region SFLASH_PUBLIC_KEY = mem:[from 0x16005A00 size 0xC00]; + +/* Table of Content part 2, two SFlash rows */ +define region SFLASH_TOC = mem:[from 0x16007C00 size 0x400]; + + +/* Emulated EEPROM app regions */ +define region EM_EEPROM_app0_core0 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app0_core1 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app1_core0 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app1_core1 = mem:[from 0x14000000 size 0x8000]; + +/* XIP/SMIF app regions */ +define region EROM_app0_core0 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app0_core1 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app1_core0 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app1_core1 = mem:[from 0x18000000 size 0x1000]; + +/* used for RAM sharing across applications */ +define region IRAM_common = mem:[from 0x08000000 size 0x0100]; + +/* note: all the IRAM_appX_core0 regions has to be 0x100 aligned */ +/* and the IRAM_appX_core1 regions has to be 0x400 aligned */ +/* as they contain Interrupt Vector Table Remapped at the start */ +define region IRAM_app0_core0 = mem:[from 0x08000100 size 0x1F00]; +define region IRAM_app0_core1 = mem:[from 0x08002000 size 0x8000]; +define region IRAM_app1_core0 = mem:[from 0x08000100 size 0x1F00]; +define region IRAM_app1_core1 = mem:[from 0x08002000 size 0x8000]; + + +/* Used by all DFU SDK and CyMCUElfTool */ +define exported symbol __cy_boot_metadata_addr = 0x100FFA00; +define exported symbol __cy_boot_metadata_length = __cy_memory_0_row_size; + +/* Used by CyMCUElfTool to generate ProductID for DFU SDK apps */ +define exported symbol __cy_product_id = 0x01020304; + +/* Used by CyMCUElfTool to generate ChecksumType for DFU SDK apps */ +define exported symbol __cy_checksum_type = 0; + +/* +* The size of the application signature. +* E.g. 4 for CRC-32, +* 32 for SHA256, +* 256 for RSA 2048. +*/ +define exported symbol __cy_boot_signature_size = 4; + +/* Used by DFU SDK projects, in dfu_user.c to fill in the metadata table */ +define exported symbol __cy_app0_verify_start = start(FLASH_app0_core0); +define exported symbol __cy_app0_verify_length = size (FLASH_app0_core0) + size (FLASH_app0_core1) + - __cy_boot_signature_size; + +define exported symbol __cy_app1_verify_start = start(FLASH_app1_core0); +define exported symbol __cy_app1_verify_length = size (FLASH_app1_core0) + size (FLASH_app1_core1) + - __cy_boot_signature_size; + +/******************************************************************************* +* End of CM4 and CM0+ linker script common region +*******************************************************************************/ + + +/* +* Used by CM0+ to start the CM4 core in DFU SDK applications. +* Make sure the correct app no. is entered here. +*/ +define exported symbol __cy_app_core1_start_addr = start(FLASH_app0_core1); + +/* CyMCUElfTool uses this symbol to set a proper app number */ +define exported symbol __cy_app_id = 0; + +/* CyMCUElfTool uses these to generate an application signature */ +/* The size of the default signature (CRC-32C) is 4 bytes */ +define exported symbol __cy_app_verify_start = start(FLASH_app0_core0); +define exported symbol __cy_app_verify_length = size(FLASH_app0_core0) + size(FLASH_app0_core1) + - __cy_boot_signature_size; + + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + + +define region IROM1_region = FLASH_app0_core0; /* Flash, user app */ +define region IROM2_region = EM_EEPROM_app0_core0; /* Emulated EEPROM */ +define region IROM3_region = SFLASH_USER_DATA; /* SFlash User Data */ +define region IROM4_region = SFLASH_NAR; /* SFlash NAR */ +define region IROM5_region = SFLASH_PUBLIC_KEY; /* SFlash Public Key */ +define region IROM6_region = SFLASH_TOC; /* SFlash TOC part 2 */ +define region IROM7_region = ROM_EFUSE; /* eFuse */ +define region EROM1_region = EROM_app0_core0; /* XIP / SMIF */ +define region IRAM1_region = IRAM_app0_core0; /* RAM */ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram, + section .cy_boot_noinit.appId, section .cy_boot_noinit }; + + +/*-Placement-*/ + +/* Flash */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM7_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM_common { readwrite section .cy_boot_noinit.appId }; +place in IRAM_common { readwrite section .cy_boot_noinit }; +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_sflash_toc_2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + section .cy_boot_noinit, + section .cy_boot_noinit.appId, + }; + + + +/* EOF */ diff --git a/2020TPCApp0.cydsn/dfu_cm0p.ld b/2020TPCApp0.cydsn/dfu_cm0p.ld new file mode 100644 index 0000000..585816c --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_cm0p.ld @@ -0,0 +1,479 @@ +/***************************************************************************//** +* \file dfu_cm0p.ld +* \version 3.0 +* +* The linker file for the GNU C compiler. +* Used for DFU SDK core0 firmware projects. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case, you may see warnings during the +* build process. In your project, simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* +* Forces symbol to be added to the output file. +* Otherwise linker may remove it if founds that it is not used in the project. +* This command has the same effect as the -u command-line option. +*/ +EXTERN(Reset_Handler) + + +/******************************************************************************* +* Start of CM4 and CM0+ linker script common region +*******************************************************************************/ + +/* +* Memory regions, for each application and MCU core. +*/ +MEMORY +{ + flash_app0_core0 (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + flash_app0_core1 (rx) : ORIGIN = 0x10010000, LENGTH = 0x30000 + flash_app1_core0 (rx) : ORIGIN = 0x10040000, LENGTH = 0x30000 + flash_app1_core1 (rx) : ORIGIN = 0x10070000, LENGTH = 0x50000 + + flash_storage (rw) : ORIGIN = 0x100D0000, LENGTH = 0x1000 + flash_boot_meta (rw) : ORIGIN = 0x100FFA00, LENGTH = 0x400 + + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400 + + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 + + ram_common (rwx) : ORIGIN = 0x08000000, LENGTH = 0x0100 + + /* note: all the ram_appX_core0 regions has to be 0x100 aligned */ + /* and the ram_appX_core1 regions has to be 0x400 aligned */ + /* as they contain Interrupt Vector Table Remapped at the start */ + ram_app0_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00 + ram_app0_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x8000 + + ram_app1_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00 + ram_app1_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x30000 + + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x08000000 +} + +/* Regions parameters */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* The DFU SDK metadata limits */ +__cy_boot_metadata_addr = ORIGIN(flash_boot_meta); +__cy_boot_metadata_length = __cy_memory_0_row_size; + +/* The Product ID, used by CyMCUElfTool to generate a updating file */ +__cy_product_id = 0x01020304; + +/* The checksum type used by CyMCUElfTool to generate a updating file */ +__cy_checksum_type = 0x00; + +/* Used by the DFU SDK application to set the metadata */ +__cy_app0_verify_start = ORIGIN(flash_app0_core0); +__cy_app0_verify_length = LENGTH(flash_app0_core0) + LENGTH(flash_app0_core1) - __cy_boot_signature_size; +__cy_app1_verify_start = ORIGIN(flash_app1_core0); +__cy_app1_verify_length = LENGTH(flash_app1_core0) + LENGTH(flash_app1_core1) - __cy_boot_signature_size; + +/* +* The size of the application signature. +* E.g. 4 for CRC-32, +* 32 for SHA256, +* 256 for RSA 2048. +*/ +__cy_boot_signature_size = 256; + +/******************************************************************************* +* End of CM4 and CM0+ linker script common region +*******************************************************************************/ + + +/* +* DFU SDK specific: aliases regions, so the rest of code does not use +* application specific memory region names +*/ +REGION_ALIAS("flash", flash_app0_core0); +REGION_ALIAS("flash_core1", flash_app0_core1); +REGION_ALIAS("ram", ram_app0_core0); + +/* DFU SDK specific: sets an app Id */ +__cy_app_id = 0; + +/* +* DFU SDK specific: sets a start address of the Core1 application image, +* more specifically an address of the Core1 interrupt vector table. +* CM0+ uses this information to launch Core1. +*/ +__cy_app_core1_start_addr = ORIGIN(flash_core1); /* used to start Core1 from Core0 */ + +/* DFU SDK specific */ +/* CyMCUElfTool uses these ELF symbols to generate an application signature */ +__cy_app_verify_start = ORIGIN(flash); +__cy_app_verify_length = LENGTH(flash) + LENGTH(flash_core1) - __cy_boot_signature_size; + + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* The linker script defines how to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * This linker script defines the symbols, which can be used by code without a definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * + * For the DFU SDK, these additional symbols are defined: + * __cy_app_id + * __cy_product_id + * __cy_checksum_type + * __cy_app_core1_start_addr + * __cy_boot_metadata_addr + * __cy_boot_metadata_length + */ + + +SECTIONS +{ + /* DFU SDK specific */ + /* The noinit section, used across all the applications */ + .cy_boot_noinit (NOLOAD) : + { + KEEP(*(.cy_boot_noinit)); + } > ram_common + + /* The last byte of the section is used for AppId to be shared between all the applications */ + .cy_boot_noinit.appId ORIGIN(ram_common) + LENGTH(ram_common) - 1 (NOLOAD) : + { + KEEP(*(.cy_boot_noinit.appId)); + } > ram_common + + /* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */ + .cy_boot_metadata : + { + KEEP(*(.cy_boot_metadata)) + } > flash_boot_meta + + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to the RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_{device}_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from Flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_{device}_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells the linker that the .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes the linker: A) not allocate the section in memory; + * B) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get the PROGBITS type. + * This makes the linker: A) allocate the zeroed section in memory; B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* The .stack_dummy section doesn't contain any symbols. It is only + * used for the linker to calculate the size of the stack sections, and assign + * values to the stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set the stack top to the end of RAM, and the stack limit move down by + * the size of the stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Places the code in the Execute in the Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* EOF */ diff --git a/2020TPCApp0.cydsn/dfu_cm0p.scat b/2020TPCApp0.cydsn/dfu_cm0p.scat new file mode 100644 index 0000000..a774dc4 --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_cm0p.scat @@ -0,0 +1,189 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file dfu_cm0p.scat +;* \version 3.0 +;* +;* The linker file for the ARMCC. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case, you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +;* DFU SDK specific: includes defines common across all the applications +#include "dfu_mdk_common.h" + +;* DFU SDK specific: defines the memory regions +;* Make sure the correct app no. is entered here. + +; Flash +#define FLASH_START CY_APP0_CORE0_FLASH_ADDR +#define FLASH_SIZE CY_APP0_CORE0_FLASH_LENGTH + +; Emulated EEPROM Flash area +#define EM_EEPROM_START CY_APP0_CORE0_EM_EEPROM_ADDR +#define EM_EEPROM_SIZE CY_APP0_CORE0_EM_EEPROM_LENGTH + +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000400 + +; External memory +#define XIP_START CY_APP0_CORE0_SMIF_ADDR +#define XIP_SIZE CY_APP0_CORE0_SMIF_LENGTH + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; RAM +#define RAM_START CY_APP0_CORE0_RAM_ADDR +#define RAM_SIZE CY_APP0_CORE0_RAM_LENGTH + + +LR_FLASH FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_COMMON CY_APP_RAM_COMMON_ADDR UNINIT + { + * (.cy_boot_noinit.appId) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Places the code in the Execute in the Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/dfu_cm4.icf b/2020TPCApp0.cydsn/dfu_cm4.icf new file mode 100644 index 0000000..ca971bc --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_cm4.icf @@ -0,0 +1,248 @@ +/***************************************************************************//** +* \file dfu_cm4.icf +* \version 3.0 +* +* The linker file for the the IAR compiler. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case, you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ + + +/******************************************************************************* +* Start of CM4 and CM0+ linker script common region +*******************************************************************************/ + +/*-Memory Regions-*/ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + + +define memory mem with size = 4G; + +/* Memory regions for all applications are defined here */ +define region FLASH_app0_core0 = mem:[from 0x10000000 size 0x10000]; +define region FLASH_app0_core1 = mem:[from 0x10010000 size 0x10000]; +define region FLASH_app1_core0 = mem:[from 0x10040000 size 0x10000]; +define region FLASH_app1_core1 = mem:[from 0x10050000 size 0x10000]; + +/* +* The region for DFU SDK metadata +* when it is outside of any application +*/ +define region FLASH_boot_meta = mem:[from 0x100FFA00 size 0x200]; + + +/* eFuse */ +define region ROM_EFUSE = mem:[from 0x90700000 size 0x100000]; + +/* SFlash NAR */ +define region SFLASH_NAR = mem:[from 0x16001A00 size 0x200]; + +/* SFlash User Data */ +define region SFLASH_USER_DATA = mem:[from 0x16000800 size 0x800]; + +/* SFlash Public Key, 6 SFlash rows */ +define region SFLASH_PUBLIC_KEY = mem:[from 0x16005A00 size 0xC00]; + +/* Table of Content part 2, two SFlash rows */ +define region SFLASH_TOC = mem:[from 0x16007C00 size 0x400]; + + +/* Emulated EEPROM app regions */ +define region EM_EEPROM_app0_core0 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app0_core1 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app1_core0 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app1_core1 = mem:[from 0x14000000 size 0x8000]; + +/* XIP/SMIF app regions */ +define region EROM_app0_core0 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app0_core1 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app1_core0 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app1_core1 = mem:[from 0x18000000 size 0x1000]; + +/* used for RAM sharing across applications */ +define region IRAM_common = mem:[from 0x08000000 size 0x0100]; + +/* note: all the IRAM_appX_core0 regions has to be 0x100 aligned */ +/* and the IRAM_appX_core1 regions has to be 0x400 aligned */ +/* as they contain Interrupt Vector Table Remapped at the start */ +define region IRAM_app0_core0 = mem:[from 0x08000100 size 0x1F00]; +define region IRAM_app0_core1 = mem:[from 0x08002000 size 0x8000]; +define region IRAM_app1_core0 = mem:[from 0x08000100 size 0x1F00]; +define region IRAM_app1_core1 = mem:[from 0x08002000 size 0x8000]; + + +/* Used by all DFU SDK and CyMCUElfTool */ +define exported symbol __cy_boot_metadata_addr = 0x100FFA00; +define exported symbol __cy_boot_metadata_length = __cy_memory_0_row_size; + +/* Used by CyMCUElfTool to generate ProductID for DFU SDK apps */ +define exported symbol __cy_product_id = 0x01020304; + +/* Used by CyMCUElfTool to generate ChecksumType for DFU SDK apps */ +define exported symbol __cy_checksum_type = 0; + +/* +* The size of the application signature. +* E.g. 4 for CRC-32, +* 32 for SHA256, +* 256 for RSA 2048. +*/ +define exported symbol __cy_boot_signature_size = 4; + +/* Used by DFU SDK projects, in dfu_user.c to fill in the metadata table */ +define exported symbol __cy_app0_verify_start = start(FLASH_app0_core0); +define exported symbol __cy_app0_verify_length = size (FLASH_app0_core0) + size (FLASH_app0_core1) + - __cy_boot_signature_size; + +define exported symbol __cy_app1_verify_start = start(FLASH_app1_core0); +define exported symbol __cy_app1_verify_length = size (FLASH_app1_core0) + size (FLASH_app1_core1) + - __cy_boot_signature_size; + +/******************************************************************************* +* End of CM4 and CM0+ linker script common region +*******************************************************************************/ + + +/* CyMCUElfTool uses this symbol to set a proper app number */ +define exported symbol __cy_app_id = 0; + +/* CyMCUElfTool uses these to generate an application signature */ +/* The size of the default signature (CRC-32C) is 4 bytes */ +define exported symbol __cy_app_verify_start = start(FLASH_app0_core0); +define exported symbol __cy_app_verify_length = size(FLASH_app0_core0) + size(FLASH_app0_core1) + - __cy_boot_signature_size; + + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + + +define region IROM1_region = FLASH_app0_core1; /* Flash, user app */ +define region IROM2_region = EM_EEPROM_app0_core1; /* Emulated EEPROM */ +define region IROM3_region = SFLASH_USER_DATA; /* SFlash User Data */ +define region IROM4_region = SFLASH_NAR; /* SFlash NAR */ +define region IROM5_region = SFLASH_PUBLIC_KEY; /* SFlash Public Key */ +define region IROM6_region = SFLASH_TOC; /* SFlash TOC part 2 */ +define region IROM7_region = ROM_EFUSE; /* eFuse */ +define region EROM1_region = EROM_app0_core1; /* XIP / SMIF */ +define region IRAM1_region = IRAM_app0_core1; /* RAM */ + + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram, + section .cy_boot_noinit.appId, section .cy_boot_noinit }; + + +/*-Placement-*/ + +/* Flash */ +place at start of IROM1_region { block RO }; +".cy_app_signature": place at end of IROM1_region { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM7_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM_common { readwrite section .cy_boot_noinit.appId }; +place in IRAM_common { readwrite section .cy_boot_noinit }; +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + +/* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */ +".cy_boot_metadata" : place at start of FLASH_boot_meta { section .cy_boot_metadata }; + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_sflash_toc_2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + section .cy_boot_metadata, + section .cy_boot_noinit, + section .cy_boot_noinit.appId, + }; + + +/* EOF */ diff --git a/2020TPCApp0.cydsn/dfu_cm4.ld b/2020TPCApp0.cydsn/dfu_cm4.ld new file mode 100644 index 0000000..8c8bfb3 --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_cm4.ld @@ -0,0 +1,478 @@ +/***************************************************************************//** +* \file dfu_cm4.ld +* \version 3.0 +* +* The linker file for the GNU C compiler. +* Used for DFU SDK core1 firmware projects. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case, you may see warnings during the +* build process. In your project, simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* +* Forces symbol to be added to the output file. +* Otherwise linker may remove it if founds that it is not used in the project. +* This command has the same effect as the -u command-line option. +*/ +EXTERN(Reset_Handler) + + +/******************************************************************************* +* Start of CM4 and CM0+ linker script common region +*******************************************************************************/ + +/* +* Memory regions, for each application and MCU core. +*/ +MEMORY +{ + flash_app0_core0 (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + flash_app0_core1 (rx) : ORIGIN = 0x10010000, LENGTH = 0x30000 + flash_app1_core0 (rx) : ORIGIN = 0x10040000, LENGTH = 0x30000 + flash_app1_core1 (rx) : ORIGIN = 0x10070000, LENGTH = 0x50000 + + flash_storage (rw) : ORIGIN = 0x100D0000, LENGTH = 0x1000 + flash_boot_meta (rw) : ORIGIN = 0x100FFA00, LENGTH = 0x400 + + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400 + + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 + + ram_common (rwx) : ORIGIN = 0x08000000, LENGTH = 0x0100 + + /* note: all the ram_appX_core0 regions has to be 0x100 aligned */ + /* and the ram_appX_core1 regions has to be 0x400 aligned */ + /* as they contain Interrupt Vector Table Remapped at the start */ + ram_app0_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00 + ram_app0_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x8000 + + ram_app1_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00 + ram_app1_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x30000 + + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x08000000 +} + +/* Regions parameters */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* The DFU SDK metadata limits */ +__cy_boot_metadata_addr = ORIGIN(flash_boot_meta); +__cy_boot_metadata_length = __cy_memory_0_row_size; + +/* The Product ID, used by CyMCUElfTool to generate a updating file */ +__cy_product_id = 0x01020304; + +/* The checksum type used by CyMCUElfTool to generate a updating file */ +__cy_checksum_type = 0x00; + +/* Used by the DFU SDK application to set the metadata */ +__cy_app0_verify_start = ORIGIN(flash_app0_core0); +__cy_app0_verify_length = LENGTH(flash_app0_core0) + LENGTH(flash_app0_core1) - __cy_boot_signature_size; +__cy_app1_verify_start = ORIGIN(flash_app1_core0); +__cy_app1_verify_length = LENGTH(flash_app1_core0) + LENGTH(flash_app1_core1) - __cy_boot_signature_size; + +/* +* The size of the application signature. +* E.g. 4 for CRC-32, +* 32 for SHA256, +* 256 for RSA 2048. +*/ +__cy_boot_signature_size = 256; + +/******************************************************************************* +* End of CM4 and CM0+ linker script common region +*******************************************************************************/ + + +/* +* DFU SDK specific: aliases regions, so the rest of code does not use +* application specific memory region names +*/ +REGION_ALIAS("flash_core0", flash_app0_core0); +REGION_ALIAS("flash", flash_app0_core1); +REGION_ALIAS("ram", ram_app0_core1); + +/* DFU SDK specific: sets an app Id */ +__cy_app_id = 0; + + +/* DFU SDK specific */ +/* CyMCUElfTool uses these ELF symbols to generate an application signature */ +__cy_app_verify_start = ORIGIN(flash_core0); +__cy_app_verify_length = LENGTH(flash_core0) + LENGTH(flash) - __cy_boot_signature_size; + + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* The linker script defines how to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * This linker script defines the symbols, which can be used by code without a definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * + * For the DFU SDK, these additional symbols are defined: + * __cy_app_id + * __cy_product_id + * __cy_checksum_type + * __cy_app_core1_start_addr + * __cy_boot_metadata_addr + * __cy_boot_metadata_length + */ + + +SECTIONS +{ + /* DFU SDK specific */ + /* The noinit section, used across all the applications */ + .cy_boot_noinit (NOLOAD) : + { + KEEP(*(.cy_boot_noinit)); + } > ram_common + + /* The last byte of the section is used for AppId to be shared between all the applications */ + .cy_boot_noinit.appId ORIGIN(ram_common) + LENGTH(ram_common) - 1 (NOLOAD) : + { + KEEP(*(.cy_boot_noinit.appId)); + } > ram_common + + /* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */ + .cy_boot_metadata : + { + KEEP(*(.cy_boot_metadata)) + } > flash_boot_meta + + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to the RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_{device}_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_{device}_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + /* + * The DFU SDK section for an app verification signature. + * Must be placed at the end of the application. + * In this case, last N bytes of the last Flash row inside the application. + */ + .cy_app_signature ABSOLUTE(ORIGIN(flash) + LENGTH(flash) - __cy_boot_signature_size) : + { + KEEP(*(.cy_app_signature)) + } > flash = 0 + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells the linker that the .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes the linker: A) not allocate the section in memory; + * B) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get the PROGBITS type. + * This makes the linker: A) allocate the zeroed section in memory; B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* The .stack_dummy section doesn't contain any symbols. It is only + * used for the linker to calculate the size of the stack sections, and assign + * values to the stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set the stack top to the end of RAM, and the stack limit move down by + * the size of the stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Places the code in the Execute in the Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* EOF */ diff --git a/2020TPCApp0.cydsn/dfu_cm4.scat b/2020TPCApp0.cydsn/dfu_cm4.scat new file mode 100644 index 0000000..8aab5d9 --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_cm4.scat @@ -0,0 +1,206 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file dfu_cm4.scat +;* \version 3.0 +;* +;* The linker file for the ARMCC. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case, you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +;* DFU SDK specific: includes defines common across all the applications +#include "dfu_mdk_common.h" + +;* DFU SDK specific: defines the memory regions +;* Make sure the correct app no. is entered here + +; Flash +#define FLASH_START CY_APP0_CORE1_FLASH_ADDR +#define FLASH_SIZE CY_APP0_CORE1_FLASH_LENGTH + +; Flash Toc +#define FLASH_TOC_START CY_TOC_START +#define FLASH_TOC_SIZE CY_TOC_SIZE + +; Emulated EEPROM Flash area +#define EM_EEPROM_START CY_APP0_CORE1_EM_EEPROM_ADDR +#define EM_EEPROM_SIZE CY_APP0_CORE1_EM_EEPROM_LENGTH + +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000400 + +; External memory +#define XIP_START CY_APP0_CORE1_SMIF_ADDR +#define XIP_SIZE CY_APP0_CORE1_SMIF_LENGTH + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; RAM +#define RAM_START CY_APP0_CORE1_RAM_ADDR +#define RAM_SIZE CY_APP0_CORE1_RAM_LENGTH + + +LR_FLASH FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_COMMON CY_APP_RAM_COMMON_ADDR UNINIT + { + * (.cy_boot_noinit.appId) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during + ; a device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + + ; Used for the digital signature of the secure application and the + ; DFU SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - CY_BOOT_SIGNATURE_SIZE) FIXED + { + * (.cy_app_signature) + } +} + +; App0 uses it to initialize DFU SDK metadata, in dfu_user.c file +LR_CY_BOOT_METADATA CY_BOOT_META_FLASH_ADDR CY_BOOT_META_FLASH_LENGTH +{ + .cy_boot_metadata + 0 + { + * (.cy_boot_metadata) + } +} + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory Flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory Flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory Flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory Flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/dfu_mdk_common.h b/2020TPCApp0.cydsn/dfu_mdk_common.h new file mode 100644 index 0000000..e50b562 --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_mdk_common.h @@ -0,0 +1,114 @@ +/******************************************************************************* +* \file dfu_mdk_common.h +* \version 3.0 +* +* This file provides only macro definitions to use for +* project configuration. +* They may be used in both scatter files and source code files. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef DFU_MDK_COMMON_H_ +#define DFU_MDK_COMMON_H_ + +/* DFU SDK parameters */ +/* The user application may either update them or leave the defaults if they fit */ +#define CY_BOOT_METADATA_ADDR 0x100FFA00 +#define CY_BOOT_METADATA_LENGTH 0x200 +#define CY_PRODUCT_ID 0x01020304 +#define CY_CHECKSUM_TYPE 0x00 + +/* +* The size of the section .cy_app_signature. +* 1,2, or 4 for a checksum +* 4 for CRC-32 +* 20 for SHA1 +* 32 for SHA256 +* 256 for RSASSA-PKCS1-v1.5 with the 2048 bit RSA key. +* +* SHA1 must be used. +*/ +#define CY_BOOT_SIGNATURE_SIZE 4 + +/* For the MDK linker script, defines TOC parameters */ +/* Update per device series to be in the last Flash row */ +#define CY_TOC_START 0x16007C00 +#define CY_TOC_SIZE 0x400 + + +/* Memory region ranges per core and app */ +#define CY_APP0_CORE0_FLASH_ADDR 0x10000000 +#define CY_APP0_CORE0_FLASH_LENGTH 0x10000 + +#define CY_APP0_CORE1_FLASH_ADDR 0x10010000 +#define CY_APP0_CORE1_FLASH_LENGTH 0x10000 + +#define CY_APP1_CORE0_FLASH_ADDR 0x10040000 +#define CY_APP1_CORE0_FLASH_LENGTH 0x10000 + +#define CY_APP1_CORE1_FLASH_ADDR 0x10050000 +#define CY_APP1_CORE1_FLASH_LENGTH 0x10000 + +/* DFU SDK metadata address range in Flash */ +#define CY_BOOT_META_FLASH_ADDR 0x100FFA00 +#define CY_BOOT_META_FLASH_LENGTH 0x200 + +/* Application ranges in emulated EEPROM */ +#define CY_APP0_CORE0_EM_EEPROM_ADDR 0x14000000 +#define CY_APP0_CORE0_EM_EEPROM_LENGTH 0x00000000 + +#define CY_APP0_CORE1_EM_EEPROM_ADDR (CY_APP0_CORE0_EM_EEPROM_ADDR + CY_APP0_CORE0_EM_EEPROM_LENGTH) +#define CY_APP0_CORE1_EM_EEPROM_LENGTH 0x0000 + +#define CY_APP1_CORE0_EM_EEPROM_ADDR 0x14000000 +#define CY_APP1_CORE0_EM_EEPROM_LENGTH 0x00000000 + +#define CY_APP1_CORE1_EM_EEPROM_ADDR (CY_APP1_CORE0_EM_EEPROM_ADDR + CY_APP1_CORE0_EM_EEPROM_LENGTH) +#define CY_APP1_CORE1_EM_EEPROM_LENGTH 0x00000000 + +/* Application ranges in SMIF XIP */ +#define CY_APP0_CORE0_SMIF_ADDR 0x18000000 +#define CY_APP0_CORE0_SMIF_LENGTH 0x00000000 + +#define CY_APP0_CORE1_SMIF_ADDR (CY_APP0_CORE0_SMIF_ADDR + CY_APP0_CORE0_SMIF_LENGTH) +#define CY_APP0_CORE1_SMIF_LENGTH 0x00000000 + +#define CY_APP1_CORE0_SMIF_ADDR 0x14000200 +#define CY_APP1_CORE0_SMIF_LENGTH 0x00000000 + +#define CY_APP1_CORE1_SMIF_ADDR (CY_APP1_CORE0_SMIF_ADDR + CY_APP1_CORE0_SMIF_LENGTH) +#define CY_APP1_CORE1_SMIF_LENGTH 0x00000000 + +/* Application ranges in RAM */ +#define CY_APP_RAM_COMMON_ADDR 0x08000000 +#define CY_APP_RAM_COMMON_LENGTH 0x00000100 + +/* note: all the CY_APPX_CORE0_RAM regions has to be 0x100 aligned */ +/* and the CY_APPX_CORE1_RAM regions has to be 0x400 aligned */ +/* as they contain Interrupt Vector Table Remapped at the start */ + +#define CY_APP0_CORE0_RAM_ADDR 0x08000100 +#define CY_APP0_CORE0_RAM_LENGTH 0x00001F00 + +#define CY_APP0_CORE1_RAM_ADDR (CY_APP0_CORE0_RAM_ADDR + CY_APP0_CORE0_RAM_LENGTH) +#define CY_APP0_CORE1_RAM_LENGTH 0x00008000 + +#define CY_APP1_CORE0_RAM_ADDR CY_APP0_CORE0_RAM_ADDR +#define CY_APP1_CORE0_RAM_LENGTH 0x00001F00 + +#define CY_APP1_CORE1_RAM_ADDR (CY_APP1_CORE0_RAM_ADDR + CY_APP1_CORE0_RAM_LENGTH) +#define CY_APP1_CORE1_RAM_LENGTH 0x00008000 + + +__asm void cy_DFU_mdkAsmDummy(void); + +#endif /* DFU_MDK_COMMON_H_ */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/dfu_mdk_symbols.c b/2020TPCApp0.cydsn/dfu_mdk_symbols.c new file mode 100644 index 0000000..fd3a950 --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_mdk_symbols.c @@ -0,0 +1,66 @@ +/******************************************************************************* +* \file dfu_mdk_symbols.c +* \version 3.0 +* +* This file provides symbols to add to an ELF file required by +* CyMCUElfTool to generate correct HEX and CYACD2 files. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "dfu_mdk_common.h" + +/******************************************************************************* +* Function Name: cy_DFU_mdkAsmDummy +******************************************************************************** +* This function provides ELF file symbols through +* the inline assembly. +* The inline assembly in the *.c file is chosen, because it allows using +* #include where the user configuration is updated. +* +* Note that this function does not have code, so no additional memory +* is allocated for it. +*******************************************************************************/ +__asm void cy_DFU_mdkAsmDummy(void) +{ + EXPORT __cy_boot_metadata_addr + EXPORT __cy_boot_metadata_length + + EXPORT __cy_app_core1_start_addr + + EXPORT __cy_product_id + EXPORT __cy_checksum_type + EXPORT __cy_app_id + + EXPORT __cy_app_verify_start + EXPORT __cy_app_verify_length + +/* Used by all DFU SDK applications to switch to another app */ +__cy_boot_metadata_addr EQU __cpp(CY_BOOT_METADATA_ADDR) +/* Used by CyMCUElfTool to update DFU SDK metadata with CRC-32C */ +__cy_boot_metadata_length EQU __cpp(CY_BOOT_METADATA_LENGTH) + +/* Used by CM0+ to start CM4 core in the DFU SDK applications. */ +/* Make sure the correct app no. is entered here */ +__cy_app_core1_start_addr EQU __cpp(CY_APP0_CORE1_FLASH_ADDR) + +/* Used by CyMCUElfTool to generate ProductID */ +__cy_product_id EQU __cpp(CY_PRODUCT_ID) +/* Used by CyMCUElfTool to generate ChecksumType */ +__cy_checksum_type EQU __cpp(CY_CHECKSUM_TYPE) +/* Application number (ID) */ +__cy_app_id EQU 0 + +/* CyMCUElfTool uses these to generate an application signature */ +/* The size of the default signature (CRC-32C) is 4 bytes */ +__cy_app_verify_start EQU __cpp(CY_APP0_CORE0_FLASH_ADDR) +__cy_app_verify_length EQU __cpp(CY_APP0_CORE0_FLASH_LENGTH + CY_APP0_CORE1_FLASH_LENGTH - CY_BOOT_SIGNATURE_SIZE) +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/dfu_user.c b/2020TPCApp0.cydsn/dfu_user.c new file mode 100644 index 0000000..136e60d --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_user.c @@ -0,0 +1,303 @@ +/***************************************************************************//** +* \file dfu_user.c +* \version 3.0 +* +* This file provides the custom API for a firmware application with +* DFU SDK. +* - Cy_DFU_ReadData (address, length, ctl, params) - to read the NVM block +* - Cy_DFU_WriteData(address, length, ctl, params) - to write the NVM block +* +* - Cy_DFU_TransportStart() to start a communication interface +* - Cy_DFU_TransportStop () to stop a communication interface +* - Cy_DFU_TransportReset() to reset a communication interface +* - Cy_DFU_TransportRead (buffer, size, count, timeout) +* - Cy_DFU_TransportWrite(buffer, size, count, timeout) +* +******************************************************************************** +* \copyright +* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "transport_ble.h" +#include "cy_syslib.h" +#include "cy_flash.h" +#include "cy_dfu.h" + + +/* +* The DFU SDK metadata initial value is placed here +* Note: the number of elements equal to the number of the app multiplies by 2 +* because of the two fields per app plus one element for the CRC-32C field. +*/ +CY_SECTION(".cy_boot_metadata") __USED +static const uint32_t cy_dfu_metadata[CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)] = +{ + CY_DFU_APP0_VERIFY_START, CY_DFU_APP0_VERIFY_LENGTH, /* The App0 base address and length */ + CY_DFU_APP1_VERIFY_START, CY_DFU_APP1_VERIFY_LENGTH, /* The App1 base address and length */ + 0u /* The rest does not matter */ +}; + + +static uint32_t IsMultipleOf(uint32_t value, uint32_t multiple); +static void GetStartEndAddress(uint32_t appId, uint32_t *startAddress, uint32_t *endAddress); + + +/******************************************************************************* +* Function Name: IsMultipleOf +****************************************************************************//** +* +* This internal function check if value parameter is a multiple of parameter +* multiple +* +* \param value value that will be checked +* \param multiple value with which value is checked +* +* \return 1 - value is multiple of parameter multiple, else 0 +* +*******************************************************************************/ +static uint32_t IsMultipleOf(uint32_t value, uint32_t multiple) +{ + return ( ((value % multiple) == 0u)? 1ul : 0ul); +} + + +/******************************************************************************* +* Function Name: GetStartEndAddress +****************************************************************************//** +* +* This internal function returns start and end address of application +* +* \param appId The application number +* \param startAddress The pointer to a variable where an application start +* address is stored +* \param endAddress The pointer to a variable where a size of application +* area is stored. +* +*******************************************************************************/ +static void GetStartEndAddress(uint32_t appId, uint32_t *startAddress, uint32_t *endAddress) +{ + uint32_t verifyStart; + uint32_t verifySize; + + (void)Cy_DFU_GetAppMetadata(appId, &verifyStart, &verifySize); + +#if (CY_DFU_APP_FORMAT == CY_DFU_SIMPLIFIED_APP) + *startAddress = verifyStart - CY_DFU_SIGNATURE_SIZE; + *endAddress = verifyStart + verifySize; +#else + *startAddress = verifyStart; + *endAddress = verifyStart + verifySize + CY_DFU_SIGNATURE_SIZE; +#endif +} + + +/******************************************************************************* +* Function Name: Cy_DFU_WriteData +****************************************************************************//** +* +* This function documentation is part of the DFU SDK API, see the +* cy_dfu.h file or DFU SDK API Reference Manual for details. +* +*******************************************************************************/ +cy_en_dfu_status_t Cy_DFU_WriteData (uint32_t address, uint32_t length, uint32_t ctl, + cy_stc_dfu_params_t *params) +{ + /* User Flash Limits */ + /* Note that App0 is out of range */ + const uint32_t minUFlashAddress = CY_FLASH_BASE + CY_DFU_APP0_VERIFY_LENGTH; + const uint32_t maxUFlashAddress = CY_FLASH_BASE + CY_FLASH_SIZE; + /* EM_EEPROM Limits*/ + const uint32_t minEmEepromAddress = CY_EM_EEPROM_BASE; + const uint32_t maxEmEepromAddress = CY_EM_EEPROM_BASE + CY_EM_EEPROM_SIZE; + + cy_en_dfu_status_t status = CY_DFU_SUCCESS; + + uint32_t app = Cy_DFU_GetRunningApp(); + uint32_t startAddress; + uint32_t endAddress; + + GetStartEndAddress(app, &startAddress, &endAddress); + + /* Check if the address and length are valid + * Note Length = 0 is valid for erase command */ + if ( (IsMultipleOf(address, CY_FLASH_SIZEOF_ROW) == 0u) || + ( (length != CY_FLASH_SIZEOF_ROW) && ( (ctl & CY_DFU_IOCTL_ERASE) == 0u) ) ) + { + status = CY_DFU_ERROR_LENGTH; + } + + /* Refuse to write to a row within a range of the current application */ + if ( (startAddress <= address) && (address < endAddress) ) + { /* It is forbidden to overwrite the currently running application */ + status = CY_DFU_ERROR_ADDRESS; + } +#if CY_DFU_OPT_GOLDEN_IMAGE + if (status == CY_DFU_SUCCESS) + { + uint8_t goldenImages[] = { CY_DFU_GOLDEN_IMAGE_IDS() }; + uint32_t count = sizeof(goldenImages) / sizeof(goldenImages[0]); + uint32_t idx; + for (idx = 0u; idx < count; ++idx) + { + app = goldenImages[idx]; + GetStartEndAddress(app, &startAddress, &endAddress); + + if ( (startAddress <= address) && (address < endAddress) ) + { + status = Cy_DFU_ValidateApp(app, params); + status = (status == CY_DFU_SUCCESS) ? CY_DFU_ERROR_ADDRESS : CY_DFU_SUCCESS; + break; + } + } + } +#endif /* #if CY_DFU_OPT_GOLDEN_IMAGE != 0 */ + + /* Check if the address is inside the valid range */ + if ( ( (minUFlashAddress <= address) && (address < maxUFlashAddress) ) + || ( (minEmEepromAddress <= address) && (address < maxEmEepromAddress) ) ) + { /* Do nothing, this is an allowed memory range to update to */ + } + else + { + status = CY_DFU_ERROR_ADDRESS; + } + + if (status == CY_DFU_SUCCESS) + { + if ((ctl & CY_DFU_IOCTL_ERASE) != 0u) + { + (void) memset(params->dataBuffer, 0, CY_FLASH_SIZEOF_ROW); + } + cy_en_flashdrv_status_t fstatus = Cy_Flash_WriteRow(address, (uint32_t*)params->dataBuffer); + status = (fstatus == CY_FLASH_DRV_SUCCESS) ? CY_DFU_SUCCESS : CY_DFU_ERROR_DATA; + } + return (status); +} + + +/******************************************************************************* +* Function Name: Cy_DFU_ReadData +****************************************************************************//** +* +* This function documentation is part of the DFU SDK API, see the +* cy_dfu.h file or DFU SDK API Reference Manual for details. +* +*******************************************************************************/ +cy_en_dfu_status_t Cy_DFU_ReadData (uint32_t address, uint32_t length, uint32_t ctl, + cy_stc_dfu_params_t *params) +{ + /* User Flash Limits */ + /* Note that App0 is out of range */ + const uint32_t minUFlashAddress = CY_FLASH_BASE + CY_DFU_APP0_VERIFY_LENGTH; + const uint32_t maxUFlashAddress = CY_FLASH_BASE + CY_FLASH_SIZE; + /* EM_EEPROM Limits*/ + const uint32_t minEmEepromAddress = CY_EM_EEPROM_BASE; + const uint32_t maxEmEepromAddress = CY_EM_EEPROM_BASE + CY_EM_EEPROM_SIZE; + + cy_en_dfu_status_t status = CY_DFU_SUCCESS; + + /* Check if the length is valid */ + if (IsMultipleOf(length, CY_FLASH_SIZEOF_ROW) == 0u) + { + status = CY_DFU_ERROR_LENGTH; + } + + /* Check if the address is inside the valid range */ + if ( ( (minUFlashAddress <= address) && (address < maxUFlashAddress) ) + || ( (minEmEepromAddress <= address) && (address < maxEmEepromAddress) ) ) + { /* Do nothing, this is an allowed memory range to update to */ + } + else + { + status = CY_DFU_ERROR_ADDRESS; + } + + /* Read or Compare */ + if (status == CY_DFU_SUCCESS) + { + if ((ctl & CY_DFU_IOCTL_COMPARE) == 0u) + { + (void) memcpy(params->dataBuffer, (const void *)address, length); + status = CY_DFU_SUCCESS; + } + else + { + status = ( memcmp(params->dataBuffer, (const void *)address, length) == 0 ) + ? CY_DFU_SUCCESS : CY_DFU_ERROR_VERIFY; + } + } + return (status); +} + + +/******************************************************************************* +* Function Name: Cy_DFU_TransportRead +****************************************************************************//** +* +* This function documentation is part of the DFU SDK API, see the +* cy_dfu.h file or DFU SDK API Reference Manual for details. +* +*******************************************************************************/ +cy_en_dfu_status_t Cy_DFU_TransportRead (uint8_t *buffer, uint32_t size, uint32_t *count, uint32_t timeout) +{ + return (CyBLE_CyBtldrCommRead(buffer, size, count, timeout)); +} + +/******************************************************************************* +* Function Name: Cy_DFU_TransportWrite +****************************************************************************//** +* +* This function documentation is part of the DFU SDK API, see the +* cy_dfu.h file or DFU SDK API Reference Manual for details. +* +*******************************************************************************/ +cy_en_dfu_status_t Cy_DFU_TransportWrite(uint8_t *buffer, uint32_t size, uint32_t *count, uint32_t timeout) +{ + return (CyBLE_CyBtldrCommWrite(buffer, size, count, timeout)); +} + +/******************************************************************************* +* Function Name: Cy_DFU_TransportReset +****************************************************************************//** +* +* This function documentation is part of the DFU SDK API, see the +* cy_dfu.h file or DFU SDK API Reference Manual for details. +* +*******************************************************************************/ +void Cy_DFU_TransportReset(void) +{ + CyBLE_CyBtldrCommReset(); +} + +/******************************************************************************* +* Function Name: Cy_DFU_TransportStart +****************************************************************************//** +* +* This function documentation is part of the DFU SDK API, see the +* cy_dfu.h file or DFU SDK API Reference Manual for details. +* +*******************************************************************************/ +void Cy_DFU_TransportStart(void) +{ + CyBLE_CyBtldrCommStart(); +} + +/******************************************************************************* +* Function Name: Cy_DFU_TransportStop +****************************************************************************//** +* +* This function documentation is part of the DFU SDK API, see the +* cy_dfu.h file or DFU SDK API Reference Manual for details. +* +*******************************************************************************/ +void Cy_DFU_TransportStop(void) +{ + CyBLE_CyBtldrCommStop(); +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/dfu_user.h b/2020TPCApp0.cydsn/dfu_user.h new file mode 100644 index 0000000..c9e0fa1 --- /dev/null +++ b/2020TPCApp0.cydsn/dfu_user.h @@ -0,0 +1,151 @@ +/***************************************************************************//** +* \file dfu_user.h +* \version 3.0 +* +* This file provides declarations that can be modified by the user but +* are used by the DFU SDK. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(DFU_USER_H) +#define DFU_USER_H + +#include +#include "cy_flash.h" + + +/** +* \addtogroup group_dfu_macro_config +* \{ +*/ + +/** The size of a buffer to hold DFU commands */ +/* 16 bytes is a maximum overhead of a DFU packet and additional data for the Program Data command */ +#define CY_DFU_SIZEOF_CMD_BUFFER (CY_FLASH_SIZEOF_ROW + 16u) + +/** The size of a buffer to hold an NVM row of data to write or verify */ +#define CY_DFU_SIZEOF_DATA_BUFFER (CY_FLASH_SIZEOF_ROW + 16u) + +/** +* Set to non-zero for the DFU SDK Program Data command to check +* if the Golden image is going to be overwritten while updating. +*/ +#define CY_DFU_OPT_GOLDEN_IMAGE (0) + +/** +* List of Golden Image Application IDs. +* Here "Golden Image Application" means an application that cannot be changed with +* CommandProgramData() +* +* Usage. Define the list of Golden Image Application IDs without enclosing +* parenthesis, e.g. +* \code #define CY_DFU_GOLDEN_IMAGE_IDS() 0u, 1u, 3u \endcode +* later it is used in cy_dfu.c file: +* \code uint8_t goldenImages[] = { CY_DFU_GOLDEN_IMAGE_IDS() }; \endcode +*/ +#define CY_DFU_GOLDEN_IMAGE_IDS() 0u + +/** +* The number of applications in the metadata, +* for 512 bytes in a Flash row - 63 is the maximum possible value, +* because 4 bytes are reserved for the entire metadata CRC. +* +* The smallest metadata size if CY_DFU_MAX_APPS * 8 (bytes per one app) + 4 (bytes for CRC-32C) +*/ +#define CY_DFU_MAX_APPS (2u) + + +/** A non-zero value enables the Verify Data DFU command */ +#define CY_DFU_OPT_VERIFY_DATA (1) + +/** A non-zero value enables the Erase Data DFU command */ +#define CY_DFU_OPT_ERASE_DATA (1) + +/** A non-zero value enables the Verify App DFU command */ +#define CY_DFU_OPT_VERIFY_APP (1) + +/** +* A non-zero value enables the Send Data DFU command. +* If the "Send Data" DFU command is enabled, \c packetBuffer and \c dataBuffer +* must be non-overlapping. +* +* Else, \c dataBuffer must be inside \c packetBuffer with an offset of +* \c CY_DFU_PACKET_DATA_IDX, typically 4 bytes. \n +* params->dataBuffer = &packetBuffer[4]; \n +* \note that \c packetBuffer in this case must be 4 bytes aligned, as +* \c dataBuffer is required to be 4 bytes aligned. +*/ +#define CY_DFU_OPT_SEND_DATA (1) + +/** A non-zero value enables the Get Metadata DFU command */ +#define CY_DFU_OPT_GET_METADATA (1) + +/** A non-zero value enables the Set EI Vector DFU command */ +#define CY_DFU_OPT_SET_EIVECTOR (0) + +/** +* A non-zero value allows writing metadata +* with the Set App Metadata DFU command. +*/ +#define CY_DFU_METADATA_WRITABLE (1) + +/** Non-zero value enables the usage of hardware Crypto API */ +#define CY_DFU_OPT_CRYPTO_HW (1) + +/** A non-zero value enables the usage of CRC-16 for DFU packet verification */ +#define CY_DFU_OPT_PACKET_CRC (0) + +/** Set the default application-format-possible values defined in \ref group_dfu_macro_app_type */ +#define CY_DFU_APP_FORMAT (CY_DFU_CYPRESS_APP) + +/** Set the default secure application-verification-type possible values + * defined in \ref group_dfu_macro_ver_type */ +#define CY_DFU_SEC_APP_VERIFY_TYPE (CY_DFU_VERIFY_FAST) + +/** \} group_dfu_macro_config */ + +#if !defined(CY_DOXYGEN) + #if defined(__GNUC__) || defined(__ICCARM__) + /* + * These variables are defined in the linker scripts, the values of their addresses define + * corresponding applications start address and length. + */ + extern uint8_t __cy_app0_verify_start; + extern uint8_t __cy_app0_verify_length; + extern uint8_t __cy_app1_verify_start; + extern uint8_t __cy_app1_verify_length; + extern uint8_t __cy_boot_signature_size; + + #define CY_DFU_APP0_VERIFY_START ( (uint32_t)&__cy_app0_verify_start ) + #define CY_DFU_APP0_VERIFY_LENGTH ( (uint32_t)&__cy_app0_verify_length ) + #define CY_DFU_APP1_VERIFY_START ( (uint32_t)&__cy_app1_verify_start ) + #define CY_DFU_APP1_VERIFY_LENGTH ( (uint32_t)&__cy_app1_verify_length ) + #define CY_DFU_SIGNATURE_SIZE ( (uint32_t)&__cy_boot_signature_size ) + + #elif defined(__ARMCC_VERSION) + #include "dfu_mdk_common.h" + + #define CY_DFU_APP0_VERIFY_START ( CY_APP0_CORE0_FLASH_ADDR ) + #define CY_DFU_APP0_VERIFY_LENGTH ( CY_APP0_CORE0_FLASH_LENGTH + CY_APP0_CORE1_FLASH_LENGTH \ + - CY_BOOT_SIGNATURE_SIZE) + #define CY_DFU_APP1_VERIFY_START ( CY_APP1_CORE0_FLASH_ADDR ) + #define CY_DFU_APP1_VERIFY_LENGTH ( CY_APP1_CORE0_FLASH_LENGTH + CY_APP1_CORE1_FLASH_LENGTH \ + - CY_BOOT_SIGNATURE_SIZE) + #define CY_DFU_SIGNATURE_SIZE CY_BOOT_SIGNATURE_SIZE + + #else + #error "Not implemented for this compiler" + #endif /* defined(__GNUC__) || defined(__ICCARM__) */ +#endif /* !defined(CY_DOXYGEN) */ + + +#endif /* !defined(DFU_USER_H) */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/gcc/startup_psoc6_01_cm0plus.S b/2020TPCApp0.cydsn/gcc/startup_psoc6_01_cm0plus.S new file mode 100644 index 0000000..e26df0a --- /dev/null +++ b/2020TPCApp0.cydsn/gcc/startup_psoc6_01_cm0plus.S @@ -0,0 +1,404 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .end + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/gcc/startup_psoc6_01_cm4.S b/2020TPCApp0.cydsn/gcc/startup_psoc6_01_cm4.S new file mode 100644 index 0000000..b904621 --- /dev/null +++ b/2020TPCApp0.cydsn/gcc/startup_psoc6_01_cm4.S @@ -0,0 +1,635 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/iar/startup_psoc6_01_cm0plus.s b/2020TPCApp0.cydsn/iar/startup_psoc6_01_cm0plus.s new file mode 100644 index 0000000..a867384 --- /dev/null +++ b/2020TPCApp0.cydsn/iar/startup_psoc6_01_cm0plus.s @@ -0,0 +1,423 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Power Mode Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK NvicMux8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux8_IRQHandler + B NvicMux8_IRQHandler + + PUBWEAK NvicMux9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux9_IRQHandler + B NvicMux9_IRQHandler + + PUBWEAK NvicMux10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux10_IRQHandler + B NvicMux10_IRQHandler + + PUBWEAK NvicMux11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux11_IRQHandler + B NvicMux11_IRQHandler + + PUBWEAK NvicMux12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux12_IRQHandler + B NvicMux12_IRQHandler + + PUBWEAK NvicMux13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux13_IRQHandler + B NvicMux13_IRQHandler + + PUBWEAK NvicMux14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux14_IRQHandler + B NvicMux14_IRQHandler + + PUBWEAK NvicMux15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux15_IRQHandler + B NvicMux15_IRQHandler + + PUBWEAK NvicMux16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux16_IRQHandler + B NvicMux16_IRQHandler + + PUBWEAK NvicMux17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux17_IRQHandler + B NvicMux17_IRQHandler + + PUBWEAK NvicMux18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux18_IRQHandler + B NvicMux18_IRQHandler + + PUBWEAK NvicMux19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux19_IRQHandler + B NvicMux19_IRQHandler + + PUBWEAK NvicMux20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux20_IRQHandler + B NvicMux20_IRQHandler + + PUBWEAK NvicMux21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux21_IRQHandler + B NvicMux21_IRQHandler + + PUBWEAK NvicMux22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux22_IRQHandler + B NvicMux22_IRQHandler + + PUBWEAK NvicMux23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux23_IRQHandler + B NvicMux23_IRQHandler + + PUBWEAK NvicMux24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux24_IRQHandler + B NvicMux24_IRQHandler + + PUBWEAK NvicMux25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux25_IRQHandler + B NvicMux25_IRQHandler + + PUBWEAK NvicMux26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux26_IRQHandler + B NvicMux26_IRQHandler + + PUBWEAK NvicMux27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux27_IRQHandler + B NvicMux27_IRQHandler + + PUBWEAK NvicMux28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux28_IRQHandler + B NvicMux28_IRQHandler + + PUBWEAK NvicMux29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux29_IRQHandler + B NvicMux29_IRQHandler + + PUBWEAK NvicMux30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux30_IRQHandler + B NvicMux30_IRQHandler + + PUBWEAK NvicMux31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux31_IRQHandler + B NvicMux31_IRQHandler + + + END + + +; [] END OF FILE diff --git a/2020TPCApp0.cydsn/iar/startup_psoc6_01_cm4.s b/2020TPCApp0.cydsn/iar/startup_psoc6_01_cm4.s new file mode 100644 index 0000000..6f1e869 --- /dev/null +++ b/2020TPCApp0.cydsn/iar/startup_psoc6_01_cm4.s @@ -0,0 +1,1142 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/2020TPCApp0.cydsn/ias.c b/2020TPCApp0.cydsn/ias.c new file mode 100644 index 0000000..4973565 --- /dev/null +++ b/2020TPCApp0.cydsn/ias.c @@ -0,0 +1,62 @@ +/******************************************************************************* +* File Name: ias.c +* +* Description: +* This file contains Immediate Alert Service callback handler function. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "ias.h" + + +/* IAS alert level value */ +volatile uint8_t alertLevel = 0; + +/****************************************************************************** +* Function Name: IasInit +******************************************************************************* +* +* Summary: +* Registers the IAS CallBack. +* +******************************************************************************/ +void IasInit(void) +{ + Cy_BLE_IAS_RegisterAttrCallback(IasEventHandler); +} + + +/******************************************************************************* +* Function Name: IasEventHandler +******************************************************************************** +* +* Summary: +* This is an event callback function to receive events from the BLE Component, +* which are specific to Immediate Alert Service. +* +* Parameters: +* event: Write Command event from the BLE component. +* eventParams: A structure instance of CY_BLE_GATT_HANDLE_VALUE_PAIR_T type. +* +*******************************************************************************/ +void IasEventHandler(uint32 event, void *eventParam) +{ + (void) eventParam; + uint8_t alert; + + /* Alert Level Characteristic write event */ + if(event == CY_BLE_EVT_IASS_WRITE_CHAR_CMD) + { + /* Read the updated Alert Level value from the GATT database */ + Cy_BLE_IASS_GetCharacteristicValue(CY_BLE_IAS_ALERT_LEVEL, sizeof(alert), &alert); + alertLevel = alert; + } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/ias.h b/2020TPCApp0.cydsn/ias.h new file mode 100644 index 0000000..233ce70 --- /dev/null +++ b/2020TPCApp0.cydsn/ias.h @@ -0,0 +1,31 @@ +/******************************************************************************* +* File Name: ias.h +* +* Description: +* Contains the function prototypes and references for the Immediate Alert +* Service of the Bluetooth Component. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "project.h" + + +/*************************************** +* Function Prototypes +***************************************/ +void IasInit(void); +void IasEventHandler(uint32_t event, void *eventParam); + + +/*************************************** +* External data references +***************************************/ +extern volatile uint8_t alertLevel; + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/key_copy.bat b/2020TPCApp0.cydsn/key_copy.bat new file mode 100644 index 0000000..7eea6c0 --- /dev/null +++ b/2020TPCApp0.cydsn/key_copy.bat @@ -0,0 +1,78 @@ +::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: +:: +:: File Name: key_copy.bat +:: +:: Version: 1.01 +:: +:: Description: +:: Simple script to copy generated key files to a persistent location +:: +::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: +:: Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +:: This software is owned by Cypress Semiconductor Corporation and is protected +:: by and subject to worldwide patent and copyright laws and treaties. +:: Therefore, you may use this software only as provided in the license agreement +:: accompanying the software package from which you obtained this software. +:: CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +:: WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, +:: IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: + +@echo off +set OUT_DIR="..\Keys" +set LOCAL_DIR=keys_generated + +set SRC_PRIV_NAME=rsa_private_generated.txt +set SRC_PUB_NAME=rsa_public_generated.txt +set SRC_AES_NAME=aes_private_generated.txt +set SRC_EIV_NAME=aes_eiv_generated.txt + +set PRIV_NAME=rsa_private.txt +set PUB_NAME=rsa_public.txt +set AES_NAME=aes_private.txt +set EIV_NAME=aes_eiv.txt + + +:: File Check +set ALLOK=1 +IF NOT EXIST %LOCAL_DIR%\%SRC_PRIV_NAME% ( + echo File %SRC_PRIV_NAME% does not exist. + set ALLOK=0 +) +IF NOT EXIST %LOCAL_DIR%\%SRC_PUB_NAME% ( + echo File %SRC_PUB_NAME% does not exist. + set ALLOK=0 +) +IF NOT EXIST %LOCAL_DIR%\%SRC_AES_NAME% ( + echo File %SRC_AES_NAME% does not exist. + set ALLOK=0 +) +IF NOT EXIST %LOCAL_DIR%\%SRC_EIV_NAME% ( + echo File %SRC_EIV_NAME% does not exist. + set ALLOK=0 +) +IF %ALLOK% == 0 ( + echo Please run the keygen batch file to generate the keys. + echo. + goto :end +) + +IF NOT EXIST %OUT_DIR% mkdir %OUT_DIR% + +:choice +cls +echo Warning: The keys used in the application will be overwritten. +set /P c=Are you sure you want to continue [Y/N]? +if /I "%c%" EQU "Y" goto :cont +if /I "%c%" EQU "N" goto :end +goto :choice + +:: Copy files to persistent location, renaming them in the process +:cont +COPY /y %LOCAL_DIR%\%SRC_PRIV_NAME% %OUT_DIR%\%PRIV_NAME% +COPY /y %LOCAL_DIR%\%SRC_PUB_NAME% %OUT_DIR%\%PUB_NAME% +COPY /y %LOCAL_DIR%\%SRC_AES_NAME% %OUT_DIR%\%AES_NAME% +COPY /y %LOCAL_DIR%\%SRC_EIV_NAME% %OUT_DIR%\%EIV_NAME% + +:end +pause \ No newline at end of file diff --git a/2020TPCApp0.cydsn/keygen.bat b/2020TPCApp0.cydsn/keygen.bat new file mode 100644 index 0000000..4a48ed3 --- /dev/null +++ b/2020TPCApp0.cydsn/keygen.bat @@ -0,0 +1,143 @@ +::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: +:: +:: File Name: keygen.bat +:: +:: Version: 1.0 +:: +:: Description: +:: Simple script to generate the RSA-2048 public and private keys using OpenSSL. +:: Once created, the script calls a python script to print out the public key +:: modulus that is ready to be inserted into cy_publicKey struct in +:: cy_si_keyStorage.c. +:: The script also generates a 128 bit random number to be used for the AES +:: private key and EIV. +:: +::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: +:: Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +:: This software is owned by Cypress Semiconductor Corporation and is protected +:: by and subject to worldwide patent and copyright laws and treaties. +:: Therefore, you may use this software only as provided in the license agreement +:: accompanying the software package from which you obtained this software. +:: CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +:: WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, +:: IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: + +@echo off +set OUT_DIR="%~dp0\keys_generated" +set LOCAL_DIR=keys_generated +set PRIV_NAME=rsa_private_generated.txt +set PUB_NAME=rsa_public_generated.txt +set MOD_NAME=rsa_to_c_generated.txt + +set AES_TEMP=aes_private_generated_temp.txt +set EIV_TEMP=aes_eiv_generated_temp.txt +set AES_NAME=aes_private_generated.txt +set EIV_NAME=aes_eiv_generated.txt +set AES_ARRAY=aes_private_array_generated.txt + +:: Check if OpenSSL and Python are correctly installed +set ALLOK=1 +CALL :testOpenSSL +CALL :testPython +IF %ALLOK% == 0 ( + echo. + pause + goto :end +) +IF NOT EXIST %OUT_DIR% mkdir %OUT_DIR% + +:: Delete temp files +IF EXIST %OUT_DIR%\%AES_TEMP% DEL /F %OUT_DIR%\%AES_TEMP% +IF EXIST %OUT_DIR%\%EIV_TEMP% DEL /F %OUT_DIR%\%EIV_TEMP% + +:: Generate the RSA-2048 public and private keys +openssl genrsa -out %OUT_DIR%\%PRIV_NAME% 2048 +openssl rsa -in %OUT_DIR%\%PRIV_NAME% -outform PEM -pubout -out %OUT_DIR%\%PUB_NAME% + +:: Generate a 128bit random number +openssl rand -hex -out %OUT_DIR%\%AES_TEMP% 16 +openssl rand -hex -out %OUT_DIR%\%EIV_TEMP% 16 + +:: Check if files exist before processing +IF NOT EXIST %LOCAL_DIR%\%AES_TEMP% ( + echo Could not find OpenSSL generated files. If the error persists, check OpenSSL installation and permissions. + echo. + pause + goto :end +) +IF NOT EXIST %LOCAL_DIR%\%AES_TEMP% ( + echo Could not find OpenSSL generated files. If the error persists, check OpenSSL installation and permissions. + echo. + pause + goto :end +) + +IF EXIST %OUT_DIR%\%AES_NAME% DEL /F %OUT_DIR%\%AES_NAME% +IF EXIST %OUT_DIR%\%EIV_NAME% DEL /F %OUT_DIR%\%EIV_NAME% +IF EXIST %OUT_DIR%\%AES_ARRAY% DEL /F %OUT_DIR%\%AES_ARRAY% + +:: Remove new line characters from AES and EIV files +FOR /F "Usebackq Tokens=*" %%@ IN ("%LOCAL_DIR%\%AES_TEMP%") DO ( +> %LOCAL_DIR%\%AES_NAME% + +FOR /F "Usebackq Tokens=*" %%@ IN ("%LOCAL_DIR%\%EIV_TEMP%") DO ( +> %LOCAL_DIR%\%EIV_NAME% + +:: Delete temp files +IF EXIST %OUT_DIR%\%AES_TEMP% DEL /F %OUT_DIR%\%AES_TEMP% +IF EXIST %OUT_DIR%\%EIV_TEMP% DEL /F %OUT_DIR%\%EIV_TEMP% + +:: Generate a C array with the AES private key +setlocal enableDelayedExpansion +set /p str=<%LOCAL_DIR%\%AES_NAME% +set counter=1 +set "out=" +for /f delims^=^ eol^= %%A in ('cmd /u /v:on /c echo(^^!str^^!^|more') do ( + IF "!counter!" == "1" ( + set "out=!out!, 0x^%%A" + set "counter=0" + ) ELSE ( + set "out=!out!%%A" + set "counter=1" + ) + ) +set "out=!out:~2!" + +echo static const uint8_t AES128_Key[16] = {!out!}; >> %OUT_DIR%\%AES_ARRAY% + +:: Create C-code ready public key +%~dp0\rsa_to_c.py %OUT_DIR%\%PUB_NAME% > %OUT_DIR%\%MOD_NAME% + +goto :end + +:testOpenSSL +openssl version >nul 2>nul +IF ERRORLEVEL 1 CALL :errOpenSSL +EXIT /B + +:testPython +python --version >nul 2>nul +IF ERRORLEVEL 1 CALL :errPython +EXIT /B + +:errOpenSSL +echo. +echo OpenSSL could not be found. +echo If OpenSSL is installed, add the OpenSSL binaries directory to the system Path variable. +echo A restart may be required. +set ALLOK=0 +EXIT /B + +:errPython +echo. +echo Python could not be found. +echo Python is required to generate the RSA public key C array. +echo Please install Python or check that it is included in the system Path variable. +set ALLOK=0 +EXIT /B + +:end +pause diff --git a/2020TPCApp0.cydsn/main_cm0p.c b/2020TPCApp0.cydsn/main_cm0p.c new file mode 100644 index 0000000..ff3bc37 --- /dev/null +++ b/2020TPCApp0.cydsn/main_cm0p.c @@ -0,0 +1,237 @@ +/******************************************************************************* +* File Name: main_cm0p.c +* +* Version: 1.30 +* +* Description: This file provides the source code for the DFU (App0) +* running on the core CM0+ (core0). +* App0 core0 firmware does the following: +* - Switches to the App1 on reset if it was scheduled. +* - Else starts App0 core1 firmware. +* +* Related Document: Code example CE216767.pdf +* +* Hardware Dependency: CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit +* CY5677 CySmart USB Dongle +* +****************************************************************************** +* Copyright (2019), Cypress Semiconductor Corporation. +****************************************************************************** +* This software is owned by Cypress Semiconductor Corporation (Cypress) and is +* protected by and subject to worldwide patent protection (United States and +* foreign), United States copyright laws and international treaty provisions. +* Cypress hereby grants to licensee a personal, non-exclusive, non-transferable +* license to copy, use, modify, create derivative works of, and compile the +* Cypress Source Code and derivative works for the sole purpose of creating +* custom software in support of licensee product to be used only in conjunction +* with a Cypress integrated circuit as specified in the applicable agreement. +* Any reproduction, modification, translation, compilation, or representation of +* this software except as specified above is prohibited without the express +* written permission of Cypress. +* +* Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH +* REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +* Cypress reserves the right to make changes without further notice to the +* materials described herein. Cypress does not assume any liability arising out +* of the application or use of any product or circuit described herein. Cypress +* does not authorize its products for use as critical components in life-support +* systems where a malfunction or failure may reasonably be expected to result in +* significant injury to the user. The inclusion of Cypress' product in a life- +* support systems application implies that the manufacturer assumes all risk of +* such use and in doing so indemnifies Cypress against all charges. Use may be +* limited by and subject to the applicable Cypress software license agreement. +*******************************************************************************/ + +#include "dfu/cy_dfu.h" +#include "project.h" +#include "cy_si_config.h" + +/* +* Set this define to any value different than 0, to use a standard TOC2, +* erase the public key, and enable the device to run code generated by other projects. +*/ +#define UNLOCK_SYSTEM (1u) + +#if CY_DFU_OPT_CRYPTO_HW != 0 + #define MY_CHAN_CRYPTO (uint32_t)(3u) /* IPC data channel for the Crypto */ + #define MY_INTR_CRYPTO_SRV (uint32_t)(1u) /* IPC interrupt structure for the Crypto server */ + #define MY_INTR_CRYPTO_CLI (uint32_t)(2u) /* IPC interrupt structure for the Crypto client */ + #define MY_INTR_CRYPTO_SRV_MUX (IRQn_Type)(2u) /* CM0+ IPC interrupt mux number the Crypto server */ + #define MY_INTR_CRYPTO_CLI_MUX (IRQn_Type)(3u) /* CM0+ IPC interrupt mux number the Crypto client */ + #define MY_INTR_CRYPTO_ERR_MUX (IRQn_Type)(4u) /* CM0+ ERROR interrupt mux number the Crypto server */ + + const cy_stc_crypto_config_t cryptoConfig = + { + /* .ipcChannel */ MY_CHAN_CRYPTO, + /* .acquireNotifierChannel */ MY_INTR_CRYPTO_SRV, + /* .releaseNotifierChannel */ MY_INTR_CRYPTO_CLI, + /* .releaseNotifierConfig */ { + #if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ MY_INTR_CRYPTO_CLI_MUX, + /* .cm0pSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */ + #else + /* .intrSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */ + #endif + /* .intrPriority */ 2u, + }, + /* .userCompleteCallback */ NULL, + /* .userGetDataHandler */ NULL, + /* .userErrorHandler */ NULL, + /* .acquireNotifierConfig */ { + #if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ MY_INTR_CRYPTO_SRV_MUX, /* to use with DeepSleep mode should be in DeepSleep capable muxer's range */ + /* .cm0pSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */ + #else + /* .intrSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */ + #endif + /* .intrPriority */ 2u, + }, + /* .cryptoErrorIntrConfig */ { + #if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ MY_INTR_CRYPTO_ERR_MUX, + /* .cm0pSrc */ cpuss_interrupt_crypto_IRQn, + #else + /* .intrSrc */ cpuss_interrupt_crypto_IRQn, + #endif + /* .intrPriority */ 2u, + } + }; + + cy_stc_crypto_server_context_t cryptoServerContext; + cy_en_crypto_status_t cryptoStatus; +#endif + +#if UNLOCK_SYSTEM == (0u) +/* Flashboot parameters */ +#define CY_SI_FLASHBOOT_FLAGS ((CY_SI_FLASHBOOT_VALIDATE_YES << CY_SI_TOC_FLAGS_APP_VERIFY_POS) \ + | (CY_SI_FLASHBOOT_WAIT_20MS << CY_SI_TOC_FLAGS_DELAY_POS) \ + | (CY_SI_FLASHBOOT_CLK_25MHZ << CY_SI_TOC_FLAGS_CLOCKS_POS)) + +/* TOC Part 2 Definition */ +CY_SECTION(".cy_toc_part2") __USED +const cy_stc_si_toc_t cy_toc2 = +{ + .objSize = sizeof(cy_stc_si_toc_t) - sizeof(uint32_t), /**< Object Size (Bytes) excluding CRC */ + .magicNum = CY_SI_TOC2_MAGICNUMBER, /**< TOC2 ID (magic number) */ + .userKeyAddr = (uint32_t) &CySecureKeyStorage, /**< User key storage address */ + .smifCfgAddr = 0UL, /**< SMIF config list pointer */ + .appAddr1 = CY_DFU_APP0_VERIFY_START, /**< App0 start address */ + .appFormat1 = CY_DFU_CYPRESS_APP, /**< App0 Format */ + .shashObj = 1UL, /**< Include public key in the SECURE HASH */ + .sigKeyAddr = (uint32_t)&SFLASH->PUBLIC_KEY, /**< Address of signature verification key */ + .tocFlags = CY_SI_FLASHBOOT_FLAGS, /**< Flashboot flags stored in TOC2 */ + .crc = 0UL, /**< CRC populated by cymcuelftool */ +}; + +/* Assuming App0 is located at start of flash, change define if different */ +#define APP0_START_ADDRESS CY_FLASH_BASE + +/* Cypress Standard Application Format Header */ +CY_SECTION(".cy_app_header") __USED +const cy_stc_user_appheader_t applicationHeader = +{ + .objSize = CY_DFU_APP0_VERIFY_LENGTH, /* Application Size (Bytes) excluding hash */ + .appId = CY_SI_APP_VERSION, /* App ID */ + .appAttributes = 0UL, /* Reserved */ + .numCores = 2UL, /* CM0+ and CM4 */ + .core0Vt = (uint32_t)(&__Vectors[0]) - APP0_START_ADDRESS - offsetof(cy_stc_user_appheader_t, core0Vt), /* Offset to CM0+ Vector Table in flash */ + .core1Vt = (uint32_t)(&__cy_app_core1_start_addr) - APP0_START_ADDRESS - offsetof(cy_stc_user_appheader_t, core1Vt), /* Offset to CM4 Vector Table in flash */ + .core0Id = CY_ARM_CM0P_CPUID, /* ARM CM0+ CPU ID */ + .core1Id = CY_ARM_CM4_CPUID, /* ARM CM4 CPU ID */ +}; +#endif /* UNLOCK_SYSTEM == (0u) */ + +#if UNLOCK_SYSTEM != (0u) +/* Flashboot parameters */ +#define CY_SI_FLASHBOOT_FLAGS ((CY_SI_FLASHBOOT_VALIDATE_NO << CY_SI_TOC_FLAGS_APP_VERIFY_POS) \ + | (CY_SI_FLASHBOOT_WAIT_20MS << CY_SI_TOC_FLAGS_DELAY_POS) \ + | (CY_SI_FLASHBOOT_CLK_25MHZ << CY_SI_TOC_FLAGS_CLOCKS_POS)) + +/* Standard TOC Part 2 Definition */ +CY_SECTION(".cy_toc_part2") __USED +const cy_stc_si_toc_t cy_toc2 = +{ + .objSize = sizeof(cy_stc_si_toc_t) - sizeof(uint32_t), /**< Object Size (Bytes) excluding CRC */ + .magicNum = CY_SI_TOC2_MAGICNUMBER, /**< TOC2 ID (magic number) */ + .userKeyAddr = 0UL, /**< User key storage address */ + .smifCfgAddr = 0UL, /**< SMIF config list pointer */ + .appAddr1 = CY_FLASH_BASE, /**< Main Flash base address */ + .appFormat1 = CY_DFU_BASIC_APP, /**< Basic format */ + .shashObj = 0UL, + .sigKeyAddr = 0UL, /**< Address of signature verification key */ + .tocFlags = CY_SI_FLASHBOOT_FLAGS, /**< Flashboot flags stored in TOC2 */ + .crc = 0UL, /**< CRC populated by cymcuelftool */ +}; +#endif /* UNLOCK_SYSTEM != 0UL */ + +/******************************************************************************* +* Function Name: main +******************************************************************************** +* +* Summary: +* Main function of App0 core0. Unfreezes IO and sets up the user button (SW2) +* as the hibernate wakeup source. Afterwards initializes core1 (CM4) and goes +* into deep sleep. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +int main(void) +{ + /* Unfreeze IO after Hibernate */ + if(Cy_SysPm_GetIoFreezeStatus()) + { + Cy_SysPm_IoUnfreeze(); + } + /* Set SW2 as hibernate wakeup pin */ + Cy_SysPm_SetHibWakeupSource(CY_SYSPM_HIBPIN1_LOW); + + /* enable global interrupts */ + __enable_irq(); + +#if CY_DFU_OPT_CRYPTO_HW != 0 + /* Start the Crypto Server */ + Cy_Crypto_Server_Start(&cryptoConfig, &cryptoServerContext); +#endif + + /* Enable CM4 with the CM4 start address defined in the + DFU SDK linker script */ + Cy_SysEnableCM4( (uint32_t)(&__cy_app_core1_start_addr) ); + + for (;;) + { + /* Process crypto server requests */ + Cy_Crypto_Server_Process(); + //Go into Deep Sleep + Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT); + } +} + +/******************************************************************************* +* Function Name: Cy_OnResetUser +******************************************************************************** +* +* Summary: +* This function is called at the start of Reset_Handler(). It is a weak function +* that may be redefined by user code. +* DFU SDK requires it to call Cy_DFU_OnResetApp0(). +* Checks if an App switch has been scheduled and transfers control to it. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Cy_OnResetUser(void) +{ + Cy_DFU_OnResetApp0(); +} + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/main_cm4.c b/2020TPCApp0.cydsn/main_cm4.c new file mode 100644 index 0000000..b925e08 --- /dev/null +++ b/2020TPCApp0.cydsn/main_cm4.c @@ -0,0 +1,812 @@ +/******************************************************************************* +* File Name: main_cm4.c +* +* Version: 1.30 +* +* Description: This file provides the source code for the DFU (App0) +* running on the core CM4 (core1). +* App0 core1 firmware does the following: +* - Downloads App1 firmware image +* - Switches to App1 if App1 image has successfully downloaded +* and is valid +* - Switches to existing App1 if button is pressed +* - Turn on an LED depending on status +* - Hibernates on timeout +******************************************************************************* +* Related Document: CE216767.pdf +* +* Hardware Dependency: CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit +* CY5677 CySmart USB Dongle +* +****************************************************************************** +* Copyright (2019), Cypress Semiconductor Corporation. +****************************************************************************** +* This software is owned by Cypress Semiconductor Corporation (Cypress) and is +* protected by and subject to worldwide patent protection (United States and +* foreign), United States copyright laws and international treaty provisions. +* Cypress hereby grants to licensee a personal, non-exclusive, non-transferable +* license to copy, use, modify, create derivative works of, and compile the +* Cypress Source Code and derivative works for the sole purpose of creating +* custom software in support of licensee product to be used only in conjunction +* with a Cypress integrated circuit as specified in the applicable agreement. +* Any reproduction, modification, translation, compilation, or representation of +* this software except as specified above is prohibited without the express +* written permission of Cypress. +* +* Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH +* REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +* Cypress reserves the right to make changes without further notice to the +* materials described herein. Cypress does not assume any liability arising out +* of the application or use of any product or circuit described herein. Cypress +* does not authorize its products for use as critical components in life-support +* systems where a malfunction or failure may reasonably be expected to result in +* significant injury to the user. The inclusion of Cypress' product in a life- +* support systems application implies that the manufacturer assumes all risk of +* such use and in doing so indemnifies Cypress against all charges. Use may be +* limited by and subject to the applicable Cypress software license agreement. +*******************************************************************************/ + +#include +#include "project.h" +#include "debug.h" +#include "ias.h" +#include "transport_ble.h" + +#if CY_DFU_OPT_CRYPTO_HW != 0 + #define MY_CHAN_CRYPTO (uint32_t)(3u) /* IPC data channel for the Crypto */ + #define MY_INTR_CRYPTO_SRV (uint32_t)(1u) /* IPC interrupt structure for the Crypto server */ + #define MY_INTR_CRYPTO_CLI (uint32_t)(2u) /* IPC interrupt structure for the Crypto client */ + #define MY_INTR_CRYPTO_SRV_MUX (IRQn_Type)(2u) /* CM0+ IPC interrupt mux number the Crypto server */ + #define MY_INTR_CRYPTO_CLI_MUX (IRQn_Type)(3u) /* CM0+ IPC interrupt mux number the Crypto client */ + #define MY_INTR_CRYPTO_ERR_MUX (IRQn_Type)(4u) /* CM0+ ERROR interrupt mux number the Crypto server */ + + const cy_stc_crypto_config_t cryptoConfig = + { + /* .ipcChannel */ MY_CHAN_CRYPTO, + /* .acquireNotifierChannel */ MY_INTR_CRYPTO_SRV, + /* .releaseNotifierChannel */ MY_INTR_CRYPTO_CLI, + /* .releaseNotifierConfig */ { + #if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ MY_INTR_CRYPTO_CLI_MUX, + /* .cm0pSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */ + #else + /* .intrSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */ + #endif + /* .intrPriority */ 2u, + }, + /* .userCompleteCallback */ NULL, + /* .userGetDataHandler */ NULL, + /* .userErrorHandler */ NULL, + /* .acquireNotifierConfig */ { + #if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ MY_INTR_CRYPTO_SRV_MUX, /* to use with DeepSleep mode should be in DeepSleep capable muxer's range */ + /* .cm0pSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */ + #else + /* .intrSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */ + #endif + /* .intrPriority */ 2u, + }, + /* .cryptoErrorIntrConfig */ { + #if (CY_CPU_CORTEX_M0P) + /* .intrSrc */ MY_INTR_CRYPTO_ERR_MUX, + /* .cm0pSrc */ cpuss_interrupt_crypto_IRQn, + #else + /* .intrSrc */ cpuss_interrupt_crypto_IRQn, + #endif + /* .intrPriority */ 2u, + } + }; + cy_stc_crypto_context_t cryptoContext; + cy_en_crypto_status_t cryptoStatus; +#endif + +/* BLE GAPP Connection Settings */ +#define CYBLE_GAPP_CONNECTION_INTERVAL_MIN (0x000Cu) /* 15 ms - (N * 1,25)*/ +#define CYBLE_GAPP_CONNECTION_INTERVAL_MAX (0x000Cu) /* 15 ms */ +#define CYBLE_GAPP_CONNECTION_SLAVE_LATENCY (0x0000u) +#define CYBLE_GAPP_CONNECTION_TIME_OUT (0x00C8u) /* 2000 ms */ + +/* BLE Callback function, defined in this file */ +void AppCallBack(uint32 event, void* eventParam); + +/* Local functions */ +static cy_en_dfu_status_t CopyRow(uint32_t dest, uint32_t src, uint32_t rowSize, cy_stc_dfu_params_t * params); +static cy_en_dfu_status_t HandleMetadata(cy_stc_dfu_params_t *params); +static bool IsButtonPressed(uint16_t timeoutInMilis); +static uint32_t counterTimeoutSeconds(uint32_t seconds, uint32_t timeout); + +/* This section is used to verify an application signature + For sha256 verification, set the number of elements in the array to 64, and + in bootload_common.ld set __cy_boot_signature_size = 256. +*/ +CY_SECTION(".cy_app_signature") __USED static const uint32_t cy_bootload_appSignature[64]; + +/******************************************************************************* +* Function Name: main +******************************************************************************** +* +* Summary: +* Main function of the DFU application (App0). +* 1. If application started from non-software reset it validates App1 +* 1.1. If App1 is valid it switches to App1, else goto #2. +* 2. Start DFU communication. +* 3. If updated application has been received it validates this app. +* 4. If App1 is valid it switches to it, else wait for new application. +* 5. If 300 seconds have passed and no new application has been received +* then validate App1, if it is valid then switch to it, else hibernate +* (Happens in the BLE AppCallBack). +* +*******************************************************************************/ +int main(void) +{ + /* timeout for Cy_DFU_Continue(), in milliseconds */ + const uint32_t paramsTimeout = 20u; + + /* used to configure DFU */ + static cy_stc_dfu_params_t dfuParams; + + /* Status codes from DFU SDK API */ + cy_en_dfu_status_t status; + + /* SW2 released after deciding to stay in App0 */ + bool buttonReleased = false; + + /* + * DFU state, one of + * - CY_DFU_STATE_NONE + * - CY_DFU_STATE_UPDATING + * - CY_DFU_STATE_FINISHED + * - CY_DFU_STATE_FAILED + */ + uint32_t state = CY_DFU_STATE_NONE; + + cy_en_ble_api_result_t apiResult; + cy_stc_ble_stack_lib_version_t stackVersion; + + /* + * Used to count seconds, to convert counts to seconds use + * counterTimeoutSeconds(SECONDS, paramsTimeout) + */ + uint32_t count = 0; + + uint32_t ledTimer = 0; + +#if CY_DFU_OPT_CRYPTO_HW != 0 + cy_en_crypto_status_t cryptoStatus; +#endif + + /* Buffer to store DFU commands */ + CY_ALIGN(4) static uint8_t buffer[CY_DFU_SIZEOF_DATA_BUFFER]; + + /* Buffer for DFU packets for Transport API */ + CY_ALIGN(4) static uint8_t packet[CY_DFU_SIZEOF_CMD_BUFFER]; + + /* Enable global interrupts */ + __enable_irq(); + + /* Start UART Services */ + UART_START(); + + /* Initializes LEDs */ + InitLED(); + +#if CY_DFU_OPT_CRYPTO_HW != 0 + /* Initialize the Crypto Client code */ + cryptoStatus = Cy_Crypto_Init(&cryptoConfig, &cryptoContext); + if (cryptoStatus != CY_CRYPTO_SUCCESS) + { + /* Crypto not initialized; debug what is the problem */ + Cy_SysLib_Halt(0x00u); + } + cryptoStatus = Cy_Crypto_Enable(); + if (cryptoStatus != CY_CRYPTO_SUCCESS) + { + /* Crypto not enabled; debug what is the problem */ + Cy_SysLib_Halt(0x00u); + } +#endif /* CY_DFU_OPT_CRYPTO_HW != 0 */ + + /* Initialize dfuParams structure and DFU SDK state */ + dfuParams.timeout = paramsTimeout; + dfuParams.dataBuffer = &buffer[0]; + dfuParams.packetBuffer = &packet[0]; + + status = Cy_DFU_Init(&state, &dfuParams); + + /* Ensure DFU Metadata is valid */ + status = HandleMetadata(&dfuParams); + if (status != CY_DFU_SUCCESS) + { + Cy_SysLib_Halt(0x00u); + } + + /* + * In the case of non-software reset and user does not + * want to stay in App0, check if there is a valid app image. + * If there is - switch to it. + */ + if ((Cy_SysLib_GetResetReason() != CY_SYSLIB_RESET_SOFT) && (IsButtonPressed(2000u) == false)) + { + status = Cy_DFU_ValidateApp(1u, &dfuParams); + if (status == CY_DFU_SUCCESS) + { + /* + * Clear reset reason because Cy_DFU_ExecuteApp() performs + * a software reset. + * Without clearing two reset reasons would be present. + */ + do + { + Cy_SysLib_ClearResetReason(); + }while(Cy_SysLib_GetResetReason() != 0); + /* Never returns */ + Cy_DFU_ExecuteApp(1u); + } + } + + /* Initialize DFU communication */ + Cy_DFU_TransportStart(); + /* Initializes the Immediate Alert Service */ + IasInit(); + + /* Output current stack version to UART */ + apiResult = Cy_BLE_GetStackLibraryVersion(&stackVersion); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("CyBle_GetStackLibraryVersion API Error: 0x%2.2x \r\n", apiResult); + } + else + { + DBG_PRINTF("Stack Version: %d.%d.%d.%d \r\n", stackVersion.majorVersion, + stackVersion.minorVersion, stackVersion.patch, stackVersion.buildNumber); + } + + for(;;) + { + /* CyBle_ProcessEvents() allows BLE stack to process pending events */ + Cy_BLE_ProcessEvents(); + + /* Process DFU commands */ + status = Cy_DFU_Continue(&state, &dfuParams); + ++count; + + switch(state) + { + case CY_DFU_STATE_FINISHED: + /* Finished downloading the application image */ + + /* Validate downloaded application, if it is valid then switch to it */ + status = Cy_DFU_ValidateApp(1u, &dfuParams); + if (status == CY_DFU_SUCCESS) + { + Cy_DFU_TransportStop(); + /* + * Clear reset reason because Cy_DFU_ExecuteApp() performs + * a software reset. + * Without clearing two reset reasons would be present. + */ + do + { + Cy_SysLib_ClearResetReason(); + }while(Cy_SysLib_GetResetReason() != 0); + /* Never returns */ + Cy_DFU_ExecuteApp(1u); + } + else if (status == CY_DFU_ERROR_VERIFY) + { + /* + * Restarts DFU, alternatives are to Halt MCU here + * or switch to the other app if it is valid. + * Error code may be handled here, i.e. print to debug UART. + */ + status = Cy_DFU_Init(&state, &dfuParams); + /* Reset LED */ + ConnectedLED(); + ledTimer = 0; + Cy_DFU_TransportReset(); + } + break; + case CY_DFU_STATE_FAILED: + /* Handle error here */ + DBG_PRINTF("Downloading has failed with error code 0x%x, try again\r\n", status); + + /* In this Code Example just restart DFU process */ + status = Cy_DFU_Init(&state, &dfuParams); + /* Reset LED */ + ConnectedLED(); + ledTimer = 0; + Cy_DFU_TransportReset(); + break; + case CY_DFU_STATE_UPDATING: + /* Reset timeout counter, if a command was correctly received */ + if (status == CY_DFU_SUCCESS) + { + count = 0u; + } + else if (status == CY_DFU_ERROR_TIMEOUT) + { + /* + * if no command has been received during 5 seconds when DFU + * has started then restart DFU. + */ + if (count >= counterTimeoutSeconds(5u, paramsTimeout)) + { + count = 0u; + Cy_DFU_Init(&state, &dfuParams); + /* Reset LED */ + ConnectedLED(); + ledTimer = 0; + Cy_DFU_TransportReset(); + } + } + else + { + count = 0u; + /* Delay because Transport still may be sending error response to a host */ + Cy_SysLib_Delay(paramsTimeout); + Cy_DFU_Init(&state, &dfuParams); + Cy_DFU_TransportReset(); + } + break; + } + + /* LED logic, constant values are optimized out. */ + /* Reset timer after 2 seconds */ + if(ledTimer == (2000u / paramsTimeout)) ledTimer = 0; + /* Every 100 miliseconds */ + if(!(ledTimer % (100u / paramsTimeout))) + { + /* Generates two 100 miliseconds pulses, every 2 seconds */ + if((state == CY_DFU_STATE_UPDATING) && (ledTimer < (400u / paramsTimeout))) + { + BlinkLED(); + } + /* Generates one 100 miliseconds pulse, every 2 seconds */ + else if ((Cy_BLE_GetAdvertisementState() == CY_BLE_ADV_STATE_ADVERTISING) + && (ledTimer < (200u / paramsTimeout))) + { + BlinkLED(); + } + else + { + /* Remain OFF */ + ConnectedLED(); + } + } + ++ledTimer; + + /* Check if a switch to the other app is requested and perform the switch if it is */ + if((buttonReleased == true) && (state == CY_DFU_STATE_NONE)) + { + bool switchRequested = false; + if (alertLevel != 0) + { + switchRequested = true; + } + else if(IsButtonPressed(500u) == true) + { + switchRequested = true; + buttonReleased = false; + } + if (switchRequested) + { + /* Validate and switch to App1 */ + cy_en_dfu_status_t status = Cy_DFU_ValidateApp(1u, &dfuParams); + + if (status == CY_DFU_SUCCESS) + { + Cy_DFU_TransportStop(); + /* + * Clear reset reason because Cy_DFU_ExecuteApp() performs + * a software reset. + * Without clearing two reset reasons would be present. + */ + do + { + Cy_SysLib_ClearResetReason(); + }while(Cy_SysLib_GetResetReason() != 0); + /* Never returns */ + Cy_DFU_ExecuteApp(1u); + } + } + } + else + { + buttonReleased = Cy_GPIO_Read(PIN_SW2_PORT, PIN_SW2_NUM); + } + } +} + + +/******************************************************************************* +* Function Name: IsButtonPressed +******************************************************************************** +* Checks if button is pressed for a 'timeoutInMilis' time. +* +* Params: +* timeout: Amount of time to check if button was pressed. Broken into +* 20 miliseconds steps. +* Returns: +* true if button is pressed for specified amount. +* false otherwise. +*******************************************************************************/ +static bool IsButtonPressed(uint16_t timeoutInMilis) +{ + uint16_t buttonTime = 0; + bool buttonPressed = false; + timeoutInMilis /= 20; + while(Cy_GPIO_Read(PIN_SW2_PORT, PIN_SW2_NUM) == 0u) + { + Cy_SysLib_Delay(20u); + if(++buttonTime == timeoutInMilis) + { + /* time has passed */ + buttonPressed = true; + break; + } + } + return buttonPressed; +} + +/******************************************************************************* +* Function Name: counterTimeoutSeconds +******************************************************************************** +* Returns number of counts that correspond to number of seconds passed as +* a parameter. +* E.g. comparing counter with 300 seconds is like this. +* --- +* uint32_t counter = 0u; +* for (;;) +* { +* Cy_SysLib_Delay(UART_TIMEOUT); +* ++count; +* if (count >= counterTimeoutSeconds(seconds: 300u, timeout: UART_TIMEOUT)) +* { +* count = 0u; +* DoSomething(); +* } +* } +* --- +* +* Both parameters are required to be compile time constants, +* so this function gets optimized out to single constant value. +* +* Parameters: +* seconds Number of seconds to pass. Must be less that 4_294_967 seconds. +* timeout Timeout for Cy_DFU_Continue() function, in milliseconds. +* Must be greater than zero. +* It is recommended to be a value that produces no reminder +* for this function to be precise. +* Return: +* See description. +*******************************************************************************/ +static uint32_t counterTimeoutSeconds(uint32_t seconds, uint32_t timeout) +{ + return (seconds * 1000ul) / timeout; +} + +/******************************************************************************* +* Function Name: CopyRow +******************************************************************************** +* Copies data from a "src" address to a flash row with the address "dest". +* If "src" data is the same as "dest" data then no copy is needed. +* +* Parameters: +* dest Destination address. Has to be an address of the start of flash row. +* src Source address. Has to be properly aligned. +* rowSize Size of flash row. +* +* Returns: +* CY_DFU_SUCCESS if operation is successful. +* Error code in a case of failure. +*******************************************************************************/ +static cy_en_dfu_status_t CopyRow(uint32_t dest, uint32_t src, uint32_t rowSize, cy_stc_dfu_params_t * params) +{ + cy_en_dfu_status_t status; + + /* Save params->dataBuffer value */ + uint8_t *buffer = params->dataBuffer; + + /* Compare "dest" and "src" content */ + params->dataBuffer = (uint8_t *)src; + status = Cy_DFU_ReadData(dest, rowSize, CY_DFU_IOCTL_COMPARE, params); + + /* Restore params->dataBuffer */ + params->dataBuffer = buffer; + + /* If "dest" differs from "src" then copy "src" to "dest" */ + if (status != CY_DFU_SUCCESS) + { + (void) memcpy((void *) params->dataBuffer, (const void*)src, rowSize); + status = Cy_DFU_WriteData(dest, rowSize, CY_DFU_IOCTL_WRITE, params); + } + /* Restore params->dataBuffer */ + params->dataBuffer = buffer; + + return (status); +} + +/******************************************************************************* +* Function Name: HandleMetadata +******************************************************************************** +* The goal of this function is to make DFU SDK metadata (MD) valid. +* The following algorithm is used (in C-like pseudocode): +* --- +* if (isValid(MD) == true) +* { if (MDC != MD) +* MDC = MD; +* } else +* { if(isValid(MDC) ) +* MD = MDC; +* #if MD Writeable +* else +* MD = INITIAL_VALUE; +* #endif +* } +* --- +* Here MD is metadata flash row, MDC is flash row with metadata copy, +* INITIAL_VALUE is known initial value. +* +* In this code example MDC is placed in the next flash row after the MD, and +* INITIAL_VALUE is MD with only CRC, App0 start and size initialized, +* all the other fields are not touched. This is only done if metadata is +* writeable when downloading. +* +* Parameters: +* params A pointer to a DFU SDK parameters structure. +* +* Returns: +* - CY_DFU_SUCCESS when finished normally. +* - Any other status code on error. +*******************************************************************************/ +static cy_en_dfu_status_t HandleMetadata(cy_stc_dfu_params_t *params) +{ + const uint32_t MD = (uint32_t)(&__cy_boot_metadata_addr ); /* MD address */ + const uint32_t mdSize = (uint32_t)(&__cy_boot_metadata_length ); /* MD size, assumed to be one flash row */ + const uint32_t MDC = MD + mdSize; /* MDC address */ + + cy_en_dfu_status_t status = CY_DFU_SUCCESS; + + status = Cy_DFU_ValidateMetadata(MD, params); + if (status == CY_DFU_SUCCESS) + { + /* Checks if MDC equals to DC, if no then copies MD to MDC */ + status = CopyRow(MDC, MD, mdSize, params); + } + else + { + status = Cy_DFU_ValidateMetadata(MDC, params); + if (status == CY_DFU_SUCCESS) + { + /* Copy MDC to MD */ + status = CopyRow(MD, MDC, mdSize, params); + } + #if CY_DFU_METADATA_WRITABLE != 0 + if (status != CY_DFU_SUCCESS) + { + const uint32_t elfStartAddress = 0x10000000; + const uint32_t elfAppSize = 0x40000; + /* Set MD to INITIAL_VALUE */ + status = Cy_DFU_SetAppMetadata(0u, elfStartAddress, elfAppSize, params); + } + #endif /* CY_DFU_METADATA_WRITABLE != 0 */ + } + return (status); +} + + +/******************************************************************************* +* Function Name: AppCallBack() +******************************************************************************** +* +* Summary: +* This is an event callback function to receive events from the BLE Component. +* Used in Cy_DFU_TransportStart() +* +* event - the event code +* *eventParam - the event parameters +* +*******************************************************************************/ +void AppCallBack(uint32 event, void* eventParam) +{ + cy_en_ble_api_result_t apiResult; + + static cy_stc_ble_gap_sec_key_info_t keyInfo = + { + .localKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST | + CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST | + CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST, + .exchangeKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST | + CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST | + CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST | + CY_BLE_GAP_SMP_RESP_ENC_KEY_DIST | + CY_BLE_GAP_SMP_RESP_IRK_KEY_DIST | + CY_BLE_GAP_SMP_RESP_CSRK_KEY_DIST, + }; + + switch (event) + { + /********************************************************** + * General Events + ***********************************************************/ + + /* This event received when BLE communication starts */ + case CY_BLE_EVT_STACK_ON: + /* Enter into discoverable mode so that remote can search it. */ + apiResult = Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, 0u); + if(apiResult != CY_BLE_SUCCESS) + { + } + + apiResult = Cy_BLE_GAP_GenerateKeys(&keyInfo); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("CyBle_GapGenerateKeys API Error: %d \r\n", apiResult); + } + break; + + /* This event indicates that some internal HW error has occurred. */ + case CY_BLE_EVT_HARDWARE_ERROR: + DBG_PRINTF("CYBLE_EVT_HARDWARE_ERROR\r\n"); + break; + /********************************************************** + * GAP Events + ***********************************************************/ + case CY_BLE_EVT_GAP_AUTH_REQ: + DBG_PRINTF("CYBLE_EVT_AUTH_REQ: security=%x, bonding=%x, ekeySize=%x, err=%x \r\n", + (*(cy_stc_ble_gap_auth_info_t *)eventParam).security, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding, + (*(cy_stc_ble_gap_auth_info_t*)eventParam).ekeySize, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr ); + if ( cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].security + == (CY_BLE_GAP_SEC_MODE_1 | CY_BLE_GAP_SEC_LEVEL_1) ) + { + cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].authErr = + CY_BLE_GAP_AUTH_ERROR_PAIRING_NOT_SUPPORTED; + } + + cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].bdHandle = + ((cy_stc_ble_gap_auth_info_t *)eventParam)->bdHandle; + + apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]); + if(apiResult != CY_BLE_SUCCESS) + { + Cy_BLE_GAP_RemoveOldestDeviceFromBondedList(); + apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("CyBle_GappAuthReqReply API Error: %d \r\n", apiResult); + } + } + break; + + case CY_BLE_EVT_GAP_PASSKEY_ENTRY_REQUEST: + DBG_PRINTF("CYBLE_EVT_PASSKEY_ENTRY_REQUEST press 'p' to enter passkey \r\n"); + break; + + case CY_BLE_EVT_GAP_PASSKEY_DISPLAY_REQUEST: + DBG_PRINTF("CYBLE_EVT_PASSKEY_DISPLAY_REQUEST %6.6d \r\n", *(int *)eventParam); + break; + + case CY_BLE_EVT_GAP_KEYINFO_EXCHNGE_CMPLT: + DBG_PRINTF("CYBLE_EVT_GAP_KEYINFO_EXCHNGE_CMPLT \r\n"); + break; + + case CY_BLE_EVT_GAP_AUTH_COMPLETE: + DBG_PRINTF("AUTH_COMPLETE \r\n"); + break; + + case CY_BLE_EVT_GAP_AUTH_FAILED: + DBG_PRINTF("CYBLE_EVT_AUTH_FAILED: %x \r\n", *(uint8 *)eventParam); + break; + + case CY_BLE_EVT_GAP_DEVICE_CONNECTED: + DBG_PRINTF("CYBLE_EVT_GAP_DEVICE_CONNECTED: %d \r\n", appConnHandle.bdHandle); + + if ( ((*(cy_stc_ble_gap_connected_param_t *)eventParam).connIntv + < CYBLE_GAPP_CONNECTION_INTERVAL_MIN ) || ( + (*(cy_stc_ble_gap_connected_param_t *)eventParam).connIntv + > CYBLE_GAPP_CONNECTION_INTERVAL_MAX ) ) + { + cy_stc_ble_gap_conn_update_param_info_t connUpdateParam; + /* If connection settings do not match expected ones - request parameter update */ + connUpdateParam.connIntvMin = CYBLE_GAPP_CONNECTION_INTERVAL_MIN; + connUpdateParam.connIntvMax = CYBLE_GAPP_CONNECTION_INTERVAL_MAX; + connUpdateParam.connLatency = CYBLE_GAPP_CONNECTION_SLAVE_LATENCY; + connUpdateParam.supervisionTO = CYBLE_GAPP_CONNECTION_TIME_OUT; + connUpdateParam.bdHandle = appConnHandle.bdHandle; + apiResult = Cy_BLE_L2CAP_LeConnectionParamUpdateRequest(&connUpdateParam); + DBG_PRINTF("Cy_BLE_L2CAP_LeConnectionParamUpdateRequest API: 0x%2.2x \r\n", apiResult); + } + keyInfo.SecKeyParam.bdHandle = (*(cy_stc_ble_gap_connected_param_t *)eventParam).bdHandle; + apiResult = Cy_BLE_GAP_SetSecurityKeys(&keyInfo); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("CyBle_GapSetSecurityKeys API Error: %d \r\n", apiResult); + } + break; + + case CY_BLE_EVT_L2CAP_CONN_PARAM_UPDATE_RSP: + DBG_PRINTF("CY_BLE_EVT_L2CAP_CONN_PARAM_UPDATE_RSP, result = %d\r\n", + (*(cy_stc_ble_l2cap_conn_update_rsp_param_t *)eventParam).result); + break; + + case CY_BLE_EVT_GAP_KEYS_GEN_COMPLETE: + DBG_PRINTF("CYBLE_EVT_GAP_KEYS_GEN_COMPLETE \r\n"); + keyInfo.SecKeyParam = (*(cy_stc_ble_gap_sec_key_param_t *)eventParam); + Cy_BLE_GAP_SetIdAddress(&cy_ble_deviceAddress); + break; + + case CY_BLE_EVT_GAP_DEVICE_DISCONNECTED: + DBG_PRINTF("CYBLE_EVT_GAP_DEVICE_DISCONNECTED\r\n"); + /* Put the device into discoverable mode so that a remote can search it. */ + apiResult = Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("StartAdvertisement API Error: %d \r\n", apiResult); + } + break; + + case CY_BLE_EVT_GAP_ENCRYPT_CHANGE: + DBG_PRINTF("CYBLE_EVT_GAP_ENCRYPT_CHANGE: %x \r\n", *(uint8 *)eventParam); + break; + + case CY_BLE_EVT_GAP_CONNECTION_UPDATE_COMPLETE: + DBG_PRINTF("CYBLE_EVT_CONNECTION_UPDATE_COMPLETE: %x \r\n", *(uint8 *)eventParam); + break; + + case CY_BLE_EVT_GAPP_ADVERTISEMENT_START_STOP: + if(Cy_BLE_GetAdvertisementState() == CY_BLE_ADV_STATE_STOPPED) + { + /* Fast and slow advertising period complete, go to low power + * mode (Hibernate mode) and wait for an external + * user event to wake up the device again */ + + /* Stop DFU communication */ + Cy_DFU_TransportStop(); + /* Check if app is valid, if it is then switch to it */ + uint32_t status = Cy_DFU_ValidateApp(1u, NULL); + if (status == CY_DFU_SUCCESS) + { + /* + * Clear reset reason because Cy_DFU_ExecuteApp() performs + * a software reset. + * Without clearing two reset reasons would be present. + */ + do + { + Cy_SysLib_ClearResetReason(); + }while(Cy_SysLib_GetResetReason() != 0); + /* Never returns */ + Cy_DFU_ExecuteApp(1u); + } + /* 300 seconds has passed and App is invalid. Hibernate */ + HibernateLED(); + Cy_SysPm_Hibernate(); + } + break; + + /********************************************************** + * GATT Events + ***********************************************************/ + case CY_BLE_EVT_GATT_CONNECT_IND: + appConnHandle = *(cy_stc_ble_conn_handle_t *)eventParam; + DBG_PRINTF("CYBLE_EVT_GATT_CONNECT_IND: %d \r\n", appConnHandle.bdHandle); + break; + + case CY_BLE_EVT_GATT_DISCONNECT_IND: + DBG_PRINTF("CYBLE_EVT_GATT_DISCONNECT_IND: %d \r\n", ((cy_stc_ble_conn_handle_t *)eventParam)->bdHandle); + break; + + case CY_BLE_EVT_GATTS_WRITE_CMD_REQ: + DBG_PRINTF("CYBLE_EVT_GATTS_WRITE_CMD_REQ\r\n"); + break; + + default: + break; + } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/mdk/startup_psoc6_01_cm0plus.s b/2020TPCApp0.cydsn/mdk/startup_psoc6_01_cm0plus.s new file mode 100644 index 0000000..9358665 --- /dev/null +++ b/2020TPCApp0.cydsn/mdk/startup_psoc6_01_cm0plus.s @@ -0,0 +1,321 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT NvicMux8_IRQHandler [WEAK] + EXPORT NvicMux9_IRQHandler [WEAK] + EXPORT NvicMux10_IRQHandler [WEAK] + EXPORT NvicMux11_IRQHandler [WEAK] + EXPORT NvicMux12_IRQHandler [WEAK] + EXPORT NvicMux13_IRQHandler [WEAK] + EXPORT NvicMux14_IRQHandler [WEAK] + EXPORT NvicMux15_IRQHandler [WEAK] + EXPORT NvicMux16_IRQHandler [WEAK] + EXPORT NvicMux17_IRQHandler [WEAK] + EXPORT NvicMux18_IRQHandler [WEAK] + EXPORT NvicMux19_IRQHandler [WEAK] + EXPORT NvicMux20_IRQHandler [WEAK] + EXPORT NvicMux21_IRQHandler [WEAK] + EXPORT NvicMux22_IRQHandler [WEAK] + EXPORT NvicMux23_IRQHandler [WEAK] + EXPORT NvicMux24_IRQHandler [WEAK] + EXPORT NvicMux25_IRQHandler [WEAK] + EXPORT NvicMux26_IRQHandler [WEAK] + EXPORT NvicMux27_IRQHandler [WEAK] + EXPORT NvicMux28_IRQHandler [WEAK] + EXPORT NvicMux29_IRQHandler [WEAK] + EXPORT NvicMux30_IRQHandler [WEAK] + EXPORT NvicMux31_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +NvicMux8_IRQHandler +NvicMux9_IRQHandler +NvicMux10_IRQHandler +NvicMux11_IRQHandler +NvicMux12_IRQHandler +NvicMux13_IRQHandler +NvicMux14_IRQHandler +NvicMux15_IRQHandler +NvicMux16_IRQHandler +NvicMux17_IRQHandler +NvicMux18_IRQHandler +NvicMux19_IRQHandler +NvicMux20_IRQHandler +NvicMux21_IRQHandler +NvicMux22_IRQHandler +NvicMux23_IRQHandler +NvicMux24_IRQHandler +NvicMux25_IRQHandler +NvicMux26_IRQHandler +NvicMux27_IRQHandler +NvicMux28_IRQHandler +NvicMux29_IRQHandler +NvicMux30_IRQHandler +NvicMux31_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, =Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, =(Heap_Mem + Heap_Size) + LDR R3, =Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END + + +; [] END OF FILE diff --git a/2020TPCApp0.cydsn/mdk/startup_psoc6_01_cm4.s b/2020TPCApp0.cydsn/mdk/startup_psoc6_01_cm4.s new file mode 100644 index 0000000..c41752b --- /dev/null +++ b/2020TPCApp0.cydsn/mdk/startup_psoc6_01_cm4.s @@ -0,0 +1,696 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Power Mode Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END + + +; [] END OF FILE diff --git a/2020TPCApp0.cydsn/post_build_core1.bat b/2020TPCApp0.cydsn/post_build_core1.bat new file mode 100644 index 0000000..2be69b0 --- /dev/null +++ b/2020TPCApp0.cydsn/post_build_core1.bat @@ -0,0 +1,42 @@ +@rem Usage: +@rem Call post_build_core1.bat +@rem E.g. in PSoC Creator 4.2: +@rem post_build_core1.bat creator ${OutputDir} ${ProjectShortName} + +@echo ------------------------------------------ +@echo Post-build commands for Cortex-M4 core +@echo ------------------------------------------ + +@rem Set proper path to your PDL 3.x and above installation +@set PDL_PATH="C:\Program Files (x86)\Cypress\PDL\3.1.7" + +@set CY_MCU_ELF_TOOL=%PDL_PATH%"\tools\win\elf\cymcuelftool.exe" + +@set IDE=%1 + +@if "%IDE%" == "creator" ( + @set OUTPUT_DIR=%2 + @set PRJ_NAME=%3 + @set ELF_EXT=.elf +) + +@if "%IDE%" == "uvision" ( + @set OUTPUT_DIR=%2 + @set PRJ_NAME=%3 + @set ELF_EXT=.axf +) + +@if "%IDE%" == "iar" ( + @set OUTPUT_DIR=%2 + @set PRJ_NAME=%3 + @set ELF_EXT=.out +) + +@if "%IDE%" == "eclipse" ( + @set OUTPUT_DIR=%2 + @set PRJ_NAME=%3 + @set ELF_EXT= +) + +@rem Sign the application with the RSA private key +%CY_MCU_ELF_TOOL% -S %OUTPUT_DIR%\%PRJ_NAME%%ELF_EXT% SHA256 --encrypt RSASSA-PKCS --key ..\Keys\rsa_private.txt --output %OUTPUT_DIR%\%PRJ_NAME%_RSA%ELF_EXT% --hex %OUTPUT_DIR%\%PRJ_NAME%.hex diff --git a/2020TPCApp0.cydsn/rsa_to_c.py b/2020TPCApp0.cydsn/rsa_to_c.py new file mode 100644 index 0000000..455666d --- /dev/null +++ b/2020TPCApp0.cydsn/rsa_to_c.py @@ -0,0 +1,254 @@ +#!/usr/bin/env python3 +""" This script may be used to generate RSA public key modulus, exponent, and + additional coefficients. Additional coefficients are optional and are used + only to increase RSA calculation performance up to 4 times. + + The format of output may be defined by command line arguments and is either + the raw HEX data, or the array. + + Copyright (C) 2017-2018, Cypress Semiconductor Corporation. All rights reserved. + + You may use this file only in accordance with the license, terms, conditions, + disclaimers, and limitations in the end user license agreement accompanying + the software package with which this file was provided. +""" + +import sys, subprocess, os + +if sys.version_info < (3,): + integer_types = (int, long,) + ## Used in convert_hexstr_to_list +else: + integer_types = (int,) + +def main(): + """ Main function + + Build the strings to print out the public key modulus and exponent. + """ + if len(sys.argv) < 2: + print("Usage: %s [-norev] [-out ]" % sys.argv[0]) + return 1 + isReverse = True + out_file_name = '' + for idx in range(len(sys.argv)): + if "-norev" == sys.argv[idx]: + isReverse = False + if "-out" == sys.argv[idx]: + out_file_name = sys.argv[idx+1] + + modulus_list = [] # list to collect bytes of modulus + rsaExp = "" # string that will contain the parsed RSA exponent + key_len = 0 # containt the length in bits of an RSA modulus + + try: + # build openssl command line + cmd_line = ['openssl', 'rsa', '-text', '-pubin', '-in', + sys.argv[1], + '-noout'] + output, error = subprocess.Popen( + cmd_line, universal_newlines=True, + stdout=subprocess.PIPE, stderr=subprocess.PIPE).communicate() + + # check for errors (warnings ignored) + lines = error.split("\n") + error_lines = [] + for line in lines: + if (len(line) != 0) and (("WARNING:" in line) == False): + error_lines.append(line) + if len(error_lines) != 0: + print ("OpenSSL call failed" + "\n" + " ".join(cmd_line) + "\n" + str(error_lines) ) + return 1 + + modulus_found = False + for line in output.split("\n"): + if "Public-Key" in line: + # get length of RSA modulus + key_len = int(line.split(" ")[1].replace("(", '')) + if "Modulus" in line: + # modulus record is found + modulus_found = True; continue + if "Exponent" in line: + modulus_found = False + # Exponent record is found + rsaExp = line.split(" ")[2][1:-1] + if modulus_found: + # Collect bytes of modulus to list + modulus_list = modulus_list + line.strip().split(":") + except subprocess.CalledProcessError as err: + print ("OpenSSL call failed with errorcode=" + str(err.returncode) \ + + "\n" + str(err.cmd) + "\n" + str(err.output)) + return 1 + + #normalize data + # remove empty strings from modulus_list + modulus_list = [i for i in modulus_list if i] + if (len(modulus_list) == key_len // 8 + 1) and (int(modulus_list[0]) == 0): + # remove first zero byte + modulus_list.pop(0) + + # Check parsed data + if not key_len: + print ("Key length was not gotten by parsing." ) + return 1 + if len(modulus_list) != (key_len // 8): + print ("Length of parsed Modulus (%s) is not equal to Key length (%s)." % (key_len, len(modulus_list) * 8)) + return 1 + + modulus_hex_str = "".join(modulus_list) + (barret, inv_modulo, r_bar) = calculate_additional_rsa_key_coefs(modulus_hex_str) + + barret_list = convert_hexstr_to_list(barret, isReverse) + # add three zero bytes + barret_list = ([0]*3 + barret_list) if not isReverse else (barret_list + [0]*3) + + barret_str = build_returned_string(barret_list) + barret_str = ".barrettData =\n{\n%s\n}," % barret_str + + inv_modulo_list = convert_hexstr_to_list(inv_modulo, isReverse) + inv_modulo_str = build_returned_string(inv_modulo_list) + inv_modulo_str = ".inverseModuloData =\n{\n%s\n}," % inv_modulo_str + + r_bar_list = convert_hexstr_to_list(r_bar, isReverse) + r_bar_str = build_returned_string(r_bar_list) + r_bar_str = ".rBarData =\n{\n%s\n}," % r_bar_str + + rsaExp_list = convert_hexstr_to_list(rsaExp, isReverse) + rsaExp_list_len = len(rsaExp_list) + if rsaExp_list_len % 4 != 0: + rsaExp_list = ([0]*(4-(rsaExp_list_len % 4)) + rsaExp_list) if not isReverse \ + else (rsaExp_list + [0]*(4-(rsaExp_list_len % 4))) + + rsaExp_str = build_returned_string(rsaExp_list) + rsaExp_str = ".expData =\n{\n%s\n}," % rsaExp_str + + # Check and apply isReverse flag + if isReverse: + modulus_list.reverse() + modulus_str = build_returned_string(modulus_list) + modulus_str = ".moduloData =\n{\n%s\n}," % modulus_str + + if not out_file_name: + print(modulus_str) + print(rsaExp_str) + print(barret_str) + print(inv_modulo_str) + print(r_bar_str) + else: + with open(out_file_name, 'w') as outfile: + outfile.write(modulus_str + "\n") + outfile.write(rsaExp_str + "\n") + outfile.write(barret_str + "\n") + outfile.write(inv_modulo_str + "\n") + outfile.write(r_bar_str + "\n") + return 0 + + +def extended_euclid(modulo): + ''' Calculate greatest common divisor (GCD) of two values. + Link: https://en.wikipedia.org/wiki/Extended_Euclidean_algorithm + formula to calculate: ax + by - gcd(a,b) + parameters: + a, b - two values witch is calculated GCD for. + return: + absolute values of x and y coefficients + + NOTE: pseudo-code of operation: + x, lastX = 0, 1 + y, lastY = 1, 0 + while (b != 0): + q = a // b + a, b = b, a % b + x, lastX = lastX - q * x, x + y, lastY = lastY - q * y, y + return (abs(lastX), abs(lastY)) + ''' + + rInv = 1; + nInv = 0; + modulo_bit_size = modulo.bit_length() + + for i in range(modulo_bit_size): + if not (rInv % 2): + rInv = rInv // 2 + nInv = nInv // 2 + else: + rInv = rInv + modulo; + rInv = rInv // 2; + nInv = nInv // 2; + nInv = nInv + (1 << (modulo_bit_size - 1)); + return rInv, nInv + + +def calculate_additional_rsa_key_coefs(modulo): + ''' Calculate three additional coefficients for modulo value of RSA key + 1. barret_coef - Barrett coefficient. Equation is: barretCoef = floor((2 << (2 * k)) / n); + Main article is here: https://en.wikipedia.org/wiki/Barrett_reduction + 2. r_bar - pre-calculated value. Equation is: r_bar = (1 << k) mod n; + 3. inverse_modulo - coefficient. It satisfying rr' - nn' = 1, where r = 1 << k; + Main article is here: https://en.wikipedia.org/wiki/Extended_Euclidean_algorithm + parameter: + modulo - part of RSA key + return: + tuple( barret_coef, r_bar, inverse_modulo ) as reversed byte arrays; + ''' + if isinstance(modulo, str): + modulo = int(modulo, 16) + if modulo <= 0: + raise ValueError("Modulus must be positive") + if modulo & (modulo - 1) == 0: + raise ValueError("Modulus must not be a power of 2") + + modulo_len = modulo.bit_length() + barret_coef = (1 << (modulo_len * 2)) // modulo + r_bar = (1 << modulo_len) % modulo + inverse_modulo = extended_euclid(modulo) + ret_arrays = ( + barret_coef, + inverse_modulo[1], + r_bar + ) + + return ret_arrays + + +def convert_hexstr_to_list(s, reversed=False): + ''' Converts a string likes '0001aaff...' to list [0, 1, 170, 255]. + Also an input parameter can be an integer, in this case it will be + converted to a hex string. + parameter: + s - string to convert + reversed - a returned list have to be reversed + return: + a list of an integer values + ''' + if isinstance(s, integer_types): + s = hex(s) + s = s[2 if s.lower().startswith("0x") else 0 : -1 if s.upper().endswith("L") else len(s)] + if len(s) % 2 != 0: + s = '0' + s + l = [int("0x%s" % s[i:i+2], 16) for i in range(0, len(s), 2)] + if reversed: + l.reverse() + return l + +def build_returned_string(inp_list): + ''' Converts a list to a C-style array of hexadecimal numbers string + ''' + if isinstance(inp_list[0], int): + inp_list = ['%02X' % x for x in inp_list] + + tmp_str = " " + for idx in range(0, len(inp_list)): + if (idx % 8 == 0) and (idx != 0): + tmp_str = tmp_str + "\n " + tmp_str = tmp_str + ( "0x%02Xu," % int(inp_list[idx], base=16) ) + if (idx % 8 != 7) and (idx != len(inp_list) - 1): + tmp_str = tmp_str + " " + + return tmp_str + + +if __name__ == "__main__": + main() + diff --git a/2020TPCApp0.cydsn/system_psoc6.h b/2020TPCApp0.cydsn/system_psoc6.h new file mode 100644 index 0000000..73d1263 --- /dev/null +++ b/2020TPCApp0.cydsn/system_psoc6.h @@ -0,0 +1,648 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.20 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is _IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#define CY_CORTEX_M4_APPL_ADDR ( CY_FLASH_BASE + CY_FLASH_SIZE / 2U) /* <<< Half of flash is reserved for the Cortex-M0+ application */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +#if defined(__ARMCC_VERSION) + extern void SystemInit(void) __attribute__((constructor)); +#else + extern void SystemInit(void); +#endif /* (__ARMCC_VERSION) */ + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/system_psoc6_cm0plus.c b/2020TPCApp0.cydsn/system_psoc6_cm0plus.c new file mode 100644 index 0000000..038e7b4 --- /dev/null +++ b/2020TPCApp0.cydsn/system_psoc6_cm0plus.c @@ -0,0 +1,699 @@ +/***************************************************************************//** +* \file system_psoc6_cm0plus.c +* \version 2.20 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) +#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) + if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) + { + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + IPC_STRUCT7->DATA = 0UL; + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + IPC_STRUCT7->RELEASE = 0UL; + } +#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t slowClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Slow Clock Divider */ + slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + pathFreqHz = pathFreqHz / periClkDiv; + cy_PeriClkFreqHz = pathFreqHz; + pathFreqHz = pathFreqHz / slowClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Returns the Cortex-M4 core power mode. +* +* \return \ref group_system_config_cm4_status_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t regValue; + + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; + + return (regValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; + + CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); + + interruptState = Cy_SysLib_EnterCriticalSection(); + + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) + { + Cy_SysResetCM4(); + } + + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core and waits for the mode to take the effect. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm0 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm0(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/system_psoc6_cm4.c b/2020TPCApp0.cydsn/system_psoc6_cm4.c new file mode 100644 index 0000000..c4d8c11 --- /dev/null +++ b/2020TPCApp0.cydsn/system_psoc6_cm4.c @@ -0,0 +1,542 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.20 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} + +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/transport_ble.c b/2020TPCApp0.cydsn/transport_ble.c new file mode 100644 index 0000000..37e76b7 --- /dev/null +++ b/2020TPCApp0.cydsn/transport_ble.c @@ -0,0 +1,328 @@ +/***************************************************************************//** +* \file transport_ble.c +* \version 3.0 +* +* This file provides the source code of the DFU communication APIs +* for the BLE Component. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "transport_ble.h" + +#if defined(CY_PSOC_CREATOR_USED) +#include "BLE.h" +#else +#include "cy_flash.h" +#include "ble/cy_ble_gap.h" +#include "ble/cy_ble_stack.h" +#endif /* defined(CY_PSOC_CREATOR_USED) */ + +#include "ble/cy_ble_stack_host_error.h" +#include "ble/cy_ble_event_handler.h" +#include "ble/cy_ble_bts.h" + +#if CY_BLE_HOST_CORE + +static uint16_t cyBle_btsDataPacketIndex = 0u; +static uint8_t cyBle_cmdReceivedFlag = 0u; +static uint16_t cyBle_cmdLength = 0u; +static uint8_t *cyBle_btsBuffPtr; + +static uint16_t cyBle_btsDataPacketSize = 0u; +static uint8_t cyBle_btsDataBuffer[CY_FLASH_SIZEOF_ROW + CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM]; + +/* Connection Handle */ +cy_stc_ble_conn_handle_t appConnHandle; + +/******************************************************************************* +* Function Name: CyBLE_CyBtldrCommStart +****************************************************************************//** +* +* Initializes DFU state for BLE communication. +* +*******************************************************************************/ +void CyBLE_CyBtldrCommStart(void) +{ +#if defined(CY_PSOC_CREATOR_USED) + /* Start BLE and register the callback function */ + (void)Cy_BLE_Start(&AppCallBack); + /* Registers a callback function for DFU */ + (void)Cy_BLE_BTS_RegisterAttrCallback(&DFUCallBack); +#endif /* defined(CY_PSOC_CREATOR_USED) */ + cyBle_btsDataPacketIndex = 0u; +} + + +/******************************************************************************* +* Function Name: CyBLE_CyBtldrCommStop +****************************************************************************//** +* +* Disconnects from the peer device and stops BLE component. +* +******************************************************************************/ +void CyBLE_CyBtldrCommStop(void) +{ + cy_stc_ble_gap_disconnect_info_t disconnectInfoParam = + { + .bdHandle = appConnHandle.bdHandle, + .reason = CY_BLE_HCI_ERROR_OTHER_END_TERMINATED_USER + }; + + /* Initiate disconnection from the peer device*/ + if(Cy_BLE_GAP_Disconnect(&disconnectInfoParam) == CY_BLE_SUCCESS) + { + /* Wait for disconnection event */ + while(Cy_BLE_GetConnectionState(appConnHandle) == CY_BLE_CONN_STATE_CONNECTED) + { + /* Process BLE events */ + Cy_BLE_ProcessEvents(); + } + } + /* Stop BLE component. Ignores an error code because current function returns nothing */ + (void) Cy_BLE_Disable(); +} + + +/******************************************************************************* +* Function Name: CyBtldrCommReset +****************************************************************************//** +* +* Resets DFU state for BLE communication. +* +*******************************************************************************/ +void CyBLE_CyBtldrCommReset(void) +{ + cyBle_btsDataPacketIndex = 0u; +} + +/******************************************************************************* +* Function Name: CyBLE_CyBtldrCommWrite +****************************************************************************//** +* +* Requests that the provided size (number of bytes) should be written from the +* input data buffer to the host device. This function in turn invokes the +* CyBle_GattsNotification() API to sent the data. If a notification is +* accepted, the function returns CYRET_SUCCESS. The timeOut parameter is ignored +* in this case. +* +* \param data The pointer to the buffer containing data to be written. +* \param size The number of bytes from the data buffer to write. +* \param count The pointer to where the BLE component will write the number +* of written bytes, generally the same as the size. +* \param timeOut Ignored. Used for consistency. +* +* \return +* The return value is of type \ref cy_en_dfu_status_t: +* - CY_DFU_SUCCESS - Indicates if a notification is successful. +* - CY_DFU_ERROR_UNKNOWN - Failed to send notification to the host. +* +*******************************************************************************/ +cy_en_dfu_status_t CyBLE_CyBtldrCommWrite(const uint8_t pData[], uint32_t size, uint32_t *count, uint32_t timeout) +{ + cy_en_dfu_status_t status = CY_DFU_ERROR_UNKNOWN; + + if (timeout == 0u) + { + /* empty */ + } + + if(Cy_BLE_BTSS_SendNotification(appConnHandle, CY_BLE_BTS_BT_SERVICE, size, (const uint8 *)pData) == CY_BLE_SUCCESS) + { + *count = size; + status = CY_DFU_SUCCESS; + } + else + { + *count = 0u; + } + return (status); +} + +/******************************************************************************* +* Function Name: CyBLE_CyBtldrCommRead +****************************************************************************//** +* +* Requests that the provided size (number of bytes) is read from the host device +* and stored in the provided data buffer. Once the read is done, the "count" is +* endorsed with the number of bytes written. The timeOut parameter is used to +* provide an upper bound on the time that the function is allowed to operate. If +* the read completes early, it should return success code as soon as possible. +* If the read was not successful before the allocated time has expired, it +* should return an error. +* +* \param data The pointer to the buffer to store data from the host controller. +* \param size The number of bytes to read into the data buffer. +* \param count The pointer to where the BLE component will write the number of +* read bytes. +* \param timeout The amount of time (in milliseconds) for which the +* BLE component should wait before indicating communication +* time out. +* +* \return +* The return value is of type \ref cy_en_dfu_status_t: +* - CY_DFU_SUCCESS - A command was successfully read. +* - CY_DFU_ERROR_DATA - The size of the command exceeds the buffer. +* - CY_DFU_ERROR_TIMEOUT - The host controller did not respond during + specified time out. +* \sideeffect +* \ref CyBle_ProcessEvents() is called as a part of this function. +* +*******************************************************************************/ +cy_en_dfu_status_t CyBLE_CyBtldrCommRead(uint8_t pData[], uint32_t size, uint32_t *count, uint32_t timeout) +{ + cy_en_dfu_status_t status = CY_DFU_ERROR_UNKNOWN; + + if ((pData != NULL) && (size > 0u)) + { + status = CY_DFU_ERROR_TIMEOUT; + + while(timeout != 0u) + { + /* Process BLE events */ + Cy_BLE_ProcessEvents(); + + if(cyBle_cmdReceivedFlag == 1u) + { + /* Clear command receive flag */ + cyBle_cmdReceivedFlag = 0u; + + if(cyBle_cmdLength < size) + { + (void) memcpy((void *) pData, (const void *) cyBle_btsBuffPtr, (uint32_t)cyBle_cmdLength); + + /* Return actual received command length */ + *count = cyBle_cmdLength; + + status = CY_DFU_SUCCESS; + } + else + { + pData = NULL; + *count = 0u; + status = CY_DFU_ERROR_DATA; + } + break; + } + /* Wait 1 ms and update timeout counter */ + Cy_SysLib_Delay(1u); + --timeout; + } + + /* Process BLE events */ + Cy_BLE_ProcessEvents(); + } + return (status); +} + +/******************************************************************************* +* Function Name: DFUCallBack +****************************************************************************//** +* +* Handles the events from the BLE stack for the DFU Service. +* +* \param eventCode Event code +* \param eventParam Event parameters +* +*******************************************************************************/ +void DFUCallBack(uint32 event, void* eventParam) +{ + /* To remove incorrect compiler warning */ + (void)eventParam; + + switch ((cy_en_ble_evt_t)event) + { + case CY_BLE_EVT_BTSS_NOTIFICATION_ENABLED: + break; + + case CY_BLE_EVT_BTSS_NOTIFICATION_DISABLED: + break; + + case CY_BLE_EVT_BTSS_EXEC_WRITE_REQ: + /* Check the execWriteFlag before execute or cancel write long operation */ + if(((cy_stc_ble_gatts_exec_write_req_t *)eventParam)->execWriteFlag == CY_BLE_GATT_EXECUTE_WRITE_EXEC_FLAG) + { + cyBle_btsBuffPtr = ((cy_stc_ble_gatts_exec_write_req_t *)eventParam)->baseAddr[0u].handleValuePair.value.val; + + /* Extract length of command data and add control bytes to data + * length to get command length. + */ + cyBle_cmdLength = (((uint16)(((uint16) cyBle_btsBuffPtr[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET + 1u]) << 8u)) | + (uint16) cyBle_btsBuffPtr[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET]) + + CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM; + + if(cyBle_cmdLength > CYBLE_BTS_COMMAND_MAX_LENGTH) + { + cyBle_cmdLength = CYBLE_BTS_COMMAND_MAX_LENGTH; + } + + /* Set flag for DFU to know that command is received from host */ + cyBle_cmdReceivedFlag = 1u; + } + break; + + case CY_BLE_EVT_BTSS_PREP_WRITE_REQ: + if(((cy_stc_ble_gatts_prep_write_req_param_t *)eventParam)->currentPrepWriteReqCount == 1u) + { + /* Send Prepare Write Response which identifies acknowledgement for + * long characteristic value write. + */ + cyBle_cmdLength = 0u; + } + break; + + case CY_BLE_EVT_BTSS_WRITE_CMD_REQ: + { + uint8 *localDataBuffer = ((cy_stc_ble_bts_char_value_t *)eventParam)->value->val; + + /* This is the beginning of the packet, let's read the size now */ + if(cyBle_btsDataPacketIndex == 0u) + { + cyBle_btsDataPacketSize = (((uint16)(((uint16) localDataBuffer[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET + 1u]) << 8u)) | + (uint16) localDataBuffer[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET]) + + CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM; + + } + + (void) memcpy(&cyBle_btsDataBuffer[cyBle_btsDataPacketIndex], localDataBuffer, (uint32_t) ((cy_stc_ble_bts_char_value_t *)eventParam)->value->len); + + cyBle_btsDataPacketIndex += ((cy_stc_ble_bts_char_value_t *)eventParam)->value->len; + + if(cyBle_btsDataPacketIndex == cyBle_btsDataPacketSize) + { + cyBle_btsBuffPtr = &cyBle_btsDataBuffer[0]; + cyBle_cmdLength = cyBle_btsDataPacketSize; + cyBle_cmdReceivedFlag = 1u; + cyBle_btsDataPacketIndex = 0u; + } + break; + } + + case CY_BLE_EVT_BTSS_WRITE_REQ: + cyBle_btsBuffPtr = + CY_BLE_GATT_DB_ATTR_GET_ATTR_GEN_PTR(cy_ble_btsConfigPtr->btss->btServiceInfo[0u].btServiceCharHandle); + + /* Extract length of command data and add control bytes to data + * length to get command length. + */ + cyBle_cmdLength = (((uint16)(((uint16) cyBle_btsBuffPtr[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET + 1u]) << 8u)) | + (uint16) cyBle_btsBuffPtr[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET]) + + CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM; + + /* Set flag for DFU to know that command is received from host */ + cyBle_cmdReceivedFlag = 1u; + break; + + default: + break; + } +} + +#endif /* CY_BLE_HOST_CORE */ + +/* [] END OF FILE */ diff --git a/2020TPCApp0.cydsn/transport_ble.h b/2020TPCApp0.cydsn/transport_ble.h new file mode 100644 index 0000000..d90095c --- /dev/null +++ b/2020TPCApp0.cydsn/transport_ble.h @@ -0,0 +1,55 @@ +/***************************************************************************//** +* \file transport_ble.h +* \version 3.0 +* +* This file provides constants and parameter values of the DFU +* communication APIs for the BLE Component. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(TRANSPORT_BLE_H) +#define TRANSPORT_BLE_H + +#include +#include "cy_dfu.h" +#include "ble/cy_ble.h" + +/*************************************** +* Function Prototypes +***************************************/ + +/* BLE DFU physical layer functions */ +void CyBLE_CyBtldrCommStart(void); +void CyBLE_CyBtldrCommStop (void); +void CyBLE_CyBtldrCommReset(void); +cy_en_dfu_status_t CyBLE_CyBtldrCommRead (uint8_t pData[], uint32_t size, uint32_t *count, uint32_t timeout); +cy_en_dfu_status_t CyBLE_CyBtldrCommWrite(const uint8_t pData[], uint32_t size, uint32_t *count, uint32_t timeout); +void DFUCallBack(uint32 event, void* eventParam); + +/* BLE Callback */ +extern void AppCallBack(uint32 event, void* eventParam); + +/*************************************** +* API Constants +***************************************/ +#define CYBLE_BTS_COMMAND_DATA_LEN_OFFSET (2u) +#define CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM (7u) +#define CYBLE_BTS_COMMAND_MAX_LENGTH (265u) + + +/*************************************** +* Global variables declaration +***************************************/ +extern cy_stc_ble_conn_handle_t appConnHandle; + + +#endif /* !defined(TRANSPORT_BLE_H) */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/2020TPCApp1.cydwr b/2020TPCApp1.cydsn/2020TPCApp1.cydwr new file mode 100644 index 0000000..55984a6 --- /dev/null +++ b/2020TPCApp1.cydsn/2020TPCApp1.cydwr @@ -0,0 +1,1242 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+TaskHandle_t Audio_Task_Handle; + +static const uint8_t START_BYTE = 0x7E; +static const uint8_t VERSION_BYTE = 0xFF; +static const uint8_t END_BYTE = 0xEF; + +// Valid volumes are 0 - 30. +static const uint8_t COMMAND_SPECIFY_VOLUME = 0x06; +static const uint8_t COMMAND_PAUSE = 0x0E; +static const uint8_t COMMAND_PLAY_TRACK_IN_FOLDER = 0x0F; + +__attribute__((always_inline)) inline uint16_t CalculateChecksum(uint8_t * buffer, uint8_t length) +{ + uint16_t checksum = 0; + + for (uint_fast8_t i = 0; i < length; i++) + { + checksum += buffer[i]; + } + + return (0 - checksum); +} + +static void Send_Command(uint8_t command, bool requireFeedback, uint16_t parameter) +{ + uint8_t buffer[10]; + uint16_t checksum; + + buffer[0] = START_BYTE; + buffer[1] = VERSION_BYTE; + buffer[2] = 6; // count + buffer[3] = command; + buffer[4] = requireFeedback; + buffer[5] = (uint8_t)(parameter >> 8); + buffer[6] = (uint8_t)(parameter); + + checksum = CalculateChecksum(&buffer[1], 6); + + buffer[7] = (uint8_t)(checksum >> 8); + buffer[8] = (uint8_t)(checksum); + buffer[9] = END_BYTE; + + for (uint_fast8_t i = 0; i < 10; i++) + { + UART_Audio_Put(buffer[i]); + } +} + +SystemKResult_T Perform_Audio_Action(AudioAction_T * action) +{ + if (xQueueSend(xQueueAudio, action, 0) == pdTRUE) + { + return SYSTEMK_RESULT_SUCCESS; + } + else + { + return SYSTEMK_RESULT_QUEUE_IS_FULL; + } +} + +void Init_Audio(void) +{ + UART_Audio_Start(); + + xQueueAudio = xQueueCreate(5, sizeof(AudioAction_T)); +} + +void Audio_Task(void * pvParameters) +{ + portBASE_TYPE xStatus; + + while (IsNVMInitialized() == false) + { + vTaskDelay(100 / portTICK_PERIOD_MS); + } + Send_Command(COMMAND_SPECIFY_VOLUME, false, NVM_VOLUME); + + while (true) + { + AudioAction_T action; + + xStatus = xQueueReceive(xQueueAudio, &action, 0); + + if (xStatus == pdPASS) + { + switch (action.ID) + { + case AUDIO_SET_VOLUME: + { + uint8_t volume = *((uint8_t *)action.Data); + if (volume <= 30) + { + Send_Command(COMMAND_SPECIFY_VOLUME, false, volume); + } + } + break; + + case AUDIO_SILENCE: + Send_Command(COMMAND_PAUSE, false, 0x0000); + break; + + case AUDIO_PLAY_STARTUP_SOUND: + // Play track "001" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0101); + break; + + case AUDIO_PLAY_SHOT_FIRED: + // Play track "002" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0102); + break; + + case AUDIO_PLAY_TAG_RECEIVED: + // Play track "003" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0103); + break; + + case AUDIO_PLAY_TAGGED_OUT: + // Play track "004" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0104); + break; + + case AUDIO_PLAY_MISFIRE: + // Play track "005" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0105); + break; + + case AUDIO_PRONOUNCE_NUMBER_0_TO_100: + { + uint8_t file_index = *((uint8_t *)action.Data); + if (file_index > 100) + { + file_index = 100; + } + else if (file_index == 0) + { + file_index = 101; + } + // The numbers are stored in folder "10". + // 001.mp3 is "one", 100.mp3 is "one hundred", and 101.mp3 is "zero". + uint16_t filenumber = 0x0A00 + file_index; + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, filenumber); + } + break; + + case AUDIO_PLAY_MENU_PROMPT: + // Play track "006" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0106); + break; + + case AUDIO_PLAY_SELECTION_INDICATOR: + // Play track "007" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0107); + break; + + case AUDIO_PLAY_HEALTH_REMAINING: + // Play track "008" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0108); + break; + + case AUDIO_PLAY_ELECTRONIC_DANCE_MUSIC: + // Play track "009" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0109); + break; + + default: + case AUDIO_PLAY_GENERIC_ERROR: + // Play track "010" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010A); + break; + + case AUDIO_PLAY_VOLUME_PROMPT: + // Play track "011" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010B); + break; + + case AUDIO_PLAY_RIGHT_HANDED: + // Play track "012" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010C); + break; + + case AUDIO_PLAY_LEFT_HANDED: + // Play track "013" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010D); + break; + + case AUDIO_PLAY_GAME_ON: + // Play track "014" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010E); + break; + + case AUDIO_PLAY_HARDWARE_SETTINGS_PROMPT: + // Play track "015" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010F); + break; + + case AUDIO_PLAY_GAME_SETTINGS_PROMPT: + // Play track "016" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0110); + break; + + case AUDIO_PLAY_BONK: + // Play track "017" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0111); + break; + + case AUDIO_PLAY_NEAR_MISS: + // Play track "018" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0112); + break; + + case AUDIO_PLAY_PLAYER_ID_PROMPT: + // Play track "019" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0113); + break; + + case AUDIO_PLAY_TEAM_ID_PROMPT: + // Play track "020" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0114); + break; + + case AUDIO_PLAY_FRIENDLY_FIRE: + // Play track "021" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0115); + break; + + case AUDIO_PLAY_STARTING_THEME: + // Play track "022" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0116); + break; + + case AUDIO_PLAY_BOOP: + // Play track "023" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0117); + break; + + case AUDIO_PLAY_BEEP: + // Play track "024" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0118); + break; + + case AUDIO_PLAY_REPROGRAMMING: + // Play track "025" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0119); + break; + + case AUDIO_PLAY_BOMB: + // Play track "026" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x011A); + break; + + case AUDIO_PLAY_GAME_OVER: + // Play track "027" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x011B); + break; + } + + if (action.Play_To_Completion == true) + { + do + { + vTaskDelay(100 / portTICK_PERIOD_MS); + } while (Is_Audio_Playing() == true); + + KEvent_T command_received_event = {.ID = KEVENT_AUDIO_COMPLETED, .Data = (void *)action.ID}; + Post_KEvent(&command_received_event); + } + } + + vTaskDelay(100 / portTICK_PERIOD_MS); + } +} + +bool Is_Audio_Playing() +{ + bool result = false; + + // The signal is active low. + if (Cy_GPIO_Read(Pin_Audio_Busy_PORT, Pin_Audio_Busy_NUM) == 0) + { + result = true; + } + + return result; +} diff --git a/2020TPCApp1.cydsn/Audio.h b/2020TPCApp1.cydsn/Audio.h new file mode 100644 index 0000000..d2dda0c --- /dev/null +++ b/2020TPCApp1.cydsn/Audio.h @@ -0,0 +1,7 @@ + +extern QueueHandle_t xQueueAudio; +extern TaskHandle_t Audio_Task_Handle; + +void Init_Audio(void); +void Audio_Task(void * pvParameters); +bool Is_Audio_Playing(); diff --git a/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE.c b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE.c new file mode 100644 index 0000000..0636c1d --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE.c @@ -0,0 +1,1013 @@ +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +#define BLE_TASK_PERIOD_IN_ms 10 + +#ifdef TRACE_BLE + #define TRACE_BLE_STATE_ENTRY(state_name) do {if (State_Changed == true) { COMM_Console_Print_String("[BLE] Entering the ");COMM_Console_Print_String(state_name);COMM_Console_Print_String(" state.\n");}} while (false) +#else // TRACE_BLE + #define TRACE_BLE_STATE_ENTRY(state_name) +#endif // TRACE_BLE + +/* Public Variables */ + +/* Variable used to maintain connection information */ +cy_stc_ble_conn_handle_t appConnHandle[CY_BLE_CONN_COUNT]; + +QueueHandle_t COMM_BLE_CommandQueue; + +TaskHandle_t COMM_BLE_Task_Handle; + +/* Private Variables */ + +static const TickType_t BLE_Task_Delay = BLE_TASK_PERIOD_IN_ms / portTICK_PERIOD_MS; +static COMM_BLE_StateID_T Current_State = COMM_BLE_DEFAULT; +static COMM_BLE_StateID_T Next_State = COMM_BLE_INITIALIZING; +static bool State_Changed = false; +static TickType_t Time_At_State_Entry_In_Ticks; + +//! Immediate Alert Service alert level value. +volatile uint8_t COMM_BLE_IASAlertLevel = 0; + +static cy_stc_ble_gapp_disc_data_t Advertising_Data; +static cy_stc_ble_gapp_scan_rsp_data_t Scan_Response_Data; +static cy_stc_ble_gapp_disc_mode_info_t Advertising_Info = {.advData = &Advertising_Data, .scanRspData = &Scan_Response_Data}; + +/* Private Function Prototypes */ +static void BLE_EventHandler(uint32_t event, void * eventParam); +static void IASEventHandler(uint32 event, void * eventParam); +static cy_en_ble_api_result_t StartNextAdvertisement(); + +/* Inline Functions */ +static inline uint32_t COMM_BLE_GetTimeInState_in_ms() +{ + uint32_t result = (xTaskGetTickCount() - Time_At_State_Entry_In_Ticks) * portTICK_PERIOD_MS; + return result; +} + +/* Public Functions */ + +//! Initializes the Bluetooth Low Energy communications. +void COMM_BLE_Init(void) +{ + COMM_BLE_CommandQueue = xQueueCreate(10, sizeof(COMM_BLE_Command_T)); + + BLE_InitPacketBuffers(); + + COMM_BLE_UART_Init(); + + if (Cy_BLE_Start(BLE_EventHandler) == CY_BLE_SUCCESS) + { + Cy_BLE_IAS_RegisterAttrCallback(IASEventHandler); + } +#ifdef TRACE_BLE + else + { + COMM_Console_Print_String("[BLE] Cy_BLE_Start API Error!\n"); + } +#endif // TRACE_BLE +} + +//! Bluetooth Low Energy communications task: Manages BLE communications, using the PSoC API functions. +/*! + * + */ +void COMM_BLE_Task(void * pvParameters) +{ + COMM_BLE_Command_T command; + + while(true) + { + Cy_BLE_ProcessEvents(); + + if (xQueueReceive(COMM_BLE_CommandQueue, &command, BLE_Task_Delay) == pdPASS) + { + if (Next_State != Current_State) + { + Current_State = Next_State; + Time_At_State_Entry_In_Ticks = xTaskGetTickCount(); + State_Changed = true; + } + else + { + State_Changed = false; + } + + switch (Current_State) + { + default: + case COMM_BLE_DEFAULT: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_DEFAULT"); + COMM_BLE_RequestState(COMM_BLE_INITIALIZING); + } + break; + + case COMM_BLE_INITIALIZING: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_INITIALIZING"); + // Wait for the CY_BLE_EVT_STACK_ON event in BLE_EventHandler() to transition to COMM_BLE_IDLE. + } + break; + + case COMM_BLE_IDLE: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_IDLE"); + + switch (command.ID) + { + case COMM_BLE_SCAN_FOR_KTAG_PACKETS: + COMM_BLE_RequestState(COMM_BLE_SCANNING_FOR_KTAG_PACKETS); + break; + + case COMM_BLE_SCAN_AND_ADVERTISE: + COMM_BLE_RequestState(COMM_BLE_SCANNING_AND_ADVERTISING); + break; + + default: + // All other commands are ignored in this state. + break; + } + } + break; + + case COMM_BLE_SCANNING_FOR_KTAG_PACKETS: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_SCANNING_FOR_KTAG_PACKETS"); + + if (State_Changed == true) + { + // Handle state entry events. + cy_en_ble_api_result_t apiResult = + Cy_BLE_GAPC_StartScan(CY_BLE_SCANNING_FAST, CY_BLE_OBSERVER_CONFIGURATION_0_INDEX); + + if(apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPC_StartScan API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + + switch (command.ID) + { + case COMM_BLE_ADVERTISE_AS_BROADCASTER: + COMM_BLE_RequestState(COMM_BLE_ADVERTISING_AS_BROADCASTER); + break; + + case COMM_BLE_SCAN_AND_ADVERTISE: + COMM_BLE_RequestState(COMM_BLE_SCANNING_AND_ADVERTISING); + break; + + default: + // All other commands are ignored in this state. + break; + } + } + break; + + case COMM_BLE_ADVERTISING_AS_BROADCASTER: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_ADVERTISING_AS_BROADCASTER"); + + if (State_Changed == true) + { + // Handle state entry events. + cy_en_ble_api_result_t apiResult = + Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_BROADCASTER_CONFIGURATION_0_INDEX); + + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + + switch (command.ID) + { + case COMM_BLE_STOP_ADVERTISING: + { + cy_en_ble_api_result_t apiResult = Cy_BLE_GAPP_StopAdvertisement(); + + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StopAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + COMM_BLE_RequestState(COMM_BLE_SCANNING_FOR_KTAG_PACKETS); + } + break; + + case COMM_BLE_SCAN_AND_ADVERTISE: + COMM_BLE_RequestState(COMM_BLE_SCANNING_AND_ADVERTISING); + break; + + default: + // All other commands are ignored in this state. + break; + } + } + break; + + case COMM_BLE_ADVERTISING_AS_PERIPHERAL: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_ADVERTISING_AS_PERIPHERAL"); + + if (State_Changed == true) + { + // Handle state entry events. + cy_en_ble_api_result_t apiResult = + Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX); + + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + } + break; + + case COMM_BLE_SCANNING_AND_ADVERTISING: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_SCANNING_AND_ADVERTISING"); + + if (State_Changed == true) + { + // Handle state entry events. + cy_en_ble_api_result_t apiResult = + Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_BROADCASTER_CONFIGURATION_0_INDEX); + + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + + apiResult = + Cy_BLE_GAPC_StartScan(CY_BLE_SCANNING_FAST, CY_BLE_OBSERVER_CONFIGURATION_0_INDEX); + + if(apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPC_StartScan API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + } + break; + } + COMM_BLE_UART_MaybeSendData(); + +#ifdef CY_DFU_SDK_VERSION_MAJOR + if (COMM_BLE_IASAlertLevel != 0u) + { + // Disconnect from all the connected devices. + for (uint_fast8_t i = 0; i < CY_BLE_CONN_COUNT; i++) + { + if (Cy_BLE_GetConnectionState(appConnHandle[i]) == CY_BLE_CONN_STATE_CONNECTED) + { + cy_stc_ble_gap_disconnect_info_t disconnectInfoParam = + { + .bdHandle = appConnHandle[i].bdHandle, + .reason = CY_BLE_HCI_ERROR_OTHER_END_TERMINATED_USER + }; + + /* Initiate disconnection from the peer device*/ + if (Cy_BLE_GAP_Disconnect(&disconnectInfoParam) == CY_BLE_SUCCESS) + { + /* Wait for disconnection event */ + while (Cy_BLE_GetConnectionState(appConnHandle[i]) == CY_BLE_CONN_STATE_CONNECTED) + { + /* Process BLE events */ + Cy_BLE_ProcessEvents(); + } + } + } + } + + /* Stop BLE component. */ + Cy_BLE_Disable(); + Cy_DFU_ExecuteApp(0u); + } +#endif // CY_DFU_SDK_VERSION_MAJOR + } + } +} + +SystemKResult_T BLE_GetMyAddress(uint8_t * BD_ADDR) +{ + BD_ADDR[0] = cy_ble_deviceAddress.bdAddr[0]; + BD_ADDR[1] = cy_ble_deviceAddress.bdAddr[1]; + BD_ADDR[2] = cy_ble_deviceAddress.bdAddr[2]; + BD_ADDR[3] = cy_ble_deviceAddress.bdAddr[3]; + BD_ADDR[4] = cy_ble_deviceAddress.bdAddr[4]; + BD_ADDR[5] = cy_ble_deviceAddress.bdAddr[5]; + return SYSTEMK_RESULT_SUCCESS; +} + +SystemKResult_T BLE_ScanAndAdvertise(void) +{ + COMM_BLE_Command_T command = { .ID = COMM_BLE_SCAN_AND_ADVERTISE, .Data = (void *)0x00 }; + xQueueSend(COMM_BLE_CommandQueue, &command, 0); + + return SYSTEMK_RESULT_SUCCESS; +} + +void COMM_BLE_RequestState(COMM_BLE_StateID_T state) +{ + Next_State = state; + COMM_BLE_Command_T command = {.ID = COMM_BLE_REQUEST_STATE_CHANGE, .Data = (void *)0x00}; + xQueueSend(COMM_BLE_CommandQueue, &command, 0); +} + +SystemKResult_T BLE_SetAdvertisingData(BLE_AdvertisingData_T * data) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + if (data->length > BLE_MAX_ADVERTISING_BYTES) + { + result = SYSTEMK_RESULT_TOO_MANY_DATA; + } + else if (data->length < BLE_KTAG_PACKET_TOTAL_SIZE) + { + result = SYSTEMK_RESULT_TOO_FEW_DATA; + } + else + { + Advertising_Data.advDataLen = BLE_KTAG_PACKET_TOTAL_SIZE; + memcpy(Advertising_Data.advData, data, BLE_KTAG_PACKET_TOTAL_SIZE); + + cy_en_ble_api_result_t result = Cy_BLE_GAPP_UpdateAdvScanData(&Advertising_Info); + + if (result != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_UpdateAdvScanData Error: 0x"); + COMM_Console_Print_UInt32AsHex(result); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + + return result; +} + +/* Private Functions */ + +static void BLE_EventHandler(uint32_t event, void * eventParam) +{ + cy_en_ble_api_result_t apiResult; + + static cy_stc_ble_gap_sec_key_info_t keyInfo = + { + .localKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST | + CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST | + CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST, + .exchangeKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST | + CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST | + CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST | + CY_BLE_GAP_SMP_RESP_ENC_KEY_DIST | + CY_BLE_GAP_SMP_RESP_IRK_KEY_DIST | + CY_BLE_GAP_SMP_RESP_CSRK_KEY_DIST, + }; + + if (COMM_BLE_UART_HandleEvent(event, eventParam) == false) + { + // For more information, refer to the comments in cy_ble_stack.h, where all + // these events are described in more detail. + switch (event) + { + case CY_BLE_EVT_INVALID: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_INVALID\n"); +#endif // TRACE_BLE + break; + + + // G E N E R I C E V E N T S (0x1000 to 0x1FFF) + case CY_BLE_EVT_STACK_ON: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_STACK_ON\n"); +#endif // TRACE_BLE + COMM_BLE_RequestState(COMM_BLE_IDLE); + break; + + case CY_BLE_EVT_TIMEOUT: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_TIMEOUT: 0x"); + COMM_Console_Print_UInt8AsHex(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_STACK_BUSY_STATUS: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_STACK_BUSY_STATUS: 0x"); + COMM_Console_Print_UInt8AsHex(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_MEMORY_REQUEST: + case CY_BLE_EVT_PENDING_FLASH_WRITE: + case CY_BLE_EVT_FLASH_CORRUPT: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); + break; +#endif // TRACE_BLE + break; + + + // H O S T C O N T R O L I N T E R F A C E E V E N T S (0x2000 to 0x2FFF) + case CY_BLE_EVT_HARDWARE_ERROR: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_HARDWARE_ERROR: 0x"); + COMM_Console_Print_UInt8AsHex(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_WRITE_AUTH_PAYLOAD_TO_COMPLETE: + case CY_BLE_EVT_READ_AUTH_PAYLOAD_TO_COMPLETE: + case CY_BLE_EVT_GET_CHANNEL_MAP_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_LE_SET_EVENT_MASK_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_SET_DEVICE_ADDR_COMPLETE\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_LE_PING_AUTH_TIMEOUT: + case CY_BLE_EVT_SET_DATA_LENGTH_COMPLETE: + case CY_BLE_EVT_SET_SUGGESTED_DATA_LENGTH_COMPLETE: + case CY_BLE_EVT_GET_DATA_LENGTH_COMPLETE: + case CY_BLE_EVT_DATA_LENGTH_CHANGE: + case CY_BLE_EVT_GET_PEER_RPA_COMPLETE: + case CY_BLE_EVT_GET_LOCAL_RPA_COMPLETE: + case CY_BLE_EVT_SET_RPA_TO_COMPLETE: + case CY_BLE_EVT_SET_RPA_ENABLE_COMPLETE: + case CY_BLE_EVT_SET_HOST_CHANNEL_COMPLETE: + case CY_BLE_EVT_ADD_DEVICE_TO_RPA_LIST_COMPLETE: + case CY_BLE_EVT_REMOVE_DEVICE_FROM_RPA_LIST_COMPLETE: + case CY_BLE_EVT_ADD_DEVICE_TO_WHITE_LIST_COMPLETE: + case CY_BLE_EVT_REMOVE_DEVICE_FROM_WHITE_LIST_COMPLETE: + case CY_BLE_EVT_GET_PHY_COMPLETE: + case CY_BLE_EVT_SET_DEFAULT_PHY_COMPLETE: + case CY_BLE_EVT_SET_PHY_COMPLETE: + case CY_BLE_EVT_PHY_UPDATE_COMPLETE: + case CY_BLE_EVT_SET_PRIVACY_MODE_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + + // V E N D O R E V E N T S (0x3000 to 0x3FFF) + case CY_BLE_EVT_LL_CNTRL_PROC_PENDING_COMPLETE: + case CY_BLE_EVT_SOFT_RESET_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_SET_DEVICE_ADDR_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_SET_DEVICE_ADDR_COMPLETE\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GET_DEVICE_ADDR_COMPLETE: + case CY_BLE_EVT_GET_RSSI_COMPLETE: + case CY_BLE_EVT_GET_TX_PWR_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_SET_TX_PWR_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_SET_TX_PWR_COMPLETE\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GET_CLK_CONFIG_COMPLETE: + case CY_BLE_EVT_SET_CLK_CONFIG_COMPLETE: + case CY_BLE_EVT_RANDOM_NUM_GEN_COMPLETE: + case CY_BLE_EVT_AES_ENCRYPT_COMPLETE: + case CY_BLE_EVT_AES_CCM_ENCRYPT_COMPLETE: + case CY_BLE_EVT_AES_CCM_DECRYPT_COMPLETE: + case CY_BLE_EVT_SET_SLAVE_LATENCY_MODE_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_STACK_SHUTDOWN_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_STACK_SHUTDOWN_COMPLETE\n"); +#endif // TRACE_BLE + // If desired, wait until console transmit is complete, then call Cy_SysPm_Hibernate(); + break; + + case CY_BLE_EVT_RADIO_TEMPERATURE: + case CY_BLE_EVT_RADIO_VOLTAGE_LEVEL: + case CY_BLE_EVT_AES_CMAC_GEN_COMPLETE: + case CY_BLE_EVT_SET_EVENT_MASK_COMPLETE: + case CY_BLE_EVT_SET_CE_LENGTH_COMPLETE: + case CY_BLE_EVT_SET_CONN_PRIORITY_COMPLETE: + case CY_BLE_EVT_HCI_PKT_RCVD: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + + // G E N E R I C A C C E S S P R O F I L E E V E N T S (0x4000 to 0x4FFF) + case CY_BLE_EVT_GAPC_SCAN_PROGRESS_RESULT: + { +#if (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + COMM_Console_Print_String("[BLE] ..SCAN_PROGRESS_RESULT "); +#endif // (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + + BLE_Packet_T * packet = BLE_DecodeKTagPacket((*(cy_stc_ble_gapc_adv_report_param_t *)eventParam).data, + (*(cy_stc_ble_gapc_adv_report_param_t *)eventParam).dataLen, + (*(cy_stc_ble_gapc_adv_report_param_t *)eventParam).peerBdAddr, + (*(cy_stc_ble_gapc_adv_report_param_t *)eventParam).rssi); + + if (packet != NULL) + { +#ifdef TRACE_BLE + switch (packet->Generic.type) + { + case BLE_PACKET_TYPE_INSTIGATE_GAME: + COMM_Console_Print_String(" KTag 'Instigate Game' packet found!"); + break; + + case BLE_PACKET_TYPE_JOIN_NOW: + COMM_Console_Print_String(" KTag 'Join Now' packet found!"); + break; + + case BLE_PACKET_TYPE_TAG: + COMM_Console_Print_String(" KTag 'Tag' packet found!"); + break; + + case BLE_PACKET_TYPE_CONSOLE: + COMM_Console_Print_String(" KTag 'Console' packet found!"); + break; + + case BLE_PACKET_TYPE_STATUS: + COMM_Console_Print_String(" KTag 'Status' packet found!"); + break; + + default: + COMM_Console_Print_String(" Unknown KTag packet found!"); + break; + } + + COMM_Console_Print_String(" RSSI: "); + COMM_Console_Print_Int8(packet->Generic.RSSI); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + if (packet->Generic.type == BLE_PACKET_TYPE_CONSOLE) + { + packet->Console.console_data[BLE_KTAG_PACKET_DATA_SIZE - 1] = COMM_CONSOLE_STRING_TERMINATOR; + COMM_Console_Execute_Internal_Command(packet->Console.console_data); + } + else + { + KEvent_T packet_received_event = {.ID = KEVENT_BLE_PACKET_RECEIVED, .Data = packet}; + Post_KEvent(&packet_received_event); + } + } +#if (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + else + { + COMM_Console_Print_String(" Not a KTag packet!\n"); + } +#endif // (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + } + break; + + case CY_BLE_EVT_GAP_AUTH_REQ: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_AUTH_REQ: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle); + COMM_Console_Print_String(" security=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).security); + COMM_Console_Print_String(" bonding=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding); + COMM_Console_Print_String(" ekeySize=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).ekeySize); + COMM_Console_Print_String(" authErr=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + + if(cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].security == + (CY_BLE_GAP_SEC_MODE_1 | CY_BLE_GAP_SEC_LEVEL_1)) + { + cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].authErr = + CY_BLE_GAP_AUTH_ERROR_PAIRING_NOT_SUPPORTED; + } + + cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].bdHandle = + ((cy_stc_ble_gap_auth_info_t *)eventParam)->bdHandle; + + /* Pass security information for authentication in reply to an authentication request + * from the master device */ + apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]); + if(apiResult != CY_BLE_SUCCESS) + { + Cy_BLE_GAP_RemoveOldestDeviceFromBondedList(); + apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]); + if(apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_AuthReqReply API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + break; + + case CY_BLE_EVT_GAP_PASSKEY_ENTRY_REQUEST: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_PASSKEY_ENTRY_REQUEST:\n"); + COMM_Console_Print_String(" Please enter the passkey displayed on the peer device.\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_PASSKEY_DISPLAY_REQUEST: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_PASSKEY_DISPLAY_REQUEST: "); + COMM_Console_Print_UInt32(*(uint32_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_AUTH_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_AUTH_COMPLETE: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle); + COMM_Console_Print_String(" security=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).security); + COMM_Console_Print_String(" bonding=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding); + COMM_Console_Print_String(" ekeySize=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).ekeySize); + COMM_Console_Print_String(" authErr=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_AUTH_FAILED: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_AUTH_FAILED: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle); + COMM_Console_Print_String(" authErr=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAPP_ADVERTISEMENT_START_STOP: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAPP_ADVERTISEMENT_START_STOP: state="); + COMM_Console_Print_UInt8(Cy_BLE_GetAdvertisementState()); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + +#if 0 + if (Cy_BLE_GetAdvertisementState() == CY_BLE_ADV_STATE_STOPPED) + { + apiResult = StartNextAdvertisement(); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } +#endif // 0 + break; + + case CY_BLE_EVT_GAP_DEVICE_CONNECTED: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_DEVICE_CONNECTED: connIntv="); + COMM_Console_Print_UInt16(((cy_stc_ble_gap_connected_param_t *)eventParam)->connIntv * 5u /4u); + COMM_Console_Print_String(" ms\n"); +#endif // TRACE_BLE + + /* Set security keys for new device which is not already bonded */ + if(App_IsDeviceInBondList((*(cy_stc_ble_gap_connected_param_t *)eventParam).bdHandle) == 0u) + { + keyInfo.SecKeyParam.bdHandle = (*(cy_stc_ble_gap_connected_param_t *)eventParam).bdHandle; + apiResult = Cy_BLE_GAP_SetSecurityKeys(&keyInfo); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_SetSecurityKeys API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + break; + + case CY_BLE_EVT_GAP_DEVICE_DISCONNECTED: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_DEVICE_DISCONNECTED: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_disconnect_param_t *)eventParam).bdHandle); + COMM_Console_Print_String(" reason=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_disconnect_param_t *)eventParam).reason); + COMM_Console_Print_String(" status=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_disconnect_param_t *)eventParam).status); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + + apiResult = StartNextAdvertisement(); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + break; + + case CY_BLE_EVT_GAP_ENCRYPT_CHANGE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_ENCRYPT_CHANGE: 0x"); + COMM_Console_Print_UInt8AsHex(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_CONNECTION_UPDATE_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAPC_SCAN_START_STOP: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAPC_SCAN_START_STOP\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_KEYINFO_EXCHNGE_CMPLT: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_NUMERIC_COMPARISON_REQUEST: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_NUMERIC_COMPARISON_REQUEST:\n"); + COMM_Console_Print_String(" Compare this passkey with the one displayed in your peer device and press 'y' or 'n':\n"); + COMM_Console_Print_String(" "); + COMM_Console_Print_UInt32(*(uint32_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_KEYPRESS_NOTIFICATION: + case CY_BLE_EVT_GAP_OOB_GENERATED_NOTIFICATION: + case CY_BLE_EVT_GAP_ENHANCE_CONN_COMPLETE: + case CY_BLE_EVT_GAPC_DIRECT_ADV_REPORT: + case CY_BLE_EVT_GAP_SMP_NEGOTIATED_AUTH_INFO: + case CY_BLE_EVT_GAP_DEVICE_ADDR_GEN_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_KEYS_GEN_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_KEYS_GEN_COMPLETE\n"); +#endif // TRACE_BLE + keyInfo.SecKeyParam = (*(cy_stc_ble_gap_sec_key_param_t *)eventParam); + Cy_BLE_GAP_SetIdAddress(&cy_ble_deviceAddress); + break; + + case CY_BLE_EVT_GAP_RESOLVE_DEVICE_COMPLETE: + case CY_BLE_EVT_GAP_GEN_SET_LOCAL_P256_KEYS_COMPLETE: + case CY_BLE_EVT_GAP_CREATE_CONN_CANCEL_COMPLETE: + case CY_BLE_EVT_GAP_CONN_ESTB: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAPP_UPDATE_ADV_SCAN_DATA_COMPLETE: +#if (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAPP_UPDATE_ADV_SCAN_DATA_COMPLETE: "); + COMM_Console_Print_UInt8(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + break; + + case CY_BLE_EVT_GAP_ADV_TX: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_ADV_TX\n"); +#endif // TRACE_BLE + break; + + // G E N E R I C A T T R I B U T E P R O F I L E E V E N T S (0x5000 to 0x5FFF) + case CY_BLE_EVT_GATTC_ERROR_RSP: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GATTC_ERROR_RSP: opCode=0x"); + COMM_Console_Print_UInt8AsHex(((cy_stc_ble_gatt_err_param_t*)eventParam)->errInfo.opCode); + COMM_Console_Print_String(" errorCode=0x"); + COMM_Console_Print_UInt8AsHex(((cy_stc_ble_gatt_err_param_t*)eventParam)->errInfo.errorCode); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GATT_CONNECT_IND: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GATT_CONNECT_IND: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_conn_handle_t *)eventParam).bdHandle); + COMM_Console_Print_String(" attId=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_conn_handle_t *)eventParam).attId); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + { + cy_stc_ble_conn_handle_t connHandle = *(cy_stc_ble_conn_handle_t*)eventParam; + appConnHandle[connHandle.attId] = *(cy_stc_ble_conn_handle_t *)eventParam; + } + break; + + case CY_BLE_EVT_GATT_DISCONNECT_IND: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GATT_DISCONNECT_IND: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_conn_handle_t *)eventParam).bdHandle); + COMM_Console_Print_String(" attId=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_conn_handle_t *)eventParam).attId); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + { + cy_stc_ble_conn_handle_t connHandle = *(cy_stc_ble_conn_handle_t*)eventParam; + appConnHandle[connHandle.attId].attId = connHandle.attId; + appConnHandle[connHandle.attId].bdHandle = CY_BLE_INVALID_CONN_HANDLE_VALUE; + } + break; + + case CY_BLE_EVT_GATTS_XCNHG_MTU_REQ: + { + cy_stc_ble_gatt_xchg_mtu_param_t mtu = + { + .connHandle = ((cy_stc_ble_gatt_xchg_mtu_param_t *)eventParam)->connHandle + }; + Cy_BLE_GATT_GetMtuSize(&mtu); +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GATTS_XCNHG_MTU_REQ: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex(mtu.connHandle.bdHandle); + COMM_Console_Print_String(" attId=0x"); + COMM_Console_Print_UInt8AsHex(mtu.connHandle.bdHandle); + COMM_Console_Print_String(" mtu="); + COMM_Console_Print_UInt16(mtu.mtu); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + break; + + case CY_BLE_EVT_GATTC_XCHNG_MTU_RSP: + case CY_BLE_EVT_GATTC_READ_BY_GROUP_TYPE_RSP: + case CY_BLE_EVT_GATTC_READ_BY_TYPE_RSP: + case CY_BLE_EVT_GATTC_FIND_INFO_RSP: + case CY_BLE_EVT_GATTC_FIND_BY_TYPE_VALUE_RSP: + case CY_BLE_EVT_GATTC_READ_RSP: + case CY_BLE_EVT_GATTC_READ_BLOB_RSP: + case CY_BLE_EVT_GATTC_READ_MULTI_RSP: + case CY_BLE_EVT_GATTS_WRITE_REQ: + case CY_BLE_EVT_GATTC_WRITE_RSP: + case CY_BLE_EVT_GATTS_WRITE_CMD_REQ: + case CY_BLE_EVT_GATTS_PREP_WRITE_REQ: + case CY_BLE_EVT_GATTS_EXEC_WRITE_REQ: + case CY_BLE_EVT_GATTC_EXEC_WRITE_RSP: + case CY_BLE_EVT_GATTC_HANDLE_VALUE_NTF: + case CY_BLE_EVT_GATTC_HANDLE_VALUE_IND: + case CY_BLE_EVT_GATTS_HANDLE_VALUE_CNF: + case CY_BLE_EVT_GATTS_DATA_SIGNED_CMD_REQ: + case CY_BLE_EVT_GATTC_STOP_CMD_COMPLETE: + case CY_BLE_EVT_GATTS_READ_CHAR_VAL_ACCESS_REQ: + case CY_BLE_EVT_GATTC_LONG_PROCEDURE_END: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + default: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt32AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + } + } +} + +/******************************************************************************* +* Function Name: IasEventHandler +******************************************************************************** +* +* Summary: +* This is an event callback function to receive events from the BLE Component, +* which are specific to Immediate Alert Service. +* +* Parameters: +* event: Write Command event from the BLE component. +* eventParams: A structure instance of CY_BLE_GATT_HANDLE_VALUE_PAIR_T type. +* +*******************************************************************************/ +static void IASEventHandler(uint32 event, void * eventParam) +{ + (void) eventParam; + uint8_t alert; + + /* Alert Level Characteristic write event */ + if (event == CY_BLE_EVT_IASS_WRITE_CHAR_CMD) + { + /* Read the updated Alert Level value from the GATT database */ + Cy_BLE_IASS_GetCharacteristicValue(CY_BLE_IAS_ALERT_LEVEL, sizeof(alert), &alert); + COMM_BLE_IASAlertLevel = alert; + } +} + +static cy_en_ble_api_result_t StartNextAdvertisement() +{ + static uint8_t Current_Advertising_Index = CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX; + cy_en_ble_api_result_t apiResult; + + apiResult = Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, Current_Advertising_Index); + + if(apiResult == CY_BLE_SUCCESS) + { + if (Current_Advertising_Index == CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX) + { + Current_Advertising_Index = CY_BLE_BROADCASTER_CONFIGURATION_0_INDEX; + COMM_Console_Print_String("CY_BLE_BROADCASTER_CONFIGURATION_0_INDEX\n"); + } + else + { + Current_Advertising_Index = CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX; + COMM_Console_Print_String("CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX\n"); + } + } + + return apiResult; +} diff --git a/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE.h b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE.h new file mode 100644 index 0000000..83701e6 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE.h @@ -0,0 +1,79 @@ +/** \dir "BLE" + * + * \brief This directory contains source code for managing Bluetooth Low Energy communications. + * + */ + +/** \file + * \brief This file defines the interface to the Bluetooth Low Energy communications used by this software. + * + */ + +#ifndef COMM_BLE_H +#define COMM_BLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +// Define this to print out BLE trace statements to the console. +//#define TRACE_BLE +//#define VERBOSE_BLE_TRACE + +#define COMM_BLE_TASK_STACK_SIZE_in_bytes 4096 + +typedef enum +{ + COMM_BLE_DEFAULT, + COMM_BLE_INITIALIZING, + COMM_BLE_IDLE, + COMM_BLE_SCANNING_FOR_KTAG_PACKETS, + COMM_BLE_ADVERTISING_AS_PERIPHERAL, + COMM_BLE_ADVERTISING_AS_BROADCASTER, + COMM_BLE_SCANNING_AND_ADVERTISING +} COMM_BLE_StateID_T; + +typedef enum +{ + COMM_BLE_COMMAND_NO_OP, + COMM_BLE_REQUEST_STATE_CHANGE, + COMM_BLE_PROCESS_BLE_EVENTS, + COMM_BLE_SCAN_FOR_KTAG_PACKETS, + COMM_BLE_ADVERTISE_AS_BROADCASTER, + COMM_BLE_ADVERTISE_AS_PERIPHERAL, + COMM_BLE_STOP_ADVERTISING, + COMM_BLE_SCAN_AND_ADVERTISE, + // COMM_BLE_COMMAND_IS_OUT_OF_RANGE is one more than the last valid command. + COMM_BLE_COMMAND_IS_OUT_OF_RANGE +} COMM_BLE_Command_ID_T; + +typedef struct +{ + COMM_BLE_Command_ID_T ID; + void * Data; +} COMM_BLE_Command_T; + +/* Include Files */ + +/* Public Variables */ + +extern cy_stc_ble_conn_handle_t appConnHandle[CY_BLE_CONN_COUNT]; +extern volatile uint8_t COMM_BLE_IASAlertLevel; + +extern QueueHandle_t COMM_BLE_CommandQueue; + +//! Handle of the COMM_BLE_Task() given when the task was created. +extern TaskHandle_t COMM_BLE_Task_Handle; + +/* Public Functions */ +void COMM_BLE_Init(void); +void COMM_BLE_Task(void * pvParameters); +void COMM_BLE_RequestState(COMM_BLE_StateID_T state); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_BLE_H diff --git a/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_Bond.c b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_Bond.c new file mode 100644 index 0000000..ece43a5 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_Bond.c @@ -0,0 +1,252 @@ +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/* Public Variables */ + +/* Private Variables */ + +static bool removeBondListFlag = false; + +/* Private Function Prototypes */ + +/* Public Functions */ + +/******************************************************************************* +* Function Name: App_DisplayBondList() +******************************************************************************** +* +* Summary: +* This function displays the bond list. +* +*******************************************************************************/ +void App_DisplayBondList(void) +{ +#ifdef TRACE_BLE + cy_en_ble_api_result_t apiResult; + cy_stc_ble_gap_peer_addr_info_t bondedDeviceInfo[CY_BLE_MAX_BONDED_DEVICES]; + cy_stc_ble_gap_bonded_device_list_info_t bondedDeviceList = + { + .bdHandleAddrList = bondedDeviceInfo + }; + uint8_t deviceCount; + + /* Find out whether the device has bonded information stored already or not */ + apiResult = Cy_BLE_GAP_GetBondList(&bondedDeviceList); + if (apiResult != CY_BLE_SUCCESS) + { + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_GetBondList API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); + } + else + { + deviceCount = bondedDeviceList.noOfDevices; + + if(deviceCount != 0u) + { + uint8_t counter; + + COMM_Console_Print_String("[BLE] Bond list:\n"); + + do + { + COMM_Console_Print_String(" "); + COMM_Console_Print_UInt8(deviceCount); + COMM_Console_Print_String(". "); + + deviceCount--; + + if(bondedDeviceList.bdHandleAddrList[deviceCount].bdAddr.type == CY_BLE_GAP_ADDR_TYPE_RANDOM) + { + COMM_Console_Print_String("Peer Random Address:"); + } + else + { + COMM_Console_Print_String("Peer Public Address:"); + } + + for (counter = CY_BLE_GAP_BD_ADDR_SIZE; counter > 0u; counter--) + { + COMM_Console_Print_String(" "); + COMM_Console_Print_UInt8AsHex(bondedDeviceList.bdHandleAddrList[deviceCount].bdAddr.bdAddr[counter - 1u]); + } + COMM_Console_Print_String(", bdHandle: 0x"); + COMM_Console_Print_UInt8AsHex(bondedDeviceList.bdHandleAddrList[deviceCount].bdHandle); + COMM_Console_Print_String("\n"); + } while (deviceCount != 0u); + COMM_Console_Print_String("\n"); + } + } +#endif // TRACE_BLE +} + + +/******************************************************************************* +* Function Name: App_RemoveDevidesFromBondList +******************************************************************************** +* +* Summary: +* Remove devices from the bond list. +* +*******************************************************************************/ +void App_RemoveDevicesFromBondList(void) +{ +#if(CY_BLE_BONDING_REQUIREMENT == CY_BLE_BONDING_YES) + cy_en_ble_api_result_t apiResult; + cy_stc_ble_gap_bd_addr_t peerBdAddr = { .type = 0u }; +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cleaning Bond List...\n\n"); +#endif // TRACE_BLE + + /* Remove all bonded devices in the list */ + apiResult = Cy_BLE_GAP_RemoveBondedDevice(&peerBdAddr); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_RemoveBondedDevice API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + else + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_RemoveBondedDevice complete.\n\n"); +#endif // TRACE_BLE + } +#else +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Bonding is disabled...no need to remove bonded devices.\n\n"); +#endif // TRACE_BLE +#endif /* (CY_BLE_BONDING_REQUIREMENT == CY_BLE_BONDING_YES) */ + + /* Clean flag */ + removeBondListFlag = false; +} + + +/******************************************************************************* +* Function Name: App_GetCountOfBondedDevices() +******************************************************************************** +* +* Summary: +* This function returns the count of bonded devices +* +* Return: +* uint32_t The count of bonded devices +* +*******************************************************************************/ +uint32_t App_GetCountOfBondedDevices(void) +{ + cy_en_ble_api_result_t apiResult; + cy_stc_ble_gap_peer_addr_info_t bondedDeviceInfo[CY_BLE_MAX_BONDED_DEVICES]; + cy_stc_ble_gap_bonded_device_list_info_t bondedDeviceList = + { + .bdHandleAddrList = bondedDeviceInfo + }; + uint32_t deviceCount = 0u; + + /* Find out whether the device has bonded information stored already or not */ + apiResult = Cy_BLE_GAP_GetBondList(&bondedDeviceList); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_GetBondList API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + else + { + deviceCount = bondedDeviceList.noOfDevices; + } + + return (deviceCount); +} + + +/******************************************************************************* +* Function Name: App_IsDeviceInBondList() +******************************************************************************** +* +* Summary: +* This function check if device with bdHandle is in the bond list +* +* Parameters: +* bdHandle - bond device handler +* +* Return: +* bool - true value when bdHandle exists in bond list +* +*******************************************************************************/ +bool App_IsDeviceInBondList(uint32_t bdHandle) +{ + cy_en_ble_api_result_t apiResult; + cy_stc_ble_gap_peer_addr_info_t bondedDeviceInfo[CY_BLE_MAX_BONDED_DEVICES]; + cy_stc_ble_gap_bonded_device_list_info_t bondedDeviceList = + { + .bdHandleAddrList = bondedDeviceInfo + }; + bool deviceIsDetected = false; + uint32_t deviceCount; + + /* Find out whether the device has bonding information stored already or not */ + apiResult = Cy_BLE_GAP_GetBondList(&bondedDeviceList); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_GetBondList API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + else + { + deviceCount = bondedDeviceList.noOfDevices; + + if(deviceCount != 0u) + { + do + { + deviceCount--; + if(bdHandle == bondedDeviceList.bdHandleAddrList[deviceCount].bdHandle) + { + deviceIsDetected = 1u; + } + } while(deviceCount != 0u); + } + } + return(deviceIsDetected); +} + +/******************************************************************************* +* Function Name: App_SetRemoveBondListFlag() +******************************************************************************** +* Summary: +* Set flag for removing bond list +* +*******************************************************************************/ +void App_SetRemoveBondListFlag(void) +{ + removeBondListFlag = true; +} + +/******************************************************************************* +* Function Name: App_IsRemoveBondListFlag() +******************************************************************************** +* Summary: +* Get value of remove bond list flag +* +* Return: +* true - remove bond list flag is set +* false - remove bond list flag is clear +* +*******************************************************************************/ +bool App_IsRemoveBondListFlag(void) +{ + return ((removeBondListFlag == true) ? true : false); +} + +/* Private Functions */ diff --git a/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_Bond.h b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_Bond.h new file mode 100644 index 0000000..ef5f43b --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_Bond.h @@ -0,0 +1,32 @@ +/** \file + * \brief This file declares Bluetooth Low Energy bond list helper functions. + * + */ + +#ifndef COMM_BLE_BOND_H +#define COMM_BLE_BOND_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +/* Include Files */ + +/* Public Variables */ + +/* Public Functions */ +void App_DisplayBondList(void); +void App_RemoveDevicesFromBondListBySW2Press(uint32_t seconds); +void App_RemoveDevicesFromBondList(void); +void App_SetRemoveBondListFlag(void); +bool App_IsRemoveBondListFlag(void); +bool App_IsDeviceInBondList(uint32_t bdHandle); +uint32_t App_GetCountOfBondedDevices(void); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_BLE_BOND_H diff --git a/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_UART.c b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_UART.c new file mode 100644 index 0000000..a50ed0f --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_UART.c @@ -0,0 +1,177 @@ +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +#define UART_CIRCULAR_BUFFER_SIZE 1024 +#define BLE_UART_BUFFER_CHARACTERISTIC_SIZE 20 + +/* Public Variables */ + +/* Private Variables */ + +static uint_fast16_t UART_Tx_Notifications_Enabled = 0; + +static uint8_t UART_Tx_Buffer_Storage[UART_CIRCULAR_BUFFER_SIZE]; +static UTIL_CircularBuffer_T UART_Tx_Buffer; +static uint8_t BLE_UART_Tx_Buffer[BLE_UART_BUFFER_CHARACTERISTIC_SIZE]; +static uint8_t Rx_Buffer[BLE_UART_BUFFER_CHARACTERISTIC_SIZE + 1]; + +/* Private Function Prototypes */ + +/* Public Functions */ + +void COMM_BLE_UART_Init(void) +{ + UTIL_InitCircularBuffer(&UART_Tx_Buffer, UART_Tx_Buffer_Storage, UART_CIRCULAR_BUFFER_SIZE); +} + +//! Sends a message over the BLE UART. +void COMM_BLE_UART_PutString(const char8 * string, uint16_t length) +{ + for (uint8_t i = 0; i < length; i++) + { + (void) UTIL_PushToCircularBuffer(&UART_Tx_Buffer, *string++); + } +} + +//! Sends a single character over the BLE UART. +void COMM_BLE_UART_PutChar(char8 character) +{ + (void) UTIL_PushToCircularBuffer(&UART_Tx_Buffer, character); +} + +void COMM_BLE_UART_MaybeSendData(void) +{ + int8_t length = 0; + + if (UTIL_IsCircularBufferEmpty(&UART_Tx_Buffer) == false) + { + while ((length < BLE_UART_BUFFER_CHARACTERISTIC_SIZE) && (UTIL_IsCircularBufferEmpty(&UART_Tx_Buffer) == false)) + { + uint8_t value; + if (UTIL_PopFromCircularBuffer(&UART_Tx_Buffer, &value) == UTIL_CIRCULARBUFFERRESULT_SUCCESS) + { + BLE_UART_Tx_Buffer[length] = value; + length++; + } + } + } + + if (length > 0) + { + for (uint_fast8_t i = 0; i < CY_BLE_CONN_COUNT; i++) + { + if (Cy_BLE_GetConnectionState(appConnHandle[i]) >= CY_BLE_CONN_STATE_CONNECTED) + { + cy_stc_ble_gatt_handle_value_pair_t tempHandle; + + tempHandle.attrHandle = CY_BLE_NORDIC_UART_SERVICE_TX_CHAR_HANDLE; + tempHandle.value.val = (uint8 *) BLE_UART_Tx_Buffer; + tempHandle.value.actualLen = length; + tempHandle.value.len = length; + + Cy_BLE_GATTS_WriteAttributeValueLocal(&tempHandle); + } + } + + // Send notification to each client that has TX notifications enabled. + for (uint_fast8_t i = 0; i < CY_BLE_CONN_COUNT; i++) + { + if ((Cy_BLE_GetConnectionState(appConnHandle[i]) >= CY_BLE_CONN_STATE_CONNECTED) && + Cy_BLE_GATTS_IsNotificationEnabled(&appConnHandle[i], + CY_BLE_NORDIC_UART_SERVICE_TX_TXCCCD_DESC_HANDLE)) + { + cy_stc_ble_gatt_handle_value_pair_t tempHandle; + + tempHandle.attrHandle = CY_BLE_NORDIC_UART_SERVICE_TX_CHAR_HANDLE; + tempHandle.value.val = (uint8 *) BLE_UART_Tx_Buffer; + tempHandle.value.actualLen = length; + tempHandle.value.len = length; + + Cy_BLE_GATTS_SendNotification(&appConnHandle[i], &tempHandle); + } + } + } +} + +//! BLE event handler for the BLE UART feature. +/*! + * This function should be called *before* events are handled in the event handler passed to + * Cy_BLE_Start(). If it returns `false`, then the rest of the event handler should proceed. + * + * \param event BLE stack event code received from the BLE middleware (one of cy_en_ble_event_t). + * \param eventParam pointer to an event-specific data structure containing the relevant event information. + * \return true if this handler has completely handled the event, and no further + * handling is necessary; false otherwise. + */ +bool COMM_BLE_UART_HandleEvent(uint32 event, void * eventParam) +{ + static cy_stc_ble_gatts_write_cmd_req_param_t * writeReqParameter; + bool handled = false; + + /* Take an action based on the current event */ + switch ((cy_en_ble_event_t)event) + { + // Handle a write request. + case CY_BLE_EVT_GATTS_WRITE_REQ: + + writeReqParameter = (cy_stc_ble_gatts_write_cmd_req_param_t*)eventParam; + + // Request to write the UART. + // https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk5.v15.2.0%2Fble_sdk_app_nus_eval.html&cp=5_5_0_4_1_2_24 + if (writeReqParameter->handleValPair.attrHandle == CY_BLE_NORDIC_UART_SERVICE_RX_CHAR_HANDLE) + { + // Only update the value and write the response if the requested write is allowed. + if (CY_BLE_GATT_ERR_NONE == Cy_BLE_GATTS_WriteAttributeValuePeer(&writeReqParameter->connHandle, &writeReqParameter->handleValPair)) + { + uint16_t i; + + for (i = 0; (i < BLE_UART_BUFFER_CHARACTERISTIC_SIZE) && (i < writeReqParameter->handleValPair.value.len); i++) + { + Rx_Buffer[i] = writeReqParameter->handleValPair.value.val[i]; + } + + // NULL-terminate the buffer. + Rx_Buffer[i] = 0x00; + + Cy_BLE_GATTS_WriteRsp(writeReqParameter->connHandle); + + COMM_Console_Execute_Internal_Command(Rx_Buffer); + } + + handled = true; + } + + // Request for UART Tx notifications. + if (writeReqParameter->handleValPair.attrHandle == CY_BLE_NORDIC_UART_SERVICE_TX_TXCCCD_DESC_HANDLE) + { + if (CY_BLE_GATT_ERR_NONE == Cy_BLE_GATTS_WriteAttributeValuePeer(&writeReqParameter->connHandle, &writeReqParameter->handleValPair)) + { + UART_Tx_Notifications_Enabled = writeReqParameter->handleValPair.value.val[0] & 0x01; + + if (UART_Tx_Notifications_Enabled) + { + COMM_Console_Print_String("[BLE] UART Tx notifications enabled.\n"); + } + else + { + COMM_Console_Print_String("[BLE] UART Tx notifications disabled.\n"); + } + + Cy_BLE_GATTS_WriteRsp(writeReqParameter->connHandle); + } + + handled = true; + } + break; + + default: + // (`handled` is already set to false.) + break; + } + + return handled; +} + +/* Private Functions */ diff --git a/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_UART.h b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_UART.h new file mode 100644 index 0000000..b0f924e --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/BLE/COMM_BLE_UART.h @@ -0,0 +1,30 @@ +/** \file + * \brief This file declares interface functions to a BLE UART implementation. + * + */ + +#ifndef COMM_BLE_UART_H +#define COMM_BLE_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +/* Include Files */ + +/* Public Variables */ + +/* Public Functions */ +void COMM_BLE_UART_Init(void); +void COMM_BLE_UART_PutString(const char8 * string, uint16_t length); +void COMM_BLE_UART_PutChar(char8 character); +void COMM_BLE_UART_MaybeSendData(void); +bool COMM_BLE_UART_HandleEvent(uint32 event, void * eventParam); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_BLE_UART_H \ No newline at end of file diff --git a/2020TPCApp1.cydsn/COMM/COMM.h b/2020TPCApp1.cydsn/COMM/COMM.h new file mode 100644 index 0000000..269a3bf --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM.h @@ -0,0 +1,50 @@ +/** \dir "COMM" + * + * \brief This directory contains source code for the communication interfaces used by this software. + * + */ + +/** \file + * \brief This file defines the interface to the communications used by this software. + * + * This file should be included by any file outside the COMM package wishing to make use + * of any of the configuration information provided by the COMM package. + * + */ + +#ifndef COMM_H +#define COMM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ +#include "COMM_IPC_Messages.h" +#include "BLE/COMM_BLE.h" +#include "BLE/COMM_BLE_Bond.h" +#include "BLE/COMM_BLE_UART.h" +#include "COMM_Console.h" +#include "COMM_Console_Util.h" +#include "COMM_I2C_Bus.h" +#include "COMM_Util.h" +#include "ConsoleCommands/COMM_ConsoleCommands.h" +#include "ConsoleCommands/COMM_BLE_ConsoleCommands.h" +#include "ConsoleCommands/COMM_NVM_ConsoleCommands.h" +#include "ConsoleCommands/COMM_RTOS_ConsoleCommands.h" +#include "ConsoleCommands/COMM_STATE_ConsoleCommands.h" + +/* Preprocessor and Type Definitions */ + +#define DebugPrintf(...) +#define Task_DebugPrintf(...) + +/* Public Variables */ + +/* Public Functions */ + +#ifdef __cplusplus +} +#endif + +#endif // COMM_H diff --git a/2020TPCApp1.cydsn/COMM/COMM_Console.c b/2020TPCApp1.cydsn/COMM/COMM_Console.c new file mode 100644 index 0000000..1d612b3 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_Console.c @@ -0,0 +1,639 @@ +/** \file + * \brief This file implements a simple serial debug console and command interpreter. + */ + +/** \defgroup CONSOLE Console + * + * \brief Serial debug console command interpreter. + * + * \todo Describe the command interpreter. + * + * @{ + * @} + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +//! Text representations of numeric digits, used by COMM_Console_Print_UInt32(). +static const char8 DIGITS[] = "0123456789ABCDEF"; + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +//! Maximum number of characters (save one) able to be printed by COMM_Console_Print_String(). +#define MAX_CONSOLE_STRING_LENGTH 81 + +//! States in the COMM_Console_Task() state machine. +typedef enum +{ + COMM_STATE_INITIALIZING = 0, + COMM_STATE_DISPLAY_POWERUP_INFO, + COMM_STATE_IDLE, + COMM_STATE_COMMAND_TOO_LONG, + COMM_STATE_IDENTIFY_COMMAND, + COMM_STATE_EXECUTE_COMMAND, + COMM_STATE_UNKNOWN_COMMAND +} COMM_Console_State_T; + +/* Public Variables */ +char8 Command_Buffer[COMM_CONSOLE_COMMAND_MAX_LENGTH]; +uint_fast16_t Command_Buffer_Index = 0; +TaskHandle_t COMM_Console_Task_Handle; + +/* Private Variables */ + +//! Current state of the COMM_Console_Task() state machine. +static COMM_Console_State_T Current_State = COMM_STATE_INITIALIZING; + +//! Next state of the COMM_Console_Task() state machine. +static COMM_Console_State_T Next_State = COMM_STATE_INITIALIZING; + +//! Index into the #COMM_Console_Command_Table for the command currently being handled. +/*! + * If #Current_Command is set to UINT_FAST16_MAX, the command being handled is unknown, or no command is being handled. + */ +static uint_fast16_t Current_Command = 0; + +/* Private Function Prototypes */ + +static void ConsoleISR(void); +static bool ConsoleCommandMatches(const char8 * const command_name); +static void ReverseString(char8 * value, uint32_t length); + +/* Inline Functions */ + +//! Swaps the characters in x and y. +static inline void Swap_Char8(char8 * x, char8 * y) +{ + uint8_t temp = *x; + *x = *y; + *y = temp; + } + +static inline void Reset_Command_Buffer() +{ + taskENTER_CRITICAL(); + for (uint_fast16_t i = 0; i < COMM_CONSOLE_COMMAND_MAX_LENGTH; i++) + { + Command_Buffer[i] = COMM_CONSOLE_STRING_TERMINATOR; + } + Command_Buffer_Index = 0; + taskEXIT_CRITICAL(); +} + +/* Public Functions */ + +//! Initializes the console. +/*! + * \ingroup CONSOLE + */ +void COMM_Console_Init(void) +{ + // Enable the pullup on the Rx pin to keep the noise down. + Cy_GPIO_SetDrivemode(UART_Console_rx_PORT, UART_Console_rx_NUM, CY_GPIO_DM_PULLUP); + UART_Console_Start(); + + /// Unmask only the RX FIFO not empty interrupt bit. + UART_Console_HW->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk; + Cy_SysInt_Init(&Int_UART_Console_cfg, ConsoleISR); + NVIC_ClearPendingIRQ(Int_UART_Console_cfg.intrSrc); + NVIC_EnableIRQ(Int_UART_Console_cfg.intrSrc); +} + +//! Parses and handle console commands in the background. +/*! + * \ingroup CONSOLE + * + * The [UML State Machine Diagram](http://www.uml-diagrams.org/state-machine-diagrams.html) below + * shows how the console messages processed by this code. Note that all of the *Character Rx'd* + * transitions occur in the #UART_Console_SPI_UART_ISR_EntryCallback() itself on the PSoC4, in + * #ConsoleRxISR() on the PSoC5, and in #ConsoleISR() on the PSoC6, to improve overall performance. + * + * \startuml{COMM_Console_Task.png} "Console Task" + * + * skinparam headerFontSize 18 + * skinparam state { + * BackgroundColor #eeeeee + * BackgroundColor<> #ffaaaa + * FontName Impact + * FontSize 18 + * } + * skinparam note { + * FontName "Comic Sans MS" + * FontStyle italic + * } + * + * state "Initializing" as STATE_INITIALIZING + * [*] --> STATE_INITIALIZING + * note left of STATE_INITIALIZING : Wait for the rest of the system to come online. + * state "Display Powerup Info" as STATE_DISPLAY_POWERUP_INFO + * STATE_DISPLAY_POWERUP_INFO : do/ print OS version + * STATE_DISPLAY_POWERUP_INFO : do/ print configuration (debug or release) + * STATE_INITIALIZING --> STATE_DISPLAY_POWERUP_INFO : after(100ms) + * state "Idle" as STATE_IDLE + * STATE_IDLE : do/ RTOS_Sleep() + * STATE_DISPLAY_POWERUP_INFO --> STATE_IDLE + * state STATE_IS_EOM <> + * note top of STATE_IS_EOM : This happens in\nUART_Console_SPI_UART_ISR_ExitCallback() on PSoC4,\nConsoleRxISR() on PSoC5,\nand ConsoleISR() on PSoC6. + * STATE_IDLE --> STATE_IS_EOM : character rx'd + * state STATE_IS_COMMAND_BUFFER_FULL <> + * note top of STATE_IS_COMMAND_BUFFER_FULL : This happens in\nUART_Console_SPI_UART_ISR_ExitCallback() on PSoC4,\nConsoleRxISR() on PSoC5,\nand ConsoleISR() on PSoC6. + * STATE_IS_EOM --> STATE_IS_COMMAND_BUFFER_FULL : [else] + * state "Identify Command" as STATE_IDENTIFY_COMMAND + * STATE_IDENTIFY_COMMAND : do/ look for command in the COMM_Console_Command_Table[] + * STATE_IS_EOM --> STATE_IDENTIFY_COMMAND : [rx'd character is EOM] + * STATE_IDLE --> STATE_IDENTIFY_COMMAND : COMM_Console_Execute_Internal_Command() + * state "Command Too Long" as STATE_COMMAND_TOO_LONG + * STATE_COMMAND_TOO_LONG : do/ print error message + * STATE_COMMAND_TOO_LONG : do/ reset command buffer + * STATE_IS_COMMAND_BUFFER_FULL --> STATE_COMMAND_TOO_LONG : [command buffer is full] + * STATE_IS_COMMAND_BUFFER_FULL --> STATE_IDLE : [else]/\nAppend received character to command buffer + * STATE_COMMAND_TOO_LONG --> STATE_IDLE + * state "Execute Command" as STATE_EXECUTE_COMMAND + * STATE_EXECUTE_COMMAND : do/ execute console command + * STATE_EXECUTE_COMMAND : exit/ reset command buffer + * STATE_EXECUTE_COMMAND --> STATE_IDLE + * STATE_IDENTIFY_COMMAND --> STATE_EXECUTE_COMMAND : [command matched] + * state "Unknown Command" as STATE_UNKNOWN_COMMAND + * STATE_UNKNOWN_COMMAND : do/ print error message + * STATE_UNKNOWN_COMMAND : do/ reset command buffer + * STATE_IDENTIFY_COMMAND --> STATE_UNKNOWN_COMMAND : [else] + * STATE_UNKNOWN_COMMAND --> STATE_IDLE + * + * left footer Key: UML 2.5\nLast modified 2020-12-14 + * \enduml + * + * \return None (infinite loop) + */ +void COMM_Console_Task(void * pvParameters) +{ + static TickType_t xTicksToWait = pdMS_TO_TICKS(10); + static uint32_t * NotificationValue; + + while(true) + { + (void) xTaskNotifyWait(0, 0, (uint32_t *)&NotificationValue, xTicksToWait); + + // Change to the next state atomically. + taskENTER_CRITICAL(); + Current_State = Next_State; + taskEXIT_CRITICAL(); + + switch (Current_State) + { + default: + case COMM_STATE_INITIALIZING: + Next_State = COMM_STATE_DISPLAY_POWERUP_INFO; + vTaskDelay(pdMS_TO_TICKS(10)); + xTicksToWait = 1; + break; + + case COMM_STATE_DISPLAY_POWERUP_INFO: + COMM_Console_Print_String("[COMM] "); + COMM_RTOS_HandleConsoleVersion(NULL, 0); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("[COMM] Console ready (awaiting commands).\n"); + Next_State = COMM_STATE_IDLE; + xTicksToWait = 1; + break; + + case COMM_STATE_IDLE: + xTicksToWait = pdMS_TO_TICKS(100); + break; + + case COMM_STATE_COMMAND_TOO_LONG: + COMM_Console_Print_String("[COMM] ERROR: Command \""); + COMM_Console_Print_String(Command_Buffer); + COMM_Console_Print_String("\" too long!\n"); + Reset_Command_Buffer(); + Next_State = COMM_STATE_IDLE; + xTicksToWait = 1; + break; + + case COMM_STATE_IDENTIFY_COMMAND: + Current_Command = UINT_FAST16_MAX; + + for (uint_fast16_t i = 0; i < COMM_N_CONSOLE_COMMANDS; i++) + { + if (ConsoleCommandMatches(COMM_Console_Command_Table[i].Command_Name) == true) + { + Current_Command = i; + Next_State = COMM_STATE_EXECUTE_COMMAND; + xTicksToWait = 1; + break; + } + } + + if (Current_Command == UINT_FAST16_MAX) + { + // No matching command was found. + Next_State = COMM_STATE_UNKNOWN_COMMAND; + xTicksToWait = 1; + } + break; + + case COMM_STATE_EXECUTE_COMMAND: + if (COMM_Console_Command_Table[Current_Command].Execute_Command != NULL) + { + COMM_Console_Command_Result_T result = COMM_Console_Command_Table[Current_Command].Execute_Command(Command_Buffer, Command_Buffer_Index); + + if (result == COMM_CONSOLE_CMD_RESULT_PARAMETER_ERROR) + { + COMM_Console_Print_String("ERROR: Parameter error!\n"); + } + } + Reset_Command_Buffer(); + Next_State = COMM_STATE_IDLE; + xTicksToWait = 1; + break; + + case COMM_STATE_UNKNOWN_COMMAND: + COMM_Console_Print_String("ERROR: Command \""); + COMM_Console_Print_String(Command_Buffer); + COMM_Console_Print_String("\" not recognized! Try '?' for help.\n"); + Reset_Command_Buffer(); + Next_State = COMM_STATE_IDLE; + xTicksToWait = 1; + break; + } + } +} + +SystemKResult_T HW_Execute_Console_Command(const uint8_t * const command) +{ + COMM_Console_Execute_Internal_Command(command); + + return SYSTEMK_RESULT_SUCCESS; +} + +//! Executes a (potentially cross-task) console command. +/*! + * This function is used to initiate a console command from a software source internal to this + * CPU. This provides a way to use preexisting console commands on TX-only consoles. + * + * \note If two calls to this function are made back-to-back (before the COMM_Console_Task() has an + * opportunity to run), only the second command will be executed, as it will have overwritten the + * first. Allow time for the console commands to execute between calls to this function. + * + * \param command String containing the command to be executed. + */ +void COMM_Console_Execute_Internal_Command(const uint8_t * const command) +{ + bool finished = false; + uint_fast16_t i = 0; + + taskENTER_CRITICAL(); + while ( (finished == false) && + (i < COMM_CONSOLE_COMMAND_MAX_LENGTH) && + (command[i] != COMM_CONSOLE_END_OF_MESSAGE ) && + (command[i] != COMM_CONSOLE_STRING_TERMINATOR ) + ) + { + Command_Buffer[i] = command[i]; + i++; + } + Command_Buffer_Index = i; + + // If there is still room, terminate the command. + if (i < COMM_CONSOLE_COMMAND_MAX_LENGTH) + { + Command_Buffer[i] = COMM_CONSOLE_END_OF_MESSAGE; + } + taskEXIT_CRITICAL(); + + Next_State = COMM_STATE_IDENTIFY_COMMAND; + xTaskNotifyGive(COMM_Console_Task_Handle); +} + +//! Prints a NULL-terminated string to the serial console. +void COMM_Console_Print_String(const char8 * const text) +{ + for (size_t i = 0; i < MAX_CONSOLE_STRING_LENGTH; i++) + { + // Check for the end of the string. If there is no NULL terminator, up to + // MAX_CONSOLE_STRING_LENGTH characters of randomness will be printed. + if (text[i] == COMM_CONSOLE_STRING_TERMINATOR) + { + break; + } + + // Send out the string, one character at a time. + COMM_Console_PutChar(text[i]); + } +} + +//! Prints a 32-bit unsigned integer to the serial console. +void COMM_Console_Print_UInt32(uint32_t value) +{ + // The largest string for a unit32_t is 10 characters (4294967296). + char8 buffer[10+1]; + uint_fast8_t buffer_index = 0; + + while (value > 9) + { + uint8_t digit_index = value % 10; + buffer[buffer_index] = DIGITS[digit_index]; + value = value / 10; + buffer_index++; + } + buffer[buffer_index] = DIGITS[value]; + buffer_index++; + ReverseString(buffer, buffer_index); + + // NULL-terminate the string. + buffer[buffer_index] = 0; + + COMM_Console_Print_String(buffer); +} + +//! Prints a 32-bit signed integer to the serial console. +void COMM_Console_Print_SInt32(int32_t value) +{ + if (value < 0) + { + value *= -1; + COMM_Console_PutChar('-'); + } + + COMM_Console_Print_UInt32(value); +} + +//! Prints a 32-bit unsigned integer to the serial console using a hexadecimal representation. +void COMM_Console_Print_UInt32AsHex(uint32_t value) +{ + // The largest hexadecimal string for a unit32_t is 8 characters (FFFFFFFF). + char8 buffer[8+1]; + uint_fast8_t buffer_index = 0; + + while (value > 15) + { + uint8_t digit_index = value % 16; + buffer[buffer_index] = DIGITS[digit_index]; + value = value / 16; + buffer_index++; + } + buffer[buffer_index] = DIGITS[value]; + buffer_index++; + ReverseString(buffer, buffer_index); + + // NULL-terminate the string. + buffer[buffer_index] = 0; + + COMM_Console_PutChar('0'); + COMM_Console_PutChar('x'); + COMM_Console_Print_String(buffer); +} + +//! Prints a 64-bit unsigned integer to the serial console. +void COMM_Console_Print_UInt64(uint64_t value) +{ + // The largest string for a unit64_t is 20 characters (18446744073709551615). + char8 buffer[20+1]; + uint_fast8_t buffer_index = 0; + + while (value > 9) + { + uint8_t digit_index = value % 10; + buffer[buffer_index] = DIGITS[digit_index]; + value = value / 10; + buffer_index++; + } + buffer[buffer_index] = DIGITS[value]; + buffer_index++; + ReverseString(buffer, buffer_index); + + // NULL-terminate the string. + buffer[buffer_index] = 0; + + COMM_Console_Print_String(buffer); +} + +//! Prints a 64-bit unsigned integer to the serial console using a hexadecimal representation. +void COMM_Console_Print_UInt64AsHex(uint64_t value) +{ + // The largest hexadecimal string for a unit64_t is 16 characters (FFFFFFFFFFFFFFFF). + char8 buffer[16+1]; + uint_fast8_t buffer_index = 0; + + while (value > 15) + { + uint8_t digit_index = value % 16; + buffer[buffer_index] = DIGITS[digit_index]; + value = value / 16; + buffer_index++; + } + buffer[buffer_index] = DIGITS[value]; + buffer_index++; + ReverseString(buffer, buffer_index); + + // NULL-terminate the string. + buffer[buffer_index] = 0; + + COMM_Console_PutChar('0'); + COMM_Console_PutChar('x'); + COMM_Console_Print_String(buffer); +} + +//! Prints a floating-point number to the serial console. +/*! + * With thanks to Rick Regan and his [Quick and Dirty Floating-Point to Decimal Conversion](https://www.exploringbinary.com/quick-and-dirty-floating-point-to-decimal-conversion/). + */ +void COMM_Console_Print_Float(float value) +{ + #define MAX_INTEGRAL_DIGITS 12 + #define MAX_FRACTIONAL_DIGITS 6 + #define BUFFER_SIZE (MAX_INTEGRAL_DIGITS + MAX_FRACTIONAL_DIGITS + 2) + + char8 buffer[BUFFER_SIZE]; + char8 integral_buffer_reversed[MAX_INTEGRAL_DIGITS]; + uint16_t buffer_index = 0; + double integral_value; + double fractional_value; + bool overflow = false; + + if (value < 0.0) + { + COMM_Console_Print_String("-"); + value *= -1.0; + } + + // Break the given value into fractional and integral parts. + fractional_value = modf(value, &integral_value); + + if (integral_value > 0) + { + // Convert the integral part. + while ((integral_value > 0) && (buffer_index < MAX_INTEGRAL_DIGITS)) + { + integral_buffer_reversed[buffer_index++] = '0' + (int)fmod(integral_value, 10); + integral_value = floor(integral_value / 10); + } + + // If there is still an integral part remaining, and overflow has occurred. + if (integral_value > 0) + { + overflow = true; + } + + // Reverse and append the integral part. + for (uint16_t i = 0; i < buffer_index; i++) + { + buffer[i] = integral_buffer_reversed[buffer_index-i-1]; + } + } + else + { + // Append a leading zero. + buffer[buffer_index++] = '0'; + } + + // Append the decimal point. + buffer[buffer_index++] = '.'; + + // Convert the fractional part, even if it is zero, and leave room for the NULL terminator. + while (buffer_index < (BUFFER_SIZE - 1)) + { + fractional_value *= 10; + buffer[buffer_index++] = '0' + (int)fractional_value; + fractional_value = modf(fractional_value, &integral_value); + } + + // Append the NULL terminator. + buffer[buffer_index] = 0; + + if (overflow == true) + { + COMM_Console_Print_String("OVERFLOW"); + } + else + { + COMM_Console_Print_String(buffer); + } +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +//! Converts a byte to a two-character hexadecimal representation. +/*! + * \param buffer Buffer into which to place the resulting sting. It needs to be at least three + * characters wide. + * \param byte The byte to be converted. + */ +void COMM_Console_ByteToHex(char8 * buffer, uint8_t byte) +{ + if (byte < 16) + { + buffer[0] = '0'; + buffer[1] = DIGITS[byte]; + buffer[2] = 0; + } + else + { + buffer[0] = DIGITS[byte / 16]; + buffer[1] = DIGITS[byte % 16]; + buffer[2] = 0; + } +} + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Private Functions */ + +static void ConsoleISR(void) +{ + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + // Check for the "Rx FIFO not empty" interrput. + if ((UART_Console_HW->INTR_RX_MASKED & SCB_INTR_RX_MASKED_NOT_EMPTY_Msk ) != 0) + { + // Clear the "Rx FIFO not empty" interrput. + UART_Console_HW->INTR_RX = UART_Console_HW->INTR_RX & SCB_INTR_RX_NOT_EMPTY_Msk; + + // Get the character. + uint32_t value = UART_Console_Get(); + + // Check if there is actually data. Sometimes the flag is set when there is no data (why?). + if (value != CY_SCB_UART_RX_NO_DATA) + { + char8 rx_data = (char8) value; + + // Determine what to do with it. + if (Command_Buffer_Index < COMM_CONSOLE_COMMAND_MAX_LENGTH) + { + if (rx_data == COMM_CONSOLE_END_OF_MESSAGE) + { + Command_Buffer[Command_Buffer_Index] = COMM_CONSOLE_STRING_TERMINATOR; + Next_State = COMM_STATE_IDENTIFY_COMMAND; + vTaskNotifyGiveFromISR(COMM_Console_Task_Handle, &xHigherPriorityTaskWoken); + } + else + { + Command_Buffer[Command_Buffer_Index] = rx_data; + Command_Buffer_Index++; + } + } + else + { + Next_State = COMM_STATE_COMMAND_TOO_LONG; + vTaskNotifyGiveFromISR(COMM_Console_Task_Handle, &xHigherPriorityTaskWoken); + } + } + } + + NVIC_ClearPendingIRQ(Int_UART_Console_cfg.intrSrc); + + // If the state needs to change, a context switch might be required. + portEND_SWITCHING_ISR(xHigherPriorityTaskWoken); +} + +static bool ConsoleCommandMatches(const char8 * const command_name) +{ + uint32_t i = 0; + bool is_match = false; + + if (Command_Buffer[i] == command_name[i]) + { + is_match = true; + i++; + } + + while ( (is_match == true) && + (i < COMM_CONSOLE_COMMAND_MAX_LENGTH) && + (Command_Buffer[i] != COMM_CONSOLE_PARAMETER_DELIMITER) && + (Command_Buffer[i] != COMM_CONSOLE_END_OF_MESSAGE ) && + (Command_Buffer[i] != COMM_CONSOLE_STRING_TERMINATOR ) + ) + { + if ( Command_Buffer[i] != command_name[i] ) + { + is_match = false; + } + i++; + } + + return is_match; +} + +//! Reverses a string in place. +/*! + * \param value Pointer to the string to be reversed. + * \param length Length of the string, including the NULL terminator. + */ +static void ReverseString(char8 * value, uint32_t length) +{ + if (length > 1) + { + uint_fast32_t start = 0; + uint_fast32_t end = length - 1; + while (start < end) + { + Swap_Char8(value + start, value + end); + start++; + end--; + } + } +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCApp1.cydsn/COMM/COMM_Console.h b/2020TPCApp1.cydsn/COMM/COMM_Console.h new file mode 100644 index 0000000..916cb6c --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_Console.h @@ -0,0 +1,144 @@ +/** \file + * \brief This file defines the interface to a simple serial debug console and command interpreter. + * + * \note As always, and should be included before this file. + */ + +#ifndef COMM_CONSOLE_H +#define COMM_CONSOLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +#define COMM_CONSOLE_TASK_STACK_SIZE_in_bytes 512 + +#define COMM_Console_PutChar UART_and_BLE_PutChar +#define COMM_Console_PutString UART_and_BLE_PutString + +#define COMM_CONSOLE_COMMAND_MAX_LENGTH 50 + +//! Character signifying the end of a console message. +#define COMM_CONSOLE_END_OF_MESSAGE ('\n') + +//! Character used between parameters in a console message. +#define COMM_CONSOLE_PARAMETER_DELIMITER (' ') + +//! Character signifying the end of a string. +#define COMM_CONSOLE_STRING_TERMINATOR ('\0') + +//! Result of executing a console command callback. +typedef enum +{ + COMM_CONSOLE_CMD_RESULT_UNKNOWN = 0, + COMM_CONSOLE_CMD_RESULT_SUCCESS = 1, + COMM_CONSOLE_CMD_RESULT_PARAMETER_ERROR = 2 +} COMM_Console_Command_Result_T; + +//! Result of parsing a console command parameter. +typedef enum +{ + COMM_CONSOLE_PARAMETER_RESULT_UNKNOWN = 0, + COMM_CONSOLE_PARAMETER_RESULT_SUCCESS = 1, + COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR = 2, + COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END = 3 +} COMM_Console_Parameter_Result_T; + +//! Prototype of a console command callback. +/*! + * \ingroup CONSOLE + * All console commands must use this signature. + * + * \param[in] data Pointer to the string containg the console command (and any arguments). + * \param[in] size Size (in char8) of the data string. + * \return #COMM_CONSOLE_CMD_RESULT_SUCCESS on success + * \return #COMM_Console_Command_Result_T otherwise + */ +typedef COMM_Console_Command_Result_T (* const COMM_Console_Command_Handler_T)(char8 * data, uint32_t size); + +typedef struct +{ + const char8 * const Command_Name; + const char8 * const Help; + COMM_Console_Command_Handler_T Execute_Command; +} COMM_Console_Command_Table_Entry_T; + +/* Public Variables */ + +//! Handle of the COMM_Console_Task() given when the task was created. +extern TaskHandle_t COMM_Console_Task_Handle; + +/* Public Functions */ + +void COMM_Console_Init(void); +void COMM_Console_Task(void * pvParameters); +void COMM_Console_Execute_Internal_Command(const uint8_t * const command); +void COMM_Console_Print_String(const char8 * const text); +void COMM_Console_Print_UInt32(uint32_t value); +void COMM_Console_Print_SInt32(int32_t value); +void COMM_Console_Print_UInt32AsHex(uint32_t value); +void COMM_Console_Print_UInt64(uint64_t value); +void COMM_Console_Print_UInt64AsHex(uint64_t value); +void COMM_Console_Print_Float(float value); + +void COMM_Console_ByteToHex(char8 * buffer, uint8_t byte); + +/* Inline Functions */ + +//! Prints an 8-bit unsigned integer to the serial console. +inline void COMM_Console_Print_UInt8(uint8_t value) +{ + COMM_Console_Print_UInt32((uint32_t) value); +} + +//! Prints an 8-bit unsigned integer to the serial console using a hexadecimal representation. +inline void COMM_Console_Print_UInt8AsHex(uint8_t value) +{ + COMM_Console_Print_UInt32AsHex((uint32_t) value); +} + +//! Prints an 8-bit signed integer to the serial console. +inline void COMM_Console_Print_Int8(int8_t value) +{ + COMM_Console_Print_SInt32((int32_t) value); +} + +//! Prints a 16-bit unsigned integer to the serial console. +inline void COMM_Console_Print_UInt16(uint16_t value) +{ + COMM_Console_Print_UInt32((uint32_t) value); +} + +//! Prints a 16-bit unsigned integer to the serial console using a hexadecimal representation. +inline void COMM_Console_Print_UInt16AsHex(uint16_t value) +{ + COMM_Console_Print_UInt32AsHex((uint32_t) value); +} + +//! Prints a 16-bit signed integer to the serial console. +inline void COMM_Console_Print_Int16(int16_t value) +{ + COMM_Console_Print_SInt32((int32_t) value); +} + +static inline void UART_and_BLE_PutChar(uint8 txDataByte) +{ + UART_Console_Put(txDataByte); + COMM_BLE_UART_PutChar(txDataByte); +} + +static inline void UART_and_BLE_PutString(const char8 string[]) +{ + UART_Console_PutString(string); + COMM_BLE_UART_PutString(string, strlen(string)); +} + +#ifdef __cplusplus +} +#endif + +#endif // COMM_CONSOLE_H diff --git a/2020TPCApp1.cydsn/COMM/COMM_Console_Util.c b/2020TPCApp1.cydsn/COMM/COMM_Console_Util.c new file mode 100644 index 0000000..0a68b17 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_Console_Util.c @@ -0,0 +1,254 @@ +/** \file + * \brief This file implements utility functions used by the command interpreter. + */ + +/** + * \ingroup CONSOLE + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Public Variables */ + +/* Private Variables */ + +/* Private Function Prototypes */ + +/* Public Functions */ + +//! Find the start location of the nth parameter in the buffer. +/*! + * \note The command itself is parameter 0. + */ +COMM_Console_Parameter_Result_T COMM_Console_FindNthParameter(const char * const buffer, const uint8_t parameterNumber, const char ** parameterLocation) +{ + uint32_t buffer_index = 0; + uint32_t parameter_index = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + + while (parameterNumber != parameter_index) + { + if (buffer[buffer_index] == COMM_CONSOLE_PARAMETER_DELIMITER) + { + parameter_index++; + } + else if (buffer[buffer_index] == COMM_CONSOLE_END_OF_MESSAGE) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + else if (buffer[buffer_index] == COMM_CONSOLE_STRING_TERMINATOR) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + buffer_index++; + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + *parameterLocation = &buffer[buffer_index]; + } + + return result; +} + + +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt8(const char * const buffer, uint8_t * const parameterUInt8) +{ + uint8_t value = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + + // Strings containing uint8s range from "0" to "255". The large number has three characters. + uint_fast16_t MAX_CHARACTERS = 3; + uint_fast16_t index = 0; + + while (index < (MAX_CHARACTERS + 1)) + { + if ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + value *= 10; + value += buffer[index] - '0'; + index++; + } + else if ( (buffer[index] == COMM_CONSOLE_PARAMETER_DELIMITER) || + (buffer[index] == COMM_CONSOLE_STRING_TERMINATOR) || + (buffer[index] == COMM_CONSOLE_END_OF_MESSAGE) ) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END; + break; + } + else + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END) + { + result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + *parameterUInt8 = value; + } + + return result; +} + + +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt16(const char * const buffer, uint16_t * const parameterUInt16) +{ + uint16_t value = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + + // Strings containing uint16s range from "0" to "65535". The large number has five characters. + uint_fast16_t MAX_CHARACTERS = 5; + uint_fast16_t index = 0; + + while (index < (MAX_CHARACTERS + 1)) + { + if ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + value *= 10; + value += buffer[index] - '0'; + index++; + } + else if ( (buffer[index] == COMM_CONSOLE_PARAMETER_DELIMITER) || + (buffer[index] == COMM_CONSOLE_STRING_TERMINATOR) || + (buffer[index] == COMM_CONSOLE_END_OF_MESSAGE) ) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END; + break; + } + else + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END) + { + result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + *parameterUInt16 = value; + } + + return result; +} + +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterInt32(const char * const buffer, int32_t * const parameterInt32) +{ + int32_t value = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + bool is_negative = false; + + // Strings containing int32s range from "-2147483648" to "2147483647". The negative number has eleven characters. + uint_fast16_t MAX_CHARACTERS = 11; + uint_fast16_t index = 0; + + if (buffer[index] == '-') + { + is_negative = true; + index++; + } + + while (index < (MAX_CHARACTERS + 1)) + { + if ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + value *= 10; + value += buffer[index] - '0'; + index++; + } + else if ( (buffer[index] == COMM_CONSOLE_PARAMETER_DELIMITER) || + (buffer[index] == COMM_CONSOLE_STRING_TERMINATOR) || + (buffer[index] == COMM_CONSOLE_END_OF_MESSAGE) ) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END; + break; + } + else + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + } + + if (is_negative == true) + { + value *= -1; + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END) + { + result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + *parameterInt32 = value; + } + + return result; +} + +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt32(const char * const buffer, uint32_t * const parameterUInt32) +{ + uint32_t value = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + + // Strings containing uint32s range from "0" to "4294967296". The large number has ten characters. + uint_fast16_t MAX_CHARACTERS = 10; + uint_fast16_t index = 0; + + while (index < (MAX_CHARACTERS + 1)) + { + if ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + value *= 10; + value += buffer[index] - '0'; + index++; + } + else if ( (buffer[index] == COMM_CONSOLE_PARAMETER_DELIMITER) || + (buffer[index] == COMM_CONSOLE_STRING_TERMINATOR) || + (buffer[index] == COMM_CONSOLE_END_OF_MESSAGE) ) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END; + break; + } + else + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END) + { + result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + *parameterUInt32 = value; + } + + return result; +} + +COMM_Console_Parameter_Result_T COMM_Console_DecodeHexParameterUInt64(const char * const buffer, uint64_t * const parameterUInt64) +{ + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + struct _reent context; + + context._errno = 0; + + *parameterUInt64 = _strtoull_r(&context, buffer, NULL, 16); + + if (context._errno != 0) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + } + + return result; +} + +/* Private Functions */ + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCApp1.cydsn/COMM/COMM_Console_Util.h b/2020TPCApp1.cydsn/COMM/COMM_Console_Util.h new file mode 100644 index 0000000..7fccbaf --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_Console_Util.h @@ -0,0 +1,50 @@ +/** \file + * \brief Utility functions used by the command interpreter. + * + * \note As always, and should be included before this file. + */ + +#ifndef COMM_CONSOLE_UTIL_H +#define COMM_CONSOLE_UTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Parameter_Result_T COMM_Console_FindNthParameter(const char * const buffer, const uint8_t parameterNumber, const char ** parameterLocation); +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt8(const char * const buffer, uint8_t * const parameterUInt8); +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt16(const char * const buffer, uint16_t * const parameterUInt16); +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterInt32(const char * const buffer, int32_t * const parameterInt32); +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt32(const char * const buffer, uint32_t * const parameterUInt32); +COMM_Console_Parameter_Result_T COMM_Console_DecodeHexParameterUInt64(const char * const buffer, uint64_t * const parameterUInt64); + +//! Returns `true` if this character marks the end of a console message; `false` otherwise. +inline bool COMM_Console_IsEndOfMessage(char8 character) +{ + bool result = false; + + if ( (character == COMM_CONSOLE_END_OF_MESSAGE) || + (character == COMM_CONSOLE_STRING_TERMINATOR) ) + { + result = true; + } + + return result; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_CONSOLE_UTIL_H diff --git a/2020TPCApp1.cydsn/COMM/COMM_I2C_Bus.c b/2020TPCApp1.cydsn/COMM/COMM_I2C_Bus.c new file mode 100644 index 0000000..7fe82f6 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_I2C_Bus.c @@ -0,0 +1,33 @@ +/** \file + * \brief This file implements the I²C bus. + * + * See COMM_I2C_Bus.h for a detailed description of the functionality implemented by this code. + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/* Public Variables */ + +SemaphoreHandle_t COMM_I2C_Bus_Mutex = NULL; + +/* Private Variables */ + +/* Private Function Prototypes */ + +/* Public Functions */ + +//! Initializes the I²C bus. +/*! + * + */ +void COMM_I2C_Init(void) +{ + COMM_I2C_Bus_Mutex = xSemaphoreCreateMutex(); + I2C_Start(); +} + + +/* Private Functions */ diff --git a/2020TPCApp1.cydsn/COMM/COMM_I2C_Bus.h b/2020TPCApp1.cydsn/COMM/COMM_I2C_Bus.h new file mode 100644 index 0000000..414e7f2 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_I2C_Bus.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file defines the interface to the I²C bus. + * + */ + +#ifndef COMM_I2C_BUS_H +#define COMM_I2C_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + + +/* Include Files */ + + +/* Public Variables */ +extern SemaphoreHandle_t COMM_I2C_Bus_Mutex; + +/* Public Functions */ +void COMM_I2C_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_I2C_BUS_H diff --git a/2020TPCApp1.cydsn/COMM/COMM_IPC_Messages.c b/2020TPCApp1.cydsn/COMM/COMM_IPC_Messages.c new file mode 100644 index 0000000..605d8df --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_IPC_Messages.c @@ -0,0 +1,285 @@ +/** \file + * \brief This file implements messaging using inter-processor communication (IPC). + * +* \see https://community.cypress.com/thread/36182. + */ + +/** + * \ingroup CONSOLE + */ + +/* Include Files */ +#include +#include +#include +#include +#include +#include + +#include "COMM_IPC_Messages.h" + +/* Private Function Prototypes */ + +#if (__CORTEX_M == 0) +static void Message_Received_for_CM0(uint32_t * msg); +static void Message_Received_by_CM4(void); +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) +static void Message_Received_for_CM4(uint32_t * msg); +static void Message_Received_by_CM0(void); +#endif // (__CORTEX_M == 4) + +static void IPC_UserPipeInit(void); +static void IPC_UserPipeISR(void); + + +/* Local Definitions and Constants */ + +//! Number of clients supported on the user pipe. +#define CY_IPC_USRPIPE_CLIENT_CNT (uint32_t)(8u) + +#define CY_IPC_CHAN_USRPIPE_CM0 (uint32_t)(8u) +#define CY_IPC_CHAN_USRPIPE_CM4 (uint32_t)(9u) + +#define CY_IPC_INTR_USRPIPE_CM0 (uint32_t)(8u) +#define CY_IPC_INTR_USRPIPE_CM4 (uint32_t)(9u) + +#define CY_IPC_EP_USRPIPE_ADDR_CM0_EP (uint32_t)(2u) +#define CY_IPC_EP_USRPIPE_ADDR_CM4_EP (uint32_t)(3u) + +#if (CY_CPU_CORTEX_M0P) + #define IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_ADDR_CM0_EP +#else + #define IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_ADDR_CM4_EP +#endif /* (CY_CPU_CORTEX_M0P) */ + +/* User Pipe Configuration */ + +#define IPC_USRPIPE_CHAN_MASK_CM0 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM0) +#define IPC_USRPIPE_CHAN_MASK_CM4 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM4) +#define IPC_USRPIPE_INTR_MASK (uint32_t)( IPC_USRPIPE_CHAN_MASK_CM0 | IPC_USRPIPE_CHAN_MASK_CM4 ) +#define IPC_INTR_USRPIPE_PRIOR_CM0 (uint32_t)(1u) /* Notifier Priority */ +#define IPC_INTR_USRPIPE_PRIOR_CM4 (uint32_t)(1u) /* Notifier Priority */ +#define IPC_INTR_USRPIPE_MUX_CM0 (uint32_t)(7u) /* IPC CYPRESS PIPE */ +#define IPC_USRPIPE_CONFIG_CM0 (uint32_t)(IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos)\ + |(CY_IPC_INTR_USRPIPE_CM0 << CY_IPC_PIPE_CFG_INTR_Pos )\ + |(CY_IPC_CHAN_USRPIPE_CM0) +#define IPC_USRPIPE_CONFIG_CM4 (uint32_t)(IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos)\ + |(CY_IPC_INTR_USRPIPE_CM4 << CY_IPC_PIPE_CFG_INTR_Pos )\ + |(CY_IPC_CHAN_USRPIPE_CM4) + +#define USRPIPE_CONFIG \ +{\ + /* .ep0ConfigData */ {\ + /* .ipcNotifierNumber */ CY_IPC_INTR_USRPIPE_CM0,\ + /* .ipcNotifierPriority */ IPC_INTR_USRPIPE_PRIOR_CM0,\ + /* .ipcNotifierMuxNumber */ IPC_INTR_USRPIPE_MUX_CM0,\ + /* .epAddress */ CY_IPC_EP_USRPIPE_ADDR_CM0_EP,\ + /* .epConfig */ IPC_USRPIPE_CONFIG_CM0\ + },\ + /* .ep1ConfigData */ {\ + /* .ipcNotifierNumber */ CY_IPC_INTR_USRPIPE_CM4,\ + /* .ipcNotifierPriority */ IPC_INTR_USRPIPE_PRIOR_CM4,\ + /* .ipcNotifierMuxNumber */ 0u,\ + /* .epAddress */ CY_IPC_EP_USRPIPE_ADDR_CM4_EP,\ + /* .epConfig */ IPC_USRPIPE_CONFIG_CM4\ + },\ + /* .endpointClientsCount */ CY_IPC_USRPIPE_CLIENT_CNT,\ + /* .endpointsCallbacksArray */ ipc_pipe_CbArray,\ + /* .userPipeIsrHandler */ &IPC_UserPipeISR\ +} + +//! Client ID for messages from the CM0 to the CM4 +#define COMM_IPC_CM0_TO_CM4_CLIENT_ID 0 +//! Client ID for messages from the CM4 to the CM0 +#define COMM_IPC_CM4_TO_CM0_CLIENT_ID 1 + + +/* Public Variables */ + +/* Private Variables */ + +#if (__CORTEX_M == 0) +static COMM_IPCMessage_T MessageBuffer = +{ + .ClientID = _VAL2FLD(CY_IPC_PIPE_MSG_CLIENT, COMM_IPC_CM0_TO_CM4_CLIENT_ID) | _VAL2FLD(CY_IPC_PIPE_MSG_USR, 0) | _VAL2FLD(CY_IPC_PIPE_MSG_RELEASE, IPC_USRPIPE_INTR_MASK), + .MessageID = COMM_SMM_DefaultNoMessage, + .Data = NULL +}; + +static volatile bool OK_to_send_from_CM0_to_CM4 = true; +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) +static COMM_IPCMessage_T MessageBuffer = +{ + .ClientID = _VAL2FLD(CY_IPC_PIPE_MSG_CLIENT, COMM_IPC_CM4_TO_CM0_CLIENT_ID) | _VAL2FLD(CY_IPC_PIPE_MSG_USR, 0) | _VAL2FLD(CY_IPC_PIPE_MSG_RELEASE, IPC_USRPIPE_INTR_MASK), + .MessageID = COMM_SMM_DefaultNoMessage, + .Data = NULL +}; + +static volatile bool OK_to_send_from_CM4_to_CM0 = true; +#endif // (__CORTEX_M == 4) + + +/* Public Functions */ + +#if (__CORTEX_M == 0) +//! Initializes the inter-processor communications on the Cortex-M0 core. +/*! + * This should be called *before* calling Cy_SysEnableCM4(). + */ +void COMM_InitIPCMessages(void) +{ + IPC_UserPipeInit(); + + // Register a callback to handle messages from CM4. + Cy_IPC_Pipe_RegisterCallback(IPC_EP_USRPIPE_ADDR, + Message_Received_for_CM0, + CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) +//! Initializes the inter-processor communications on the Cortex-M4 core. +void COMM_InitIPCMessages(void) +{ + IPC_UserPipeInit(); + + // Register a callback to handle messages from CM0. + Cy_IPC_Pipe_RegisterCallback(IPC_EP_USRPIPE_ADDR, + Message_Received_for_CM4, + CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif // (__CORTEX_M == 4) + + +//! Sends an inter-processor communication message to the other core. +bool COMM_SendMessageToOtherCore(COMM_IPCMessageID_T message_ID, void * message_data) +{ + bool message_sent = false; + + MessageBuffer.MessageID = message_ID; + MessageBuffer.Data = message_data; + +#if (__CORTEX_M == 0) + if (OK_to_send_from_CM0_to_CM4 == true) + { + OK_to_send_from_CM0_to_CM4 = false; + uint32_t timeout_in_us = 2000; + cy_en_ipc_pipe_status_t ipcStatus; + + do + { + ipcStatus = Cy_IPC_Pipe_SendMessage(CY_IPC_EP_USRPIPE_ADDR_CM4_EP, + CY_IPC_EP_USRPIPE_ADDR_CM0_EP, + (uint32_t *) &MessageBuffer, + Message_Received_by_CM4); + Cy_SysLib_DelayUs(1u); + timeout_in_us--; + } while((ipcStatus != CY_IPC_PIPE_SUCCESS) && (timeout_in_us != 0)); + + message_sent = true; + } +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) + if (OK_to_send_from_CM4_to_CM0 == true) + { + OK_to_send_from_CM4_to_CM0 = false; + uint32_t timeout_in_us = 2000; + cy_en_ipc_pipe_status_t ipcStatus; + + do + { + ipcStatus = Cy_IPC_Pipe_SendMessage(CY_IPC_EP_USRPIPE_ADDR_CM0_EP, + CY_IPC_EP_USRPIPE_ADDR_CM4_EP, + (uint32_t *) &MessageBuffer, + Message_Received_by_CM0); + Cy_SysLib_DelayUs(1u); + timeout_in_us--; + } while((ipcStatus != CY_IPC_PIPE_SUCCESS) && (timeout_in_us != 0)); + + message_sent = true; + } +#endif // (__CORTEX_M == 4) + + return message_sent; +} + + +/* Private Functions */ + +#if (__CORTEX_M == 0) +//! Callback for messages received by the CM0 core from the CM4 core. +/*! + * \note This code is executed inside an interrupt handler. + */ +static void Message_Received_for_CM0(uint32_t * msg) +{ + switch (((COMM_IPCMessage_T *)msg)->MessageID) + { + default: + case COMM_SMM_DefaultNoMessage: + case COMM_SMM_NoMessage: + break; + + case COMM_SMM_RebootImmediately: + // Perform a software reset of both cores. + NVIC_SystemReset(); + break; + } +} + +static void Message_Received_by_CM4(void) +{ + OK_to_send_from_CM0_to_CM4 = true; +} +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) +//! Callback for messages received by the CM4 core from the CM0 core. +/*! + * \note This code is executed inside an interrupt handler. + */ +static void Message_Received_for_CM4(uint32_t * msg) +{ + switch (((COMM_IPCMessage_T *)msg)->MessageID) + { + default: + case COMM_SMM_DefaultNoMessage: + case COMM_SMM_NoMessage: + break; + + case COMM_SMM_RebootImmediately: + // This message does nothing on CM4 + break; + } +} + +static void Message_Received_by_CM0(void) +{ + OK_to_send_from_CM4_to_CM0 = true; +} +#endif // (__CORTEX_M == 4) + +//! Initializes the IPC user pipe. +static void IPC_UserPipeInit(void) +{ + static cy_ipc_pipe_callback_ptr_t ipc_pipe_CbArray[CY_IPC_USRPIPE_CLIENT_CNT]; + static const cy_stc_ipc_pipe_config_t userPipeConfig = USRPIPE_CONFIG; + + uint32_t savedIntrStatus = Cy_SysLib_EnterCriticalSection(); + + Cy_IPC_Pipe_Init(&userPipeConfig); + + Cy_SysLib_ExitCriticalSection(savedIntrStatus); +} + +//! Interrupt service routine for the user pipe. +void IPC_UserPipeISR(void) +{ + Cy_IPC_Pipe_ExecuteCallback(IPC_EP_USRPIPE_ADDR); +} + diff --git a/2020TPCApp1.cydsn/COMM/COMM_IPC_Messages.h b/2020TPCApp1.cydsn/COMM/COMM_IPC_Messages.h new file mode 100644 index 0000000..c6efdc3 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_IPC_Messages.h @@ -0,0 +1,49 @@ + +/** \file + * \brief This file contains definitions and prototypes for messaging using inter-processor + * communication (IPC). + */ + +#ifndef COMM_IPC_MESSAGES_H +#define COMM_IPC_MESSAGES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +typedef enum +{ + //! This is not an actual message. Upon receipt, do nothing. + COMM_SMM_DefaultNoMessage = 0, + //! Reboot the system immediately upon receipt of this message (Data is "don't care"). + COMM_SMM_RebootImmediately, + //! This is not an actual message. Upon receipt, do nothing. + COMM_SMM_NoMessage = 0xFFFFFFFF, +} COMM_IPCMessageID_T; + +typedef struct +{ + //! The client ID number is the index into the callback array. + uint32_t ClientID; + //! The message ID represents the meaning of the message being sent. + COMM_IPCMessageID_T MessageID; + //! The contents of Data are different for each message ID. See #COMM_IPCMessageID_T for more details. + void * Data; +} COMM_IPCMessage_T; + +/* Public Variables */ + +/* Public Functions */ + +void COMM_InitIPCMessages(void); +bool COMM_SendMessageToOtherCore(COMM_IPCMessageID_T message_ID, void * message_data); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_IPC_MESSAGES_H diff --git a/2020TPCApp1.cydsn/COMM/COMM_Util.c b/2020TPCApp1.cydsn/COMM/COMM_Util.c new file mode 100644 index 0000000..311d8a5 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_Util.c @@ -0,0 +1,48 @@ +/** \file + * \brief This file implements utility functions used by the communications package. + */ + +/** + * \ingroup CONSOLE + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/* Public Variables */ + +/* Private Variables */ +static char8 uint64_buffer[20+1]; + +/* Private Function Prototypes */ + +/* Public Functions */ + +//! Converts a UInt64 to a NULL-terminated string. +/*! + * This function is necessary because newlib-nano does not support "%llu" / #PRIu64. + * \see https://answers.launchpad.net/gcc-arm-embedded/+question/257014 + * + * \note This function is not reentrant! + * + * \param value pointer to the digital input object. + * \return pointer to a NULL-terminated string containing the base-10 textual representation of #value. + */ +char8 * COMM_UInt64ToDecimal(uint64_t value) +{ + char8 * p = uint64_buffer + sizeof(uint64_buffer); + *(--p) = 0x00; + + for (bool first_time = true; value || first_time; first_time = false) + { + const uint32_t digit = value % 10; + const char c = '0' + digit; + *(--p) = c; + value = value / 10; + } + return p; +} + +/* Private Functions */ diff --git a/2020TPCApp1.cydsn/COMM/COMM_Util.h b/2020TPCApp1.cydsn/COMM/COMM_Util.h new file mode 100644 index 0000000..0dc199a --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/COMM_Util.h @@ -0,0 +1,27 @@ +/** \file + * \brief Utility functions used by the communications package. + * + * \note As always, and should be included before this file. + */ + +#ifndef COMM_UTIL_H +#define COMM_UTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +char8 * COMM_UInt64ToDecimal(uint64_t value); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_UTIL_H diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.c b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.c new file mode 100644 index 0000000..183e994 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.c @@ -0,0 +1,78 @@ +/** \file + * \brief This file defines the serial console commands for the Bluetooth Low Energy subsystem. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) && (CONFIG__FEATURE_BLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ + +/* Public Variables */ + +/* Private Variables */ + +/* Public Functions */ + +/* Private Functions */ + +//! Console command handler for subcommands of the 'ble' command. +COMM_Console_Command_Result_T COMM_HandleBLECommand(char8 * data, uint32_t size) +{ + // data[0] through data[3] is 'ble '. + + if (data[4] == '?') + { + COMM_Console_Print_String("ble ? Display this help.\n"); + COMM_Console_Print_String("ble cmd Inject the BLE command with ID .\n"); + } + else if ( (data[4] == 'c') && + (data[5] == 'm') && + (data[6] == 'd') ) + + { + if (COMM_Console_IsEndOfMessage(data[7])) + { + COMM_Console_Print_String("ERROR: missing BLE command ID!\n"); + } + else if (data[7] == ' ') + { + uint16_t id = 0; + + if (COMM_Console_DecodeParameterUInt16(&(data[8]), &id) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + if ((id > COMM_BLE_COMMAND_NO_OP) && (id < COMM_BLE_COMMAND_IS_OUT_OF_RANGE)) + { + COMM_BLE_Command_T command = {.ID = id, .Data = (void *)0x00}; + xQueueSend(COMM_BLE_CommandQueue, &command, 0); + } + else + { + COMM_Console_Print_String("ERROR: specified BLE command ID ("); + COMM_Console_Print_UInt16(id); + COMM_Console_Print_String(") is invalid!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: could not comprehend BLE command ID!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: unrecognized or mangled command!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: Unknown BLE command!\n"); + } + + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) && (CONFIG__FEATURE_BLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.h b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.h new file mode 100644 index 0000000..014c11e --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file declares the serial console commands for the Bluetooth Low Energy subsystem. + */ + +#ifndef COMM_BLE_CONSOLECOMMANDS_H +#define COMM_BLE_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Command_Result_T COMM_HandleBLECommand(char8 * data, uint32_t size); + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_BLE_CONSOLECOMMANDS_H diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.c b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.c new file mode 100644 index 0000000..bee533d --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.c @@ -0,0 +1,73 @@ +/** \file + * \brief This file defines the serial console commands for this CPU. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ +static COMM_Console_Command_Result_T HandleConsoleHelp(char8 * data, uint32_t size); +static COMM_Console_Command_Result_T HandleConsoleComment(char8 * data, uint32_t size); +static COMM_Console_Command_Result_T HandleConsoleUptime(char8 * data, uint32_t size); + +/* Public Variables */ + +const COMM_Console_Command_Table_Entry_T COMM_Console_Command_Table[] = +{ + {"?", " Show this help.", HandleConsoleHelp}, + {"#", " Comment (Do not omit the space after the #.)", HandleConsoleComment}, + {"event", " Generate an event in the high-level state machine (\'event ?\' for help).", COMM_HandleEventCommand}, + {"ble", " Interact with the Bluetooth Low Energy subsystem (try \'ble ?\').", COMM_HandleBLECommand}, + {"up", " Display uptime.", HandleConsoleUptime}, + {"cpu (r)", " Display CPU usage ('r' to reset maximum).", COMM_RTOS_HandleConsoleCPU}, + {"stack", " Display stack usage.", COMM_RTOS_HandleConsoleStack}, + {"version", " Display RTOS version.", COMM_RTOS_HandleConsoleVersion}, + {"reboot", " Performs a software reset on both cores.", COMM_RTOS_HandleConsoleReboot}, + {"nvm", " Interact with the Nonvolatile Memory (try \'nvm ?\').", COMM_NVM_HandleConsoleNVMCommand}, + {"reprogram", " Loads the KTag bootloader for OTA reprogramming.", COMM_RTOS_HandleConsoleReprogram}, +}; + +//! Size of the #COMM_Console_Command_Table array (i.e. the number of console commands). +const uint_fast16_t COMM_N_CONSOLE_COMMANDS = (uint_fast16_t) (sizeof(COMM_Console_Command_Table) / sizeof(COMM_Console_Command_Table_Entry_T)); + +/* Private Variables */ + +/* Public Functions */ + +/* Private Functions */ + +static COMM_Console_Command_Result_T HandleConsoleHelp(char8 * data, uint32_t size) +{ + for (uint_fast16_t i = 0; i < COMM_N_CONSOLE_COMMANDS; i++) + { + COMM_Console_Print_String(COMM_Console_Command_Table[i].Command_Name); + COMM_Console_Print_String(" "); + COMM_Console_Print_String(COMM_Console_Command_Table[i].Help); + COMM_Console_Print_String("\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + } + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +static COMM_Console_Command_Result_T HandleConsoleComment(char8 * data, uint32_t size) +{ + COMM_Console_Print_String("Comment.\n"); + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +static COMM_Console_Command_Result_T HandleConsoleUptime(char8 * data, uint32_t size) +{ +#if (configTICK_RATE_HZ != 1000) +#error This code assumes configTICK_RATE_HZ is set to 1000 (== 1ms ticks)! +#endif // (configTICK_RATE_HZ != 1000) + COMM_Console_Print_String("Up "); + COMM_Console_Print_UInt32(xTaskGetTickCount()); + COMM_Console_Print_String(" milliseconds.\n"); + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.h b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.h new file mode 100644 index 0000000..c332d4d --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.h @@ -0,0 +1,30 @@ +/** \file + * \brief This file configures the serial console commands on this CPU. + */ + +#ifndef COMM_CONSOLECOMMANDS_H +#define COMM_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ +extern const COMM_Console_Command_Table_Entry_T COMM_Console_Command_Table[]; +extern const uint_fast16_t COMM_N_CONSOLE_COMMANDS; + +/* Public Functions */ + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_CONSOLECOMMANDS_H \ No newline at end of file diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.c b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.c new file mode 100644 index 0000000..ced911a --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.c @@ -0,0 +1,207 @@ +/** \file + * \brief This file defines the serial console commands for the Nonvolatile Memory. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ + +/* Public Variables */ + +/* Private Variables */ + +/* Public Functions */ + +/* Private Functions */ + +//! Console command handler for subcommands of the 'nvm' command. +COMM_Console_Command_Result_T COMM_NVM_HandleConsoleNVMCommand(char8 * data, uint32_t size) +{ + // data[0] through data[3] is 'nvm '. + if (data[4] == '?') + { + COMM_Console_Print_String("nvm ? Display this help.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("nvm dump Display the entire Nonvolatile Memory.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("nvm names Display the NVM parameter names.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("nvm get Display an individual parameter from NVM.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("nvm set Assign a value to an individual parameter in NVM (be careful!).\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + } + else if ((data[4] == 'd') && (data[5] == 'u') && (data[6] == 'm') && (data[7] == 'p')) + { + for (uint8_t i = 0; i < NVM_N_ONCHIP_EEPROM_ENTRIES; i++) + { + COMM_Console_Print_String("NVM["); + COMM_Console_Print_UInt16(i); + COMM_Console_Print_String("]: "); + + for (uint8_t j = 0; j < NVM_OnChipEEPROMEntries[i]->Size; j++) + { + char8 buffer[3]; + + COMM_Console_ByteToHex(buffer, *(NVM_OnChipEEPROMEntries[i]->Value + j)); + COMM_Console_Print_String("0x"); + COMM_Console_Print_String(buffer); + COMM_Console_Print_String(" "); + } + COMM_Console_Print_String("\n"); + } + } + else if ((data[4] == 'n') && (data[5] == 'a') && (data[6] == 'm') && (data[7] == 'e') && (data[8] == 's')) + { + COMM_Console_Print_String("Valid NVM parameters:\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String(" test_1\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String(" test_2\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String(" volume\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + } + else if ((data[4] == 'g') && (data[5] == 'e') && (data[6] == 't') && (data[7] == ' ')) + { + if (strncmp(&data[8], "volume", 6) == 0) + { + COMM_Console_Print_String("Volume: "); + COMM_Console_Print_UInt8(NVM_VOLUME); + COMM_Console_Print_String("\n"); + } + else if (strncmp(&data[8], "test_1", 6) == 0) + { + COMM_Console_Print_String("Test 1: "); + COMM_Console_Print_UInt16(NVM_ONCHIP_TEST_1); + COMM_Console_Print_String("\n"); + } + else if (strncmp(&data[8], "test_2", 6) == 0) + { + COMM_Console_Print_String("Test 2: "); + COMM_Console_Print_UInt32(NVM_ONCHIP_TEST_2); + COMM_Console_Print_String("\n"); + } + else if (strncmp(&data[8], "test_3", 6) == 0) + { + COMM_Console_Print_String("Test 3: "); + COMM_Console_Print_UInt16(NVM_EXTERNAL_TEST_3); + COMM_Console_Print_String("\n"); + } + else if (strncmp(&data[8], "test_4", 6) == 0) + { + COMM_Console_Print_String("Test 4: "); + COMM_Console_Print_UInt32(NVM_EXTERNAL_TEST_4); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Unknown NVM parameter!\n"); + } + } + else if ((data[4] == 's') && (data[5] == 'e') && (data[6] == 't') && (data[7] == ' ')) + { + if (strncmp(&data[8], "volume", 6) == 0) + { + uint8_t volume = 0; + if (COMM_Console_DecodeParameterUInt8(&(data[15]), &volume) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_VOLUME = volume; + NVM_SaveExternalEEPROMEntry(NVM_VOLUME_ENTRY_PTR); + + COMM_Console_Print_String("Volume changed to "); + COMM_Console_Print_UInt8(NVM_VOLUME); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else if (strncmp(&data[8], "test_1", 6) == 0) + { + uint16_t test_value = 0; + if (COMM_Console_DecodeParameterUInt16(&(data[15]), &test_value) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_ONCHIP_TEST_1 = test_value; + NVM_SaveOnChipEEPROMEntry(NVM_ONCHIP_TEST_1_ENTRY_PTR); + + COMM_Console_Print_String("Test 1 value changed to "); + COMM_Console_Print_UInt16(NVM_ONCHIP_TEST_1); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else if (strncmp(&data[8], "test_2", 6) == 0) + { + uint32_t test_value = 0; + if (COMM_Console_DecodeParameterUInt32(&(data[15]), &test_value) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_ONCHIP_TEST_2 = test_value; + NVM_SaveOnChipEEPROMEntry(NVM_ONCHIP_TEST_2_ENTRY_PTR); + + COMM_Console_Print_String("Test 2 value changed to "); + COMM_Console_Print_UInt32(NVM_ONCHIP_TEST_2); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else if (strncmp(&data[8], "test_3", 6) == 0) + { + uint16_t test_value = 0; + if (COMM_Console_DecodeParameterUInt16(&(data[15]), &test_value) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_EXTERNAL_TEST_3 = test_value; + NVM_SaveExternalEEPROMEntry(NVM_EXTERNAL_TEST_3_ENTRY_PTR); + + COMM_Console_Print_String("Test 3 value changed to "); + COMM_Console_Print_UInt16(NVM_EXTERNAL_TEST_3); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else if (strncmp(&data[8], "test_4", 6) == 0) + { + uint32_t test_value = 0; + if (COMM_Console_DecodeParameterUInt32(&(data[15]), &test_value) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_EXTERNAL_TEST_4 = test_value; + NVM_SaveExternalEEPROMEntry(NVM_EXTERNAL_TEST_4_ENTRY_PTR); + + COMM_Console_Print_String("Test 4 value changed to "); + COMM_Console_Print_UInt32(NVM_EXTERNAL_TEST_4); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: Unknown NVM parameter!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: Unknown NVM command!\n"); + } + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.h b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.h new file mode 100644 index 0000000..d71ee1a --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file declares the serial console commands for the Nonvolatile Memory. + */ + +#ifndef COMM_NVM_CONSOLECOMMANDS_H +#define COMM_NVM_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Command_Result_T COMM_NVM_HandleConsoleNVMCommand(char8 * data, uint32_t size); + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_NVM_CONSOLECOMMANDS_H diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.c b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.c new file mode 100644 index 0000000..21d457e --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.c @@ -0,0 +1,120 @@ +/** \file + * \brief This file defines the serial console commands for the RTOS package. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ + +/* Public Variables */ + +/* Private Variables */ + +/* Public Functions */ + +/* Private Functions */ + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleVersion(char8 * data, uint32_t size) +{ + COMM_Console_Print_String("PSoC 6 running FreeRTOS "); + + COMM_Console_Print_String(tskKERNEL_VERSION_NUMBER); + +#ifdef NDEBUG + COMM_Console_Print_String(" (Release, compiled "); +#else + COMM_Console_Print_String(" (Debug, compiled "); +#endif // NDEBUG + + COMM_Console_Print_String(__DATE__); + COMM_Console_Print_String(" "); + COMM_Console_Print_String(__TIME__); + COMM_Console_Print_String(").\n"); + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleStack(char8 * data, uint32_t size) +{ + for (uint_fast8_t i = 0; i < CONFIG_N_TASK_HANDLES; i++) + { + TaskStatus_t status; + vTaskGetInfo(*CONFIG_TaskHandles[i], &status, pdTRUE, eInvalid); + COMM_Console_Print_String(status.pcTaskName); + COMM_Console_Print_String(": "); + COMM_Console_Print_UInt16(status.usStackHighWaterMark); + COMM_Console_Print_String("\n"); + } + + // Repeat for the Idle Task. + { + TaskStatus_t status; + vTaskGetInfo(xTaskGetIdleTaskHandle(), &status, pdTRUE, eInvalid); + COMM_Console_Print_String(status.pcTaskName); + COMM_Console_Print_String(": "); + COMM_Console_Print_UInt16(status.usStackHighWaterMark); + COMM_Console_Print_String("\n"); + } + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleCPU(char8 * data, uint32_t size) +{ + // data[0] through data[3] is 'cpu '. + if (data[4] == 'r') + { + //COMM_Console_Print_String("Max CPU reset.\n"); + COMM_Console_Print_String("(Not yet implemented.)\n"); + } + else + { + for (uint_fast8_t i = 0; i < CONFIG_N_TASK_HANDLES; i++) + { + TaskStatus_t status; + vTaskGetInfo(*CONFIG_TaskHandles[i], &status, pdTRUE, eInvalid); + COMM_Console_Print_String(status.pcTaskName); + COMM_Console_Print_String(": "); + COMM_Console_Print_UInt32(status.ulRunTimeCounter); + COMM_Console_Print_String("\n"); + } + + // Repeat for the Idle Task. + { + TaskStatus_t status; + vTaskGetInfo(xTaskGetIdleTaskHandle(), &status, pdTRUE, eInvalid); + COMM_Console_Print_String(status.pcTaskName); + COMM_Console_Print_String(": "); + COMM_Console_Print_UInt16(status.ulRunTimeCounter); + COMM_Console_Print_String("\n"); + } + } + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleReboot(char8 * data, uint32_t size) +{ + (void) COMM_SendMessageToOtherCore(COMM_SMM_RebootImmediately, NULL); + + // Not that it matters... + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleReprogram(char8 * data, uint32_t size) +{ + COMM_Console_Print_String("Entering bootloader for BLE reprogramming.\n"); + vTaskDelay(pdMS_TO_TICKS(100)); + + Cy_DFU_ExecuteApp(0u); + + // Not that it matters... + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.h b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.h new file mode 100644 index 0000000..ac65346 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.h @@ -0,0 +1,33 @@ +/** \file + * \brief This file declares the serial console commands for the RTOS package. + */ + +#ifndef COMM_RTOS_CONSOLECOMMANDS_H +#define COMM_RTOS_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleVersion(char8 * data, uint32_t size); +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleStack(char8 * data, uint32_t size); +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleCPU(char8 * data, uint32_t size); +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleReboot(char8 * data, uint32_t size); +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleReprogram(char8 * data, uint32_t size); + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_RTOS_CONSOLECOMMANDS_H \ No newline at end of file diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.c b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.c new file mode 100644 index 0000000..83d8bcf --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.c @@ -0,0 +1,189 @@ +/** \file + * \brief This file defines the serial console commands for the high-level state machine. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ +static void Simulate_Hit(uint8_t team_ID, uint16_t damage); + +/* Public Variables */ + +/* Private Variables */ + +/* Public Functions */ + +//! Console command handler for the 'event' command. +COMM_Console_Command_Result_T COMM_HandleEventCommand(char8 * data, uint32_t size) +{ + // data[0] through data[5] is 'event '. + + if (data[6] == '?') + { + COMM_Console_Print_String("event ? Display this help.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("event raw Inject the event with ID .\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("event tag Send tag(s).\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("event hit Simulate a hit from team for damage.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + } + else if ( (data[6] == 'r') && + (data[7] == 'a') && + (data[8] == 'w') ) + + { + if (COMM_Console_IsEndOfMessage(data[9])) + { + COMM_Console_Print_String("ERROR: missing event ID!\n"); + } + else if (data[9] == ' ') + { + uint16_t id = 0; + + if (COMM_Console_DecodeParameterUInt16(&(data[10]), &id) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + if ((id > KEVENT_NO_EVENT) && (id < KEVENT_IS_OUT_OF_RANGE)) + { + KEvent_T raw_event = { .ID = id, .Data = (void *)0x00 }; + Post_KEvent(&raw_event); + } + else + { + COMM_Console_Print_String("ERROR: specified event ID ("); + COMM_Console_Print_UInt16(id); + COMM_Console_Print_String(") is invalid!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: could not comprehend event ID!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: unrecognized or mangled command!\n"); + } + } + else if ( (data[6] == 't') && + (data[7] == 'a') && + (data[8] == 'g') ) + + { + if (COMM_Console_IsEndOfMessage(data[9])) + { + if (Send_Tag() == SYSTEMK_RESULT_SUCCESS) + { + COMM_Console_Print_String("Tag sent.\n"); + } + else + { + COMM_Console_Print_String("Error: Couldn't send tag!\n"); + } + } + else if (data[9] == ' ') + { + uint16_t times = 0; + + if (COMM_Console_DecodeParameterUInt16(&(data[10]), ×) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + while (times > 0) + { + if (Send_Tag() == SYSTEMK_RESULT_SUCCESS) + { + COMM_Console_Print_String("Tag sent.\n"); + } + else + { + COMM_Console_Print_String("Error: Couldn't send tag!\n"); + } + //! \todo Why can't the console command 'event tag ' send tags faster than once per second? + vTaskDelay(1000 / portTICK_PERIOD_MS); + times--; + } + } + else + { + COMM_Console_Print_String("ERROR: could not comprehend tag repetitions!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: unrecognized or mangled command!\n"); + } + } + else if ( (data[6] == 'h') && + (data[7] == 'i') && + (data[8] == 't') ) + + { + if (COMM_Console_IsEndOfMessage(data[9])) + { + Simulate_Hit(1, 10); + COMM_Console_Print_String("Hit!\n"); + } + else if (data[9] == ' ') + { + uint8_t team_ID = 0; + uint16_t damage = 10; + + if (COMM_Console_DecodeParameterUInt8(&(data[10]), &team_ID) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + const char * damage_location; + + // Damage is the first parameter after team ID. + if (COMM_Console_FindNthParameter(&(data[10]), 1, &damage_location) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + if (COMM_Console_DecodeParameterUInt16(damage_location, &damage) != COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + COMM_Console_Print_String("ERROR: could not comprehend damage--using default.\n"); + damage = 10; + } + } + Simulate_Hit(team_ID, damage); + COMM_Console_Print_String("Hit!\n"); + } + else + { + COMM_Console_Print_String("ERROR: could not comprehend team ID!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: unrecognized or mangled command!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: Unknown event command!\n"); + } + + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +/* Private Functions */ + +static void Simulate_Hit(uint8_t team_ID, uint16_t damage) +{ + static DecodedPacket_T Simulated_Tag_Rx_Buffer; + static KEvent_T tag_received_event; + + Simulated_Tag_Rx_Buffer.Tag.type = DECODED_PACKET_TYPE_TAG_RECEIVED; + Simulated_Tag_Rx_Buffer.Tag.protocol = LASER_X_PROTOCOL; + Simulated_Tag_Rx_Buffer.Tag.player_ID = 0x00; + Simulated_Tag_Rx_Buffer.Tag.team_ID = team_ID; + Simulated_Tag_Rx_Buffer.Tag.damage = damage; + Simulated_Tag_Rx_Buffer.Tag.color = GetColorFromTeamID(team_ID); + tag_received_event.ID = KEVENT_TAG_RECEIVED; + tag_received_event.Data = &Simulated_Tag_Rx_Buffer; + Post_KEvent(&tag_received_event); +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.h b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.h new file mode 100644 index 0000000..0c29268 --- /dev/null +++ b/2020TPCApp1.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file declares the serial console commands for the high-level state machine. + */ + +#ifndef COMM_STATE_CONSOLECOMMANDS_H +#define COMM_STATE_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Command_Result_T COMM_HandleEventCommand(char8 * data, uint32_t size); + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_STATE_CONSOLECOMMANDS_H diff --git a/2020TPCApp1.cydsn/CONFIG/CONFIG.h b/2020TPCApp1.cydsn/CONFIG/CONFIG.h new file mode 100644 index 0000000..5ec88f7 --- /dev/null +++ b/2020TPCApp1.cydsn/CONFIG/CONFIG.h @@ -0,0 +1,83 @@ +/** \dir "CONFIG" + * + * \brief This directory contains configuration files for this software. + * + */ + +/** \file + * \brief This file includes project-wide for this software. + * + * This file should be included by every file outside the CONFIG package! + * + * \note As always, should be included before this file. + */ + +#ifndef CONFIG_H +#define CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "CONFIG_RTOS.h" + +//! Value of audio volume represeting the maximum volume possible for this device. +#define CONFIG_KTAG_MAX_AUDIO_VOLUME 30 + +//! Value of audio volume represeting the minimum volume possible for this device. +#define CONFIG_KTAG_MIN_AUDIO_VOLUME 5 + +//! Time (in milliseconds) after starting a game before the countdown begins. +#define CONFIG_KTAG_T_DEFAULT_START_GAME_in_ms (30 * 1000) + +//! true if the hardware includes internal (on-chip) NVM. +#define CONFIG__HAS_INTERNAL_NVM true + +//! true if the hardware includes an external (I2C) NVM chip. +#define CONFIG__HAS_EXTERNAL_NVM true + +// '||' || '|| '||''|. TM +// || ... || || || ... .. ... ... .... ... +// || || || ||'''|. ||' '' || || '|. | +// || || || || || || || || '|.| +// .||.....| .||. .||. .||...|' .||. '|..'|. '| + +#if (defined LIL_BRUV) || (defined LITTLE_BOY_BLUE) + +//! Number of NeoPixel channels supported. +#define CONFIG_KTAG_N_NEOPIXEL_CHANNELS 1 + +//! Maximum number of NeoPixels on a single channel. +#define CONFIG_KTAG_MAX_NEOPIXELS_PER_CHANNEL 5 + + + +// /\ /\\ /\ /\\ TM +// ( ) || || ( ) || || |''||''| '||''|. ..|'''.| +// // || || // || || || || || .|' ' +// // || || // || || || ||...|' || +// /( || || /( || || || || '|. . +// {___ \\/ {___ \\/ .||. .||. ''|....' + +#elif (defined TWENTY20TPC) + +//! Number of NeoPixel channels supported. +#define CONFIG_KTAG_N_NEOPIXEL_CHANNELS 4 + +//! Maximum number of NeoPixels on a single channel. +#define CONFIG_KTAG_MAX_NEOPIXELS_PER_CHANNEL 8 + + + +#else + #error "No recognized KTag models defined. Supported models are: LIL_BRUV, LITTLE_BOY_BLUE, and TWENTY20TPC." +#endif + +//! Time between NeoPixel animation frames, in milliseconds. +#define CONFIG_KTAG_ANIMATION_STEP_TIME_IN_ms 10 + +#ifdef __cplusplus +} +#endif + +#endif // CONFIG_H diff --git a/2020TPCApp1.cydsn/CONFIG/CONFIG_RTOS.c b/2020TPCApp1.cydsn/CONFIG/CONFIG_RTOS.c new file mode 100644 index 0000000..9c97c6c --- /dev/null +++ b/2020TPCApp1.cydsn/CONFIG/CONFIG_RTOS.c @@ -0,0 +1,113 @@ +/** \file + * \brief This file defines and registers the tasks used by the Real-Time Operating System. + * + * See CONFIG_RTOS.h for a detailed description of the functionality implemented by this code. + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/*---------------------------------------------------------------------------*/ +/* Task priorities: Low priority numbers denote low priority tasks. + * + * Low == 0 == tskIDLE_PRIORITY + * ... + * High == (configMAX_PRIORITIES - 1) + * + * See http://www.freertos.org/RTOS-task-priority.html for more information. + */ +#define CAPSENSE_TASK_PRIORITY (tskIDLE_PRIORITY + 3) +#define SAMPLE_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define FIRE_CONTROL_TASK_PRIORITY (tskIDLE_PRIORITY + 1) +#define AUDIO_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define NEOPIXELS_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define TAG_SENSORS_TASK_PRIORITY (tskIDLE_PRIORITY + 5) +#define SWITCHES_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define NVM_EXTERNAL_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define NVM_ON_CHIP_EEPROM_TASK_PRIORITY (tskIDLE_PRIORITY + 1) +#define COMM_CONSOLE_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define COMM_BLE_TASK_PRIORITY (tskIDLE_PRIORITY + 4) + + +/* External Variables [Only if necessary!] */ + +/* External Function Prototypes [Only if necessary!] */ + +/* Public Variables */ + +//! Array of all the handles for the configured RTOS tasks. +TaskHandle_t * const CONFIG_TaskHandles[] = {&HW_CapSense_Task_Handle, + &Fire_Control_Task_Handle, + &Sample_Task_Handle, + &Audio_Task_Handle, + &NeoPixels_Task_Handle, + &Tag_Sensors_Task_Handle, + &Switches_Task_Handle, + &State_Machine_Task_Handle, + &NVM_ExternalEEPROM_Task_Handle, + &NVM_OnChipEEPROM_Task_Handle, + &COMM_Console_Task_Handle, + &COMM_BLE_Task_Handle}; + +//! Size of the #CONFIG_TaskHandles array (i.e. the number of configured tasks). +const uint8_t CONFIG_N_TASK_HANDLES = (uint8_t) (sizeof(CONFIG_TaskHandles) / sizeof(TaskHandle_t *)); + +/* Private Variables */ + +/* Private Function Prototypes */ + +/* Public Functions */ + +void CONFIG_InitTasks(void) +{ + HW_CapSense_Init(); + COMM_I2C_Init(); + NVM_InitExternalEEPROM(); + NVM_InitOnChipEEPROM(); + Sample_Task_Init(); + Init_Fire_Control(); + Tag_Sensors_Init(); + Init_Audio(); + Switches_Init(); + COMM_Console_Init(); + COMM_BLE_Init(); +} + +//! Registers tasks with the kernel, and then runs them. +/*! + * This function should not return. +*/ +void CONFIG_RunTasks(void) +{ + (void) xTaskCreate(HW_CapSense_Task, "CapSense Task", HW_CAPSENSE_TASK_STACK_SIZE_in_bytes, NULL, CAPSENSE_TASK_PRIORITY, &HW_CapSense_Task_Handle); + (void) xTaskCreate(Fire_Control_Task, "Fire Control Task", configMINIMAL_STACK_SIZE, NULL, FIRE_CONTROL_TASK_PRIORITY, &Fire_Control_Task_Handle); + (void) xTaskCreate(Sample_Task, "Sample Task", configMINIMAL_STACK_SIZE, NULL, SAMPLE_TASK_PRIORITY, &Sample_Task_Handle); + (void) xTaskCreate(Audio_Task, "Audio Task", configMINIMAL_STACK_SIZE, NULL, AUDIO_TASK_PRIORITY, &Audio_Task_Handle); + (void) xTaskCreate(NeoPixels_Task, "NeoPixels Task", configMINIMAL_STACK_SIZE, NULL, NEOPIXELS_TASK_PRIORITY, &NeoPixels_Task_Handle); + (void) xTaskCreate(Tag_Sensors_Task, "Tag Sensors Task", configMINIMAL_STACK_SIZE, NULL, TAG_SENSORS_TASK_PRIORITY, &Tag_Sensors_Task_Handle); + (void) xTaskCreate(Switches_Task, "Switches Task", configMINIMAL_STACK_SIZE, NULL, SWITCHES_TASK_PRIORITY, &Switches_Task_Handle); + (void) xTaskCreate(NVM_OnChipEEPROMTask, "NVMOn", NVM_ON_CHIP_EEPROM_TASK_STACK_SIZE_in_bytes, NULL, NVM_ON_CHIP_EEPROM_TASK_PRIORITY, &NVM_OnChipEEPROM_Task_Handle); + (void) xTaskCreate(NVM_ExternalEEPROMTask, "NVMEx", NVM_EXTERNAL_EEPROM_TASK_STACK_SIZE_in_bytes, NULL, NVM_EXTERNAL_TASK_PRIORITY, &NVM_ExternalEEPROM_Task_Handle); + (void) xTaskCreate(COMM_Console_Task, "Console Task", COMM_CONSOLE_TASK_STACK_SIZE_in_bytes, NULL, COMM_CONSOLE_TASK_PRIORITY, &COMM_Console_Task_Handle); + (void) xTaskCreate(COMM_BLE_Task, "BLE Task", COMM_BLE_TASK_STACK_SIZE_in_bytes, NULL, COMM_BLE_TASK_PRIORITY, &COMM_BLE_Task_Handle); + + if (Initialize_SystemK() != SYSTEMK_RESULT_SUCCESS) + { + KLOG_ERROR("CONFIG", "Failed to initilaize SystemK!"); + } + + /* This should not return. */ + vTaskStartScheduler(); + + // Something went wrong. +#ifdef DEBUG + // Break into the debugger. + __BKPT(0); +#else // DEBUG + __NVIC_SystemReset(); +#endif // DEBUG +} + +/* Private Functions */ diff --git a/2020TPCApp1.cydsn/CONFIG/CONFIG_RTOS.h b/2020TPCApp1.cydsn/CONFIG/CONFIG_RTOS.h new file mode 100644 index 0000000..26709c3 --- /dev/null +++ b/2020TPCApp1.cydsn/CONFIG/CONFIG_RTOS.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file configures the Real-Time Operating System (RTOS). + */ + +#ifndef CONFIG_RTOS_H +#define CONFIG_RTOS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +extern TaskHandle_t * const CONFIG_TaskHandles[]; +extern const uint8_t CONFIG_N_TASK_HANDLES; + +/* Public Functions */ +void CONFIG_InitTasks(void); +void CONFIG_RunTasks(void); + +#ifdef __cplusplus +} +#endif + +#endif // CONFIG_RTOS_H diff --git a/2020TPCApp1.cydsn/Fire_Control.c b/2020TPCApp1.cydsn/Fire_Control.c new file mode 100644 index 0000000..6033112 --- /dev/null +++ b/2020TPCApp1.cydsn/Fire_Control.c @@ -0,0 +1,223 @@ +/* Include Files */ +#include "KTag.h" + +#define FIRE_CONTROL_REGISTER__IR_OFF 0b00000 +#define FIRE_CONTROL_REGISTER__IR_ON_MODULATED_LOW_POWER 0b00011 +#define FIRE_CONTROL_REGISTER__IR_ON_MODULATED_HIGH_POWER 0b00101 +#define FIRE_CONTROL_REGISTER__IR_ON_MODULATED_MAX_POWER 0b11111 +#define FIRE_CONTROL_REGISTER__IR_ON_UNMODULATED_LOW_POWER 0b00010 +#define FIRE_CONTROL_REGISTER__IR_ON_UNMODULATED_HIGH_POWER 0b00100 +#define FIRE_CONTROL_REGISTER__IR_ON_UNMODULATED_MAX_POWER 0b00110 + +#define TRIGGER_STATUS_REGISTER__NO_ACTION 0x00 +#define TRIGGER_STATUS_REGISTER__TRIGGER_PULLED 0x01 +#define TRIGGER_STATUS_REGISTER__TRIGGER_RELEASED 0x02 + + +void Trigger_Interrupt_ISR(); +void Bit_Stream_Timer_ISR(); + +TimedPulseTrain_T * Shot_Buffer; +TagPacket_T Shot_Packet; + +TaskHandle_t Fire_Control_Task_Handle; + +static TimedPulseTrain_T * Active_Pulse_Train = NULL; +static uint8_t Active_Bitstream_Index = 0; + +static TickType_t TicksAtTriggerPress; + +static inline void Initiate_Pulse_Train(TimedPulseTrain_T * pulsetrain) +{ + Bit_Stream_Timer_Disable(); + Active_Pulse_Train = pulsetrain; + Active_Bitstream_Index = 0; + + if (Active_Pulse_Train->bitstream[Active_Bitstream_Index].symbol == MARK) + { + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_ON_MODULATED_MAX_POWER); + } + else + { + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); + } + Bit_Stream_Timer_SetPeriod(Active_Pulse_Train->bitstream[0].duration); + Bit_Stream_Timer_SetCounter(0); + Active_Bitstream_Index++; + Bit_Stream_Timer_Enable(); + Bit_Stream_Timer_TriggerStart(); +} + +static inline void Next_Bit(void) +{ + static BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + Bit_Stream_Timer_Disable(); + + if (Active_Pulse_Train->bitstream[Active_Bitstream_Index].duration != LAST_PULSE) + { + if (Active_Pulse_Train->bitstream[Active_Bitstream_Index].symbol == MARK) + { + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_ON_MODULATED_MAX_POWER); + } + else + { + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); + } + + if (Active_Bitstream_Index < ((2*MAX_PULSES) - 2)) + { + Bit_Stream_Timer_SetPeriod(Active_Pulse_Train->bitstream[Active_Bitstream_Index].duration); + Bit_Stream_Timer_SetCounter(0); + Active_Bitstream_Index++; + Bit_Stream_Timer_Enable(); + Bit_Stream_Timer_TriggerStart(); + } + else + { + // The bitstream is too long! + + // Turn the IR Emitter off, and wait a long time. + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); + xSemaphoreGiveFromISR(NeoPixels_Semaphore, &xHigherPriorityTaskWoken); + Bit_Stream_Timer_SetPeriod(UINT16_MAX); + Bit_Stream_Timer_SetCounter(0); + Active_Pulse_Train = NULL; + Bit_Stream_Timer_Enable(); + Bit_Stream_Timer_TriggerStart(); + } + } + else + { + // Turn the IR Emitter off, and wait a long time. + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); + xSemaphoreGiveFromISR(NeoPixels_Semaphore, &xHigherPriorityTaskWoken); + Bit_Stream_Timer_SetPeriod(UINT16_MAX); + Bit_Stream_Timer_SetCounter(0); + Active_Pulse_Train = NULL; + Bit_Stream_Timer_Enable(); + Bit_Stream_Timer_TriggerStart(); + } + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + +void Init_Fire_Control(void) +{ + // Register and enable the ISRs. + Cy_SysInt_Init(&Trigger_Interrupt_cfg, Trigger_Interrupt_ISR); + Cy_SysInt_Init(&Bit_Stream_Timer_Interrupt_cfg, Bit_Stream_Timer_ISR); + NVIC_EnableIRQ(Trigger_Interrupt_cfg.intrSrc); + NVIC_EnableIRQ(Bit_Stream_Timer_Interrupt_cfg.intrSrc); + + // Initialize the hardware. + Bit_Stream_Timer_Clock_Enable(); + Bit_Stream_Timer_Init(&Bit_Stream_Timer_config); + Bit_Stream_Timer_SetPeriod(2); + Bit_Stream_Timer_Start(); + SW_CLK_Enable(); + PWM_IR_Modulation_Start(); + + + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); +} + +void Fire_Control_Task(void * pvParameters) +{ + while (true) + { + vTaskDelay(1000 / portTICK_PERIOD_MS); + } +} + +SystemKResult_T Prepare_Tag() +{ + Shot_Packet.player_ID = NVM_PLAYER_ID; + Shot_Packet.team_ID = NVM_TEAM_ID; + Weapon_t weapon = GetWeaponFromID(NVM_WEAPON_ID); + Shot_Packet.color = (uint32_t)PROTOCOLS_GetColor(weapon.Protocol, Shot_Packet.team_ID, Shot_Packet.player_ID); + Shot_Packet.protocol = weapon.Protocol; + Shot_Packet.damage = weapon.Damage_Per_Shot; + Shot_Buffer = PROTOCOLS_EncodePacket(&Shot_Packet); + Fire_Control_Set_Modulation_Frequency(PROTOCOLS_GetModulationFrequency(weapon.Protocol)); + return SYSTEMK_RESULT_SUCCESS; +} + +SystemKResult_T Send_Tag() +{ + xSemaphoreTake(NeoPixels_Semaphore, portMAX_DELAY); + Initiate_Pulse_Train(Shot_Buffer); + + KEvent_T tag_sent_event = { .ID = KEVENT_TAG_SENT, .Data = (void *)0x00 }; + Post_KEvent(&tag_sent_event); + + return SYSTEMK_RESULT_SUCCESS; +} + +void Fire_Control_Set_Modulation_Frequency(ModulationFrequency_T freq) +{ + PWM_IR_Modulation_TriggerKill(); + if (freq == FREQUENCY_38kHz) + { + PWM_IR_Modulation_SetPeriod0(314); + //PWM_IR_Modulation_SetCompare0(314/2); // 50% Duty Cycle + PWM_IR_Modulation_SetCompare0((314 * 3)/10); // 30% Duty Cycle + } + else // (freq == FREQUENCY_56kHz) + { + PWM_IR_Modulation_SetPeriod0(213); + //PWM_IR_Modulation_SetCompare0(213/2); // 50% Duty Cycle + PWM_IR_Modulation_SetCompare0((213 * 3)/10); // 30% Duty Cycle + } + PWM_IR_Modulation_TriggerStart(); +} + +//! ISR for the trigger input. +void Trigger_Interrupt_ISR() +{ + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + // Clear the interrupt. + NVIC_ClearPendingIRQ(Trigger_Interrupt_cfg.intrSrc); + + // Read the trigger register to know if this was a pull or a release. + uint8_t trigger_status = Trigger_Status_Reg_Read(); + + if ((trigger_status & TRIGGER_STATUS_REGISTER__TRIGGER_PULLED) == TRIGGER_STATUS_REGISTER__TRIGGER_PULLED) + { + TicksAtTriggerPress = xTaskGetTickCountFromISR(); + KEvent_T switch_event = {.ID = KEVENT_CENTER_SWITCH_PRESSED, .Data = NULL}; + Post_KEvent_From_ISR(&switch_event, &xHigherPriorityTaskWoken); + } + else if ((trigger_status & TRIGGER_STATUS_REGISTER__TRIGGER_RELEASED) == TRIGGER_STATUS_REGISTER__TRIGGER_RELEASED) + { + uint32_t triggerPressDurationInms = pdTICKS_TO_MS(xTaskGetTickCountFromISR() - TicksAtTriggerPress); + KEvent_T switch_event = {.ID = KEVENT_CENTER_SWITCH_RELEASED, .Data = (void *) triggerPressDurationInms}; + Post_KEvent_From_ISR(&switch_event, &xHigherPriorityTaskWoken); + } + else + { + // What happened!!? + } + + // If an event was enqueued above, a context switch might be required. + // xHigherPriorityTaskWoken was initialized to pdFALSE on interrupt entry. If calling + // xSemaphoreGiveFromISR() caused a task to unblock, and the unblocked task has a + // priority equal to or higher than the currently running task (the task that was + // interrupted by this ISR), then xHigherPriorityTaskWoken will have been set to pdTRUE + // and portEND_SWITCHING_ISR() will request a context switch to the newly unblocked task. + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} + +void Bit_Stream_Timer_ISR() +{ + // Get all the enabled pending interrupts... + uint32_t source = Bit_Stream_Timer_GetInterruptStatusMasked(); + // ...and clear them. + Bit_Stream_Timer_ClearInterrupt(source); + + if (Active_Pulse_Train != NULL) + { + Next_Bit(); + } +} diff --git a/2020TPCApp1.cydsn/Fire_Control.h b/2020TPCApp1.cydsn/Fire_Control.h new file mode 100644 index 0000000..bcf8e72 --- /dev/null +++ b/2020TPCApp1.cydsn/Fire_Control.h @@ -0,0 +1,13 @@ +#ifndef FIRE_CONTROL_H +#define FIRE_CONTROL_H + +#include +#include + +extern TaskHandle_t Fire_Control_Task_Handle; + +void Init_Fire_Control(void); +void Fire_Control_Task(void * pvParameters); +void Fire_Control_Set_Modulation_Frequency(ModulationFrequency_T freq); + +#endif // FIRE_CONTROL_H diff --git a/2020TPCApp1.cydsn/FreeRTOSConfig.h b/2020TPCApp1.cydsn/FreeRTOSConfig.h new file mode 100644 index 0000000..ff41915 --- /dev/null +++ b/2020TPCApp1.cydsn/FreeRTOSConfig.h @@ -0,0 +1,228 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#include "syslib/cy_syslib.h" + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ 1000u +#define configMAX_PRIORITIES 15 +#define configMINIMAL_STACK_SIZE 512 +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 10 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE (64*1024) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 1 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + + +//! Debug Exception and Monitor Control register +#define CORE_DBG_EXC_MON_CTL (*(uint32_t *)0xE000EDFC) + +//! DWT Control Register +#define DWT_CTRL (*(uint32_t *)0xE0001000) + +//! DWT Current PC Sampler Cycle Count Register +/*! + * Use the DWT Current PC Sampler Cycle Count Register to count the number of core cycles. This + * count can measure elapsed execution time. + */ +#define DWT_CYCCNT (*(uint32_t *)0xE0001004) + +//! Initializes the Data Watchpoint and Trace Unit and starts the CYCCNT counter. +static inline void vCONFIGURE_TIMER_FOR_RUN_TIME_STATS(void) +{ + // If the Data Watchpoint and Trace Unit is present, #DWT_CTRL will be non-zero. + if (DWT_CTRL != 0) + { + // Set bit 24 (TRCENA) on the CORE_DBG_EXC_MON_CTL register to enable use of the DWT. + CORE_DBG_EXC_MON_CTL |= (1 << 24); + // Initialize the count register. + DWT_CYCCNT = 0; + // Set bit 0 (CYCCNTENA) on the DWT_CTRL register to enable the CYCCNT counter. + DWT_CTRL |= (1 << 0); + } +} + +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS vCONFIGURE_TIMER_FOR_RUN_TIME_STATS + +//! Returns the current value of the DWT Current PC Sampler Cycle Count Register +/*! + * Use the DWT Current PC Sampler Cycle Count Register to count the number of core cycles. This + * count can measure elapsed execution time. + */ +static inline uint32_t ulGET_RUN_TIME_COUNTER_VALUE(void) +{ + return DWT_CYCCNT; +} + +#define portGET_RUN_TIME_COUNTER_VALUE ulGET_RUN_TIME_COUNTER_VALUE + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 3 +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* FreeRTOS MPU specific definitions. */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 + +/* +Interrupt nesting behavior configuration. +This is explained here: http://www.freertos.org/a00110.html + +Priorities are controlled by two macros: +- configKERNEL_INTERRUPT_PRIORITY determines the priority of the RTOS daemon task +- configMAX_API_CALL_INTERRUPT_PRIORITY dictates the priority of ISRs that make API calls + +Notes: +1. Interrupts that do not call API functions should be >= configKERNEL_INTERRUPT_PRIORITY + and will nest. +2. Interrupts that call API functions must have priority between KERNEL_INTERRUPT_PRIORITY + and MAX_API_CALL_INTERRUPT_PRIORITY (inclusive). +3. Interrupts running above MAX_API_CALL_INTERRUPT_PRIORITY are never delayed by the OS. +*/ +/* +PSoC 6 __NVIC_PRIO_BITS = 3 + +0 (high) +1 MAX_API_CALL_INTERRUPT_PRIORITY 001xxxxx (0x3F) +2 +3 +4 +5 +6 +7 (low) KERNEL_INTERRUPT_PRIORITY 111xxxxx (0xFF) + +!!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + +If you call a FreeRTOS API function from an interrupt with priority higher than +MAX_API_CALL_INTERRUPT_PRIORITY FreeRTOS will generate an exception. If you need +to call a FreeRTOS API function from your system’s highest priority interrupt +you must reduce all interrupt priorities to MAX_API_CALL_INTERRUPT_PRIORITY or +lower. + +If your system pipe (IPC) interrupt priority is less than or equal to +MAX_API_CALL_INTERRUPT_PRIORITY then care must be taken with code that writes to +flash (including the Flash/BLE/Emulated EEPROM/Bootloader drivers from Cypress +PDL). The duration of critical sections must be kept short - see the +Configuration Considerations section of the flash driver in the PDL API +Reference. + +*/ + +/* Put KERNEL_INTERRUPT_PRIORITY in top __NVIC_PRIO_BITS bits of CM4 register */ +#define configKERNEL_INTERRUPT_PRIORITY 0xFF +/* +Put MAX_SYSCALL_INTERRUPT_PRIORITY in top __NVIC_PRIO_BITS bits of CM4 register +NOTE For IAR compiler make sure that changes of this macro is reflected in +file portable\IAR\CM4F\portasm.s in PendSV_Handler: routine +*/ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0x3F +/* configMAX_API_CALL_INTERRUPT_PRIORITY is a new name for configMAX_SYSCALL_INTERRUPT_PRIORITY + that is used by newer ports only. The two are equivalent. */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY configMAX_SYSCALL_INTERRUPT_PRIORITY + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xEventGroupSetBitFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 0 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names - or at least those used in the unmodified vector table. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/2020TPCApp1.cydsn/HW/HW.h b/2020TPCApp1.cydsn/HW/HW.h new file mode 100644 index 0000000..0a27ecd --- /dev/null +++ b/2020TPCApp1.cydsn/HW/HW.h @@ -0,0 +1,50 @@ +/** \dir "HW" + * + * \brief This directory contains source code interfacing to the lowest level of the hardware on this CPU. + * + */ + +/** \file + * \brief This file defines the interface to the low-level hardware used by this software. + * + * This file should be included by any file outside the HW package wishing to make use + * of any of the HW functionality. + * + * \note As always, and should be included before this file. + */ + +#ifndef HW_H +#define HW_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +//! Represents the states of a Digital Input or Digital Output. +typedef enum +{ + //! Represents low voltage (logic '0') on a digital input or output. + HW_DIGITAL_STATE_LOW = 0, + + //! Represents high voltage (logic '1') on a digital input or output. + HW_DIGITAL_STATE_HIGH = 1, + + //! Used when the state of a digital input or output cannot be determined. + HW_DIGITAL_STATE_UNKNOWN = 2 +} HW_DigitalState_T; + +/* Include Files */ + +#include "HW_CapSense.h" + +/* Public Variables */ + +/* Public Functions */ + +#ifdef __cplusplus +} +#endif + +#endif // HW_H diff --git a/2020TPCApp1.cydsn/HW/HW_CapSense.c b/2020TPCApp1.cydsn/HW/HW_CapSense.c new file mode 100644 index 0000000..14db4b5 --- /dev/null +++ b/2020TPCApp1.cydsn/HW/HW_CapSense.c @@ -0,0 +1,125 @@ +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +#define CAPSENSE_TASK_PERIOD_IN_ms 50 + +/* Public Variables */ + +TaskHandle_t HW_CapSense_Task_Handle; + +/* Private Variables */ + +static const TickType_t CapSense_Task_Delay = CAPSENSE_TASK_PERIOD_IN_ms / portTICK_PERIOD_MS; + +static bool CapSense_One_Pressed = false; +static bool CapSense_Two_Pressed = false; + +/* Private Function Prototypes */ + + +/* Public Functions */ + +//! Initializes the capacitive touch sensing. +void HW_CapSense_Init(void) +{ +} + +//! Capacitive touch sensing task: Manages the capsense, using the PSoC API functions. +/*! + * + */ +void HW_CapSense_Task(void * pvParameters) +{ + TickType_t xLastWakeTime; + + // Initialize the xLastWakeTime variable with the current time. + xLastWakeTime = xTaskGetTickCount(); + + // Start up the capsense component, and initiate the first scan. + // Note that this can't be done in HW_CapSense_Init(), since it requires interrupts to be enabled. + CapSense_Start(); + CapSense_ScanAllWidgets(); + + vTaskDelayUntil(&xLastWakeTime, CapSense_Task_Delay); + + while (true) + { + // Check to see if the CapSense hardware is still busy with a previous scan. + if (CapSense_IsBusy() == CapSense_NOT_BUSY) + { + // Process all the widgets and read the touch information. + CapSense_ProcessAllWidgets(); + + // Perform the on-change logic for "Button One". + if (CapSense_IsSensorActive(CapSense_BUTTON0_WDGT_ID, CapSense_BUTTON0_SNS0_ID)) + { + if (CapSense_One_Pressed == false) + { + KEvent_T switch_event = {.ID = KEVENT_CAPSENSE_ONE_PRESSED, .Data = NULL}; + Post_KEvent(&switch_event); + } + CapSense_One_Pressed = true; + } + else + { + if (CapSense_One_Pressed == true) + { + KEvent_T switch_event = {.ID = KEVENT_CAPSENSE_ONE_RELEASED, .Data = NULL}; + Post_KEvent(&switch_event); + } + CapSense_One_Pressed = false; + } + + // Perform the on-change logic for "Button Two". + if (CapSense_IsSensorActive(CapSense_BUTTON0_WDGT_ID, CapSense_BUTTON0_SNS1_ID)) + { + if (CapSense_Two_Pressed == false) + { + KEvent_T switch_event = {.ID = KEVENT_CAPSENSE_TWO_PRESSED, .Data = NULL}; + Post_KEvent(&switch_event); + } + CapSense_Two_Pressed = true; + } + else + { + if (CapSense_Two_Pressed == true) + { + KEvent_T switch_event = {.ID = KEVENT_CAPSENSE_TWO_RELEASED, .Data = NULL}; + Post_KEvent(&switch_event); + } + CapSense_Two_Pressed = false; + } + + // Initiate the next scan. + CapSense_ScanAllWidgets(); + } + + vTaskDelayUntil(&xLastWakeTime, CapSense_Task_Delay); + } +} + +//! Gets the state of the given CapSense button. +/*! + * \param button the button in question + * \return true if the button was pressed last time it was checked; false otherwise + */ +bool HW_IsCapsenseButtonPressed(HW_CapSenseButton_T button) +{ + bool pressed = false; + + if ((button == HW_CAPSENSE_BUTTON_ONE) && (CapSense_One_Pressed == true)) + { + pressed = true; + } + else if ((button == HW_CAPSENSE_BUTTON_TWO) && (CapSense_Two_Pressed == true)) + { + pressed = true; + } + + return pressed; +} + +/* Private Functions */ + diff --git a/2020TPCApp1.cydsn/HW/HW_CapSense.h b/2020TPCApp1.cydsn/HW/HW_CapSense.h new file mode 100644 index 0000000..f357e19 --- /dev/null +++ b/2020TPCApp1.cydsn/HW/HW_CapSense.h @@ -0,0 +1,40 @@ +/** \file + * \brief This file defines the interface to the capacitive touch sensing used by this software. + * + */ + +#ifndef HW_CAPSENSE_H +#define HW_CAPSENSE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +#define HW_CAPSENSE_TASK_STACK_SIZE_in_bytes 128 + +typedef enum +{ + HW_CAPSENSE_BUTTON_ONE, + HW_CAPSENSE_BUTTON_TWO +} HW_CapSenseButton_T; + +/* Include Files */ + +/* Public Variables */ + +//! Handle of the HW_CapSense_Task() given when the task was created. +extern TaskHandle_t HW_CapSense_Task_Handle; + +/* Public Functions */ +void HW_CapSense_Init(void); +void HW_CapSense_Task(void * pvParameters); +bool HW_IsCapsenseButtonPressed(HW_CapSenseButton_T button); + +#ifdef __cplusplus +} +#endif + +#endif // HW_CAPSENSE_H + diff --git a/2020TPCApp1.cydsn/HW/HW_NeoPixels.c b/2020TPCApp1.cydsn/HW/HW_NeoPixels.c new file mode 100644 index 0000000..d732a10 --- /dev/null +++ b/2020TPCApp1.cydsn/HW/HW_NeoPixels.c @@ -0,0 +1,392 @@ +// NeoPixel Driver using Direct Memory Access +// +// This implementation is based on the one by Alan Hawse of Elkhorn Creek, +// documented at https://iotexpert.com/2019/01/08/psoc-6-dma-ws2812-leds/. +// We are grateful to Mr. Hawse for sharing this. + +#include "KTag.h" + +#define NEOPIXEL_ZOFFSET (1) +#define NEOPIXEL_ONE3 (0b110<<24) +#define NEOPIXEL_ZERO3 (0b100<<24) +#define NEOPIXEL_SPI_BIT_PER_BIT (3) +#define NEOPIXEL_COLOR_PER_PIXEL (3) +#define NEOPIXEL_BYTES_PER_PIXEL (NEOPIXEL_SPI_BIT_PER_BIT * NEOPIXEL_COLOR_PER_PIXEL) +#define FRAME_BUFFER_SIZE (NEOPIXEL_ZOFFSET + (CONFIG_KTAG_MAX_NEOPIXELS_PER_CHANNEL * NEOPIXEL_BYTES_PER_PIXEL)) + +#if (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 1) + static uint8_t NeoPixel_Barrel_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; +#elif (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 4) + static uint8_t NeoPixel_Barrel_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; + static uint8_t NeoPixel_Receiver_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; + static uint8_t NeoPixel_Display_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; + static uint8_t NeoPixel_Effects_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; +#else + #error "Unsupported number of NeoPixel channels defined. Supported configurations are 1 and 4." +#endif + +static uint8_t* NeoPixel_Frame_Buffers[CONFIG_KTAG_N_NEOPIXEL_CHANNELS] = +{ +#if (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 1) + NeoPixel_Barrel_Channel_Frame_Buffer +#elif (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 4) + NeoPixel_Barrel_Channel_Frame_Buffer, + NeoPixel_Receiver_Channel_Frame_Buffer, + NeoPixel_Display_Channel_Frame_Buffer, + NeoPixel_Effects_Channel_Frame_Buffer +#else + #error "Unsupported number of NeoPixel channels defined. Supported configurations are 1 and 4." +#endif +}; + +ColorOrder_T ColorOrderByChannel[CONFIG_KTAG_N_NEOPIXEL_CHANNELS]; + +// Since the descriptors are (or should be) set to "trigger on descriptor completion" (`.interruptType = CY_DMA_DESCR`), +// this ISR is called after each channel has been written. +static void NeoPixel_DMA_Complete(void) +{ + static BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + Cy_DMA_Channel_ClearInterrupt(DMA_NeoPixel_HW, DMA_NeoPixel_DW_CHANNEL); + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + +#define NEOPIXEL_N_DESCRIPTORS CONFIG_KTAG_N_NEOPIXEL_CHANNELS +static cy_stc_dma_descriptor_t NeoPixel_Descriptors[NEOPIXEL_N_DESCRIPTORS]; +static void NeoPixel_Configure_DMA(void) +{ + // I [AH] copied this structure from the PSoC Creator Component configuration + // in the generated source. + const cy_stc_dma_descriptor_config_t NeoPixel_DMA_Descriptor_Config = + { + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_ENABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1L, + .dstXincrement = 0L, + .xCount = 256UL, + .srcYincrement = 0L, + .dstYincrement = 0L, + .yCount = 1UL, + .nextDescriptor = NULL + }; + + for (uint_fast8_t i=0; i < NEOPIXEL_N_DESCRIPTORS; i++) + { + Cy_DMA_Descriptor_Init(&NeoPixel_Descriptors[i], &NeoPixel_DMA_Descriptor_Config); + Cy_DMA_Descriptor_SetSrcAddress(&NeoPixel_Descriptors[i], (uint8_t *)&NeoPixel_Frame_Buffers[i][0]); + Cy_DMA_Descriptor_SetDstAddress(&NeoPixel_Descriptors[i], (void *)&SPI_NeoPixel_HW->TX_FIFO_WR); + Cy_DMA_Descriptor_SetXloopDataCount(&NeoPixel_Descriptors[i], FRAME_BUFFER_SIZE); + } + + // Initialize and enable the interrupt from DMA_NeoPixel_HW. + Cy_SysInt_Init(&DMA_NeoPixel_Int_cfg, &NeoPixel_DMA_Complete); + NVIC_EnableIRQ(DMA_NeoPixel_Int_cfg.intrSrc); + Cy_DMA_Channel_SetInterruptMask(DMA_NeoPixel_HW, DMA_NeoPixel_DW_CHANNEL, DMA_NeoPixel_INTR_MASK); + + Cy_DMA_Enable(DMA_NeoPixel_HW); +} + +// Function: NeoPixel_Trigger_DMA +// This function sets up the channel... then enables it to dump the frameBuffer to pixels. +void NeoPixel_Trigger_DMA(uint_fast8_t channel) +{ + cy_stc_dma_channel_config_t channel_config; + channel_config.descriptor = &NeoPixel_Descriptors[channel]; + channel_config.preemptable = DMA_NeoPixel_PREEMPTABLE; + channel_config.priority = DMA_NeoPixel_PRIORITY; + channel_config.enable = false; + Cy_DMA_Channel_Init(DMA_NeoPixel_HW, DMA_NeoPixel_DW_CHANNEL, &channel_config); + Cy_DMA_Channel_Enable(DMA_NeoPixel_HW, DMA_NeoPixel_DW_CHANNEL); +} + +//! Takes an 8-bit value representing a color level and turns it into a WS2812 bit code... +/*! + * ...where 1=110 and 0=011 + * One input byte turns into three output bytes of a uint32_t. + */ +uint32_t NeoPixel_ConvertTo3Code(uint8_t input) +{ + uint32_t rval=0; + for (uint_fast8_t i=0; i < 8; i++) + { + if (input % 2) + { + rval |= NEOPIXEL_ONE3; + } + else + { + rval |= NEOPIXEL_ZERO3; + } + rval = rval >> 3; + + input = input >> 1; + } + return rval; +} + +//! Takes a position and a three byte RGB value and updates the corresponding NeoPixel_Frame_Buffer with the correct nine bytes. +SystemKResult_T HW_NeoPixels_Set_RGB(NeoPixelsChannel_T channel, uint8_t position, uint8_t red, uint8_t green, uint8_t blue) +{ + typedef union { + uint8_t bytes[4]; + uint32_t word; + } NeoPixel_ColorByNumber; + + NeoPixel_ColorByNumber color; + ColorOrder_T order = ColorOrderByChannel[channel]; + + if (order == COLOR_ORDER_RGB) + { + color.word = NeoPixel_ConvertTo3Code(red); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+0+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+1+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+2+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(green); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+3+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+4+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+5+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(blue); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+6+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+7+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+8+NEOPIXEL_ZOFFSET] = color.bytes[0]; + } + else if (order == COLOR_ORDER_GRB) + { + color.word = NeoPixel_ConvertTo3Code(green); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+0+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+1+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+2+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(red); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+3+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+4+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+5+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(blue); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+6+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+7+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+8+NEOPIXEL_ZOFFSET] = color.bytes[0]; + } + else + { + // Color order is not handled--log this and use RGB. + { + static bool error_logged = false; + if (error_logged == false) + { + COMM_Console_Print_String("Color order "); + COMM_Console_Print_UInt8(order); + COMM_Console_Print_String(" not yet supported!"); + error_logged = true; + } + } + + color.word = NeoPixel_ConvertTo3Code(red); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+0+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+1+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+2+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(green); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+3+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+4+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+5+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(blue); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+6+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+7+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+8+NEOPIXEL_ZOFFSET] = color.bytes[0]; + } + + return SYSTEMK_RESULT_SUCCESS; +} + + +//! Initializes the hardware. +SystemKResult_T HW_NeoPixels_Init(void) +{ + Cy_SCB_SPI_Init(SPI_NeoPixel_HW, &SPI_NeoPixel_config, &SPI_NeoPixel_context); + Cy_SCB_SPI_Enable(SPI_NeoPixel_HW); + NeoPixel_Configure_DMA(); + +#if (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 1) + ColorOrderByChannel[NEOPIXEL_CHANNEL_BARREL] = NVM_BARREL_COLOR_ORDER; +#elif (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 4) + ColorOrderByChannel[NEOPIXEL_CHANNEL_BARREL] = NVM_BARREL_COLOR_ORDER; + ColorOrderByChannel[NEOPIXEL_CHANNEL_RECEIVER] = NVM_RECEIVER_COLOR_ORDER; + ColorOrderByChannel[NEOPIXEL_CHANNEL_DISPLAY] = NVM_DISPLAY_COLOR_ORDER; + ColorOrderByChannel[NEOPIXEL_CHANNEL_EFFECTS] = NVM_EFFECTS_COLOR_ORDER; +#else + #error "Unsupported number of NeoPixel channels defined. Supported configurations are 1 and 4." +#endif + + return SYSTEMK_RESULT_SUCCESS; +} + + +#if (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 1) +static inline __attribute__((always_inline)) void NeoPixels_Set_Color_On_All_Channels(uint8_t position, color_t color) +{ + HW_NeoPixels_Set_RGB(NEOPIXEL_CHANNEL_BARREL, position, Gamma8[Red(color)], Gamma8[Green(color)], Gamma8[Blue(color)]); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_All_Channels() +{ + // Nothing to do. +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Channel(uint_fast8_t __attribute__ ((unused)) channel) +{ + // Nothing to do. +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Channel(uint_fast8_t __attribute__ ((unused)) channel) +{ + // Nothing to do. +} +#elif (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 4) + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Barrel_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_0_PORT, Pin_NeoPixel_Select_0_NUM, 1); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Barrel_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_0_PORT, Pin_NeoPixel_Select_0_NUM, 0); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Receiver_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_1_PORT, Pin_NeoPixel_Select_1_NUM, 1); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Receiver_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_1_PORT, Pin_NeoPixel_Select_1_NUM, 0); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Display_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_2_PORT, Pin_NeoPixel_Select_2_NUM, 1); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Display_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_2_PORT, Pin_NeoPixel_Select_2_NUM, 0); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Effects_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_3_PORT, Pin_NeoPixel_Select_3_NUM, 1); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Effects_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_3_PORT, Pin_NeoPixel_Select_3_NUM, 0); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_All_Channels() +{ + NeoPixel_Enable_Barrel_Channel(); + NeoPixel_Enable_Receiver_Channel(); + NeoPixel_Enable_Display_Channel(); + NeoPixel_Enable_Effects_Channel(); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_All_Channels() +{ + NeoPixel_Disable_Barrel_Channel(); + NeoPixel_Disable_Receiver_Channel(); + NeoPixel_Disable_Display_Channel(); + NeoPixel_Disable_Effects_Channel(); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Channel(uint_fast8_t channel) +{ + switch (channel) + { + case NEOPIXEL_CHANNEL_BARREL: + NeoPixel_Enable_Barrel_Channel(); + break; + + case NEOPIXEL_CHANNEL_RECEIVER: + NeoPixel_Enable_Receiver_Channel(); + break; + + case NEOPIXEL_CHANNEL_DISPLAY: + NeoPixel_Enable_Display_Channel(); + break; + + case NEOPIXEL_CHANNEL_EFFECTS: + NeoPixel_Enable_Effects_Channel(); + break; + + default: + // Do nothing. + break; + } +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Channel(uint_fast8_t channel) +{ + switch (channel) + { + case NEOPIXEL_CHANNEL_BARREL: + NeoPixel_Disable_Barrel_Channel(); + break; + + case NEOPIXEL_CHANNEL_RECEIVER: + NeoPixel_Disable_Receiver_Channel(); + break; + + case NEOPIXEL_CHANNEL_DISPLAY: + NeoPixel_Disable_Display_Channel(); + break; + + case NEOPIXEL_CHANNEL_EFFECTS: + NeoPixel_Disable_Effects_Channel(); + break; + + default: + // Do nothing. + break; + } +} +#else + #error "Unsupported number of NeoPixel channels defined. Supported configurations are 1 and 4." +#endif + +SystemKResult_T HW_NeoPixels_Publish(void) +{ + // Update the NeoPixels using DMA. + for (uint_fast8_t Current_NeoPixel_Channel = 0; Current_NeoPixel_Channel < CONFIG_KTAG_N_NEOPIXEL_CHANNELS; Current_NeoPixel_Channel++) + { + xSemaphoreTake(NeoPixels_Semaphore, portMAX_DELAY); + NeoPixel_Enable_Channel(Current_NeoPixel_Channel); + NeoPixel_Trigger_DMA(Current_NeoPixel_Channel); + // Allow time for the DMA transfer to go out on the wire. + vTaskDelay(portTICK_PERIOD_MS); + NeoPixel_Disable_Channel(Current_NeoPixel_Channel); + xSemaphoreGive(NeoPixels_Semaphore); + } + + return SYSTEMK_RESULT_SUCCESS; +} + +//! \todo Refactor this somehow...it doesn't belong here. +color_t HW_NeoPixels_Get_My_Color(void) +{ + return PROTOCOLS_GetColor(GetWeaponFromID(NVM_WEAPON_ID).Protocol, NVM_TEAM_ID, NVM_PLAYER_ID); +} diff --git a/2020TPCApp1.cydsn/KTag.h b/2020TPCApp1.cydsn/KTag.h new file mode 100644 index 0000000..8bbe992 --- /dev/null +++ b/2020TPCApp1.cydsn/KTag.h @@ -0,0 +1,81 @@ +/** \file + * \brief This is the top-level include file for the entire project. + * + * By including this file (and only this file), include dependency order is maintained. + * + */ + +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKky+.`/ykKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKds/. -+o:` ./sdNKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKNds+-` `-+hNKKKKNho:` `-+shNKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKNkhyo+:. `-/sdNKKKKKKKKKKKKKky+:` .-/oyhdNKKKKKKKKKK +// KKys++:-.````.-:+oykNKKKKKKKKKKKKKKKKKKKKKKNkhs+/-.````.-:/+syKK +// KK -/+osydkNNNKKKkkkkkkkNKKKKKKKKKKKkkkkkkkkNKKKKNNkdhyso/: KK +// KK sKKKKKKKKKKKKK```````/KKKKKKKKKd-```````:kKKKKKKKKKKKKKd `KK +// KK- oKKKKKKKKKKKKK :KKKKKKKKo` `oNKKKKKKKKKKKKKKh :KK +// KK/ +KKKKKKKKKKKKK :KKKKKKd- -dKKKKKKKKKKKKKKKKy /KK +// KK+ /KKKKKKKKKKKKK :KKKKKs` +NKKKKKKKKKKKKKKKKKs +KK +// KKo :KKKKKKKKKKKKK :KKKk: .hKKKKKKKKKKKKKKKKKKKo oKK +// KKy -KKKKKKKKKKKKK :KKy` +NKKKKKKKKKKKKKKKKKKKK/ yKK +// KKd `KKKKKKKKKKKKK :k/ .hKKKKKKKKKKKKKKKKKKKKKK: dKK +// KKN NKKKKKKKKKKKK .. /kKKKKKKKKKKKKKKKKKKKKKKK. NKK +// KKK. dKKKKKKKKKKKK .yKKKKKKKKKKKKKKKKKKKKKKKKN .KKK +// KKK+ oKKKKKKKKKKKK -kKKKKKKKKKKKKKKKKKKKKKKKKKh +KKK +// KKKd .KKKKKKKKKKKK `sNKKKKKKKKKKKKKKKKKKKKKKKK/ dKKK +// KKKK: hKKKKKKKKKKK :kKKKKKKKKKKKKKKKKKKKKKKk :KKKK +// KKKKh -KKKKKKKKKKK `` .yKKKKKKKKKKKKKKKKKKKKK+ hKKKK +// KKKKK/ yKKKKKKKKKK T :d: /kKKKKKKKKKKKKKKKKKKk`:KKKKK +// KKKKKk`.NKKKKKKKKK :KNo` .hKKKKKKKKKKKKKKKKK:`kKKKKK +// KKKKKKy /KKKKKKKKK A :KKKd- +NKKKKKKKKKKKKKKo yKKKKKK +// KKKKKKK+ oKKKKKKKK :KKKKN+` -hKKKKKKKKKKKKy`+KKKKKKK +// KKKKKKKN/ sKKKKKKK G :KKKKKKh. `oNKKKKKKKKKh`/KKKKKKKK +// KKKKKKKKN/`sKKKKKK :KKKKKKKN/ -dKKKKKKKh`/NKKKKKKKK +// KKKKKKKKKK+ +NKKKK :KKKKKKKKKy. `sNKKKKs`+KKKKKKKKKK +// KKKKKKKKKKKs`:kKKK-------+KKKKKKKKKKk/--------oKKN+`sKKKKKKKKKKK +// KKKKKKKKKKKKh..yKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKd--dKKKKKKKKKKKK +// KKKKKKKKKKKKKN+`/kKKKKKKKKKKKKKKKKKKKKKKKKKKKKNo`+NKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKh-`sNKKKKKKKKKKKKKKKKKKKKKKKKNy.-hKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKs..sNKKKKKKKKKKKKKKKKKKKKNy-.yKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKNs..okKKKKKKKKKKKKKKKKNs-.sNKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKy-`/hKKKKKKKKKKKKd+`-yKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKd/`.odKKKKKKks-`/dKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKNs: .+yy+-`:sNKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKNy/..+yNKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK + + +#ifndef KTAG_H +#define KTAG_H + +/* Include FreeRTOS APIs and defines */ +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" +#include "semphr.h" +#include "portmacro.h" +#include "timers.h" + +/* Include PSoC system and component APIs and defines */ +#include + +#include +#include +#include +#include + +#include "CONFIG.h" +#include "SystemK.h" +#include "HW.h" +#include "Audio.h" +#include "NVM.h" +#include "COMM.h" +#include "Fire_Control.h" +#include "Sample_Tasks.h" +#include "Tag_Sensors.h" +#include "Switches.h" +#include "Util.h" + +#endif // KTAG_H diff --git a/2020TPCApp1.cydsn/Menu/GameSettings/GameMenuItem.c b/2020TPCApp1.cydsn/Menu/GameSettings/GameMenuItem.c new file mode 100644 index 0000000..1478413 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/GameSettings/GameMenuItem.c @@ -0,0 +1,79 @@ +/* Include Files */ +#include "KTag.h" + +static uint8_t SubmenuIndex = 0; +static MenuItem_T const * const Submenus[] = +{ + &TeamIDMenuItem, + &PlayerIDMenuItem +}; +static const uint8_t N_SUBMENUS = (sizeof(Submenus) / sizeof(MenuItem_T *)); + +static void OnFocus(bool IncludeDetails); +static MenuItem_T const * OnSelect(); +static void OnIncrement(); +static void OnDecrement(); + +const MenuItem_T GameMenuItem = +{ + .OnFocus = OnFocus, + .OnSelect = OnSelect, + .OnIncrement = OnIncrement, + .OnDecrement = OnDecrement + +}; + +static void OnFocus(bool IncludeDetails) +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_GAME_SETTINGS_PROMPT, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + if (IncludeDetails == true) + { + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } + } +} + +static MenuItem_T const * OnSelect() +{ + return Submenus[SubmenuIndex]; +} + +static void OnIncrement() +{ + if (SubmenuIndex < (N_SUBMENUS -1)) + { + SubmenuIndex++; + } + else + { + // Wrap around. + SubmenuIndex = 0; + } + + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } +} + +static void OnDecrement() +{ + if (SubmenuIndex > 0) + { + SubmenuIndex--; + } + else + { + // Wrap around. + SubmenuIndex = (N_SUBMENUS -1); + } + + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } +} diff --git a/2020TPCApp1.cydsn/Menu/GameSettings/GameMenuItem.h b/2020TPCApp1.cydsn/Menu/GameSettings/GameMenuItem.h new file mode 100644 index 0000000..675ea18 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/GameSettings/GameMenuItem.h @@ -0,0 +1,6 @@ +#ifndef GAMEMENUITEM_H +#define GAMEMENUITEM_H + +const MenuItem_T GameMenuItem; + +#endif // GAMEMENUITEM_H diff --git a/2020TPCApp1.cydsn/Menu/GameSettings/PlayerIDMenuItem.c b/2020TPCApp1.cydsn/Menu/GameSettings/PlayerIDMenuItem.c new file mode 100644 index 0000000..dc79ccd --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/GameSettings/PlayerIDMenuItem.c @@ -0,0 +1,66 @@ +/* Include Files */ +#include "KTag.h" + +#define MIN_PLAYER_ID 0b0000000 +#define MAX_PLAYER_ID 0b1111111 + +static void OnFocus(bool IncludeDetails); +static MenuItem_T const * OnSelect(); +static void OnIncrement(); +static void OnDecrement(); + +const MenuItem_T PlayerIDMenuItem = +{ + .OnFocus = OnFocus, + .OnSelect = OnSelect, + .OnIncrement = OnIncrement, + .OnDecrement = OnDecrement + +}; + +static void OnFocus(bool IncludeDetails) +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_PLAYER_ID_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + if (IncludeDetails == true) + { + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_PLAYER_ID}; + xQueueSend(xQueueAudio, &volume_action, 0); + } +} + +static MenuItem_T const * OnSelect() +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_SELECTION_INDICATOR, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + return NULL; +} + +static void OnIncrement() +{ + if (NVM_PLAYER_ID < MAX_PLAYER_ID) + { + NVM_PLAYER_ID++; + } + + AudioAction_T audio_action = {.ID = AUDIO_PLAY_PLAYER_ID_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_PLAYER_ID}; + xQueueSend(xQueueAudio, &volume_action, 0); +} + +static void OnDecrement() +{ + if (NVM_PLAYER_ID > MIN_PLAYER_ID) + { + NVM_PLAYER_ID--; + } + + AudioAction_T audio_action = {.ID = AUDIO_PLAY_PLAYER_ID_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_PLAYER_ID}; + xQueueSend(xQueueAudio, &volume_action, 0); +} \ No newline at end of file diff --git a/2020TPCApp1.cydsn/Menu/GameSettings/PlayerIDMenuItem.h b/2020TPCApp1.cydsn/Menu/GameSettings/PlayerIDMenuItem.h new file mode 100644 index 0000000..b18453c --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/GameSettings/PlayerIDMenuItem.h @@ -0,0 +1,6 @@ +#ifndef PLAYERIDMENUITEM_H +#define PLAYERIDMENUITEM_H + +const MenuItem_T PlayerIDMenuItem; + +#endif // PLAYERIDMENUITEM_H diff --git a/2020TPCApp1.cydsn/Menu/GameSettings/TeamIDMenuItem.c b/2020TPCApp1.cydsn/Menu/GameSettings/TeamIDMenuItem.c new file mode 100644 index 0000000..a16f807 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/GameSettings/TeamIDMenuItem.c @@ -0,0 +1,66 @@ +/* Include Files */ +#include "KTag.h" + +#define MIN_TEAM_ID 0 +#define MAX_TEAM_ID 3 + +static void OnFocus(bool IncludeDetails); +static MenuItem_T const * OnSelect(); +static void OnIncrement(); +static void OnDecrement(); + +const MenuItem_T TeamIDMenuItem = +{ + .OnFocus = OnFocus, + .OnSelect = OnSelect, + .OnIncrement = OnIncrement, + .OnDecrement = OnDecrement + +}; + +static void OnFocus(bool IncludeDetails) +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_TEAM_ID_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + if (IncludeDetails == true) + { + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_TEAM_ID}; + xQueueSend(xQueueAudio, &volume_action, 0); + } +} + +static MenuItem_T const * OnSelect() +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_SELECTION_INDICATOR, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + return NULL; +} + +static void OnIncrement() +{ + if (NVM_TEAM_ID < MAX_TEAM_ID) + { + NVM_TEAM_ID++; + } + + AudioAction_T audio_action = {.ID = AUDIO_PLAY_TEAM_ID_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_TEAM_ID}; + xQueueSend(xQueueAudio, &volume_action, 0); +} + +static void OnDecrement() +{ + if (NVM_TEAM_ID > MIN_TEAM_ID) + { + NVM_TEAM_ID--; + } + + AudioAction_T audio_action = {.ID = AUDIO_PLAY_TEAM_ID_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_TEAM_ID}; + xQueueSend(xQueueAudio, &volume_action, 0); +} \ No newline at end of file diff --git a/2020TPCApp1.cydsn/Menu/GameSettings/TeamIDMenuItem.h b/2020TPCApp1.cydsn/Menu/GameSettings/TeamIDMenuItem.h new file mode 100644 index 0000000..f5df1a2 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/GameSettings/TeamIDMenuItem.h @@ -0,0 +1,6 @@ +#ifndef TEAMIDMENUITEM_H +#define TEAMIDMENUITEM_H + +const MenuItem_T TeamIDMenuItem; + +#endif // TEAMIDMENUITEM_H diff --git a/2020TPCApp1.cydsn/Menu/HardwareSettings/HandedMenuItem.c b/2020TPCApp1.cydsn/Menu/HardwareSettings/HandedMenuItem.c new file mode 100644 index 0000000..aeab8ac --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/HardwareSettings/HandedMenuItem.c @@ -0,0 +1,64 @@ +/* Include Files */ +#include "KTag.h" + +static void OnFocus(bool IncludeDetails); +static MenuItem_T const * OnSelect(); +static void OnIncrement(); +static void OnDecrement(); +static void ToggleHanded(); + +const MenuItem_T HandedMenuItem = +{ + .OnFocus = OnFocus, + .OnSelect = OnSelect, + .OnIncrement = OnIncrement, + .OnDecrement = OnDecrement + +}; + +static void OnFocus(bool IncludeDetails) +{ + if (NVM_IS_RIGHT_HANDED == true) + { + AudioAction_T audio_action = {.ID = AUDIO_PLAY_RIGHT_HANDED, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + } + else + { + AudioAction_T audio_action = {.ID = AUDIO_PLAY_LEFT_HANDED, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + } +} + +static MenuItem_T const * OnSelect() +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_SELECTION_INDICATOR, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + return NULL; +} + +static void OnIncrement() +{ + ToggleHanded(); +} + +static void OnDecrement() +{ + ToggleHanded(); +} + +static void ToggleHanded() +{ + if (NVM_IS_RIGHT_HANDED == true) + { + NVM_IS_RIGHT_HANDED = false; + AudioAction_T audio_action = {.ID = AUDIO_PLAY_LEFT_HANDED, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + } + else + { + NVM_IS_RIGHT_HANDED = true; + AudioAction_T audio_action = {.ID = AUDIO_PLAY_RIGHT_HANDED, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + } +} diff --git a/2020TPCApp1.cydsn/Menu/HardwareSettings/HandedMenuItem.h b/2020TPCApp1.cydsn/Menu/HardwareSettings/HandedMenuItem.h new file mode 100644 index 0000000..e68953a --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/HardwareSettings/HandedMenuItem.h @@ -0,0 +1,6 @@ +#ifndef HANDEDMENUITEM_H +#define HANDEDMENUITEM_H + +const MenuItem_T HandedMenuItem; + +#endif // VOLUMEMENUITEM_H diff --git a/2020TPCApp1.cydsn/Menu/HardwareSettings/HardwareMenuItem.c b/2020TPCApp1.cydsn/Menu/HardwareSettings/HardwareMenuItem.c new file mode 100644 index 0000000..389f887 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/HardwareSettings/HardwareMenuItem.c @@ -0,0 +1,79 @@ +/* Include Files */ +#include "KTag.h" + +static uint8_t SubmenuIndex = 0; +static MenuItem_T const * const Submenus[] = +{ + &VolumeMenuItem, + &HandedMenuItem +}; +static const uint8_t N_SUBMENUS = (sizeof(Submenus) / sizeof(MenuItem_T *)); + +static void OnFocus(bool IncludeDetails); +static MenuItem_T const * OnSelect(); +static void OnIncrement(); +static void OnDecrement(); + +const MenuItem_T HardwareMenuItem = +{ + .OnFocus = OnFocus, + .OnSelect = OnSelect, + .OnIncrement = OnIncrement, + .OnDecrement = OnDecrement + +}; + +static void OnFocus(bool IncludeDetails) +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_HARDWARE_SETTINGS_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + if (IncludeDetails == true) + { + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } + } +} + +static MenuItem_T const * OnSelect() +{ + return Submenus[SubmenuIndex]; +} + +static void OnIncrement() +{ + if (SubmenuIndex < (N_SUBMENUS -1)) + { + SubmenuIndex++; + } + else + { + // Wrap around. + SubmenuIndex = 0; + } + + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } +} + +static void OnDecrement() +{ + if (SubmenuIndex > 0) + { + SubmenuIndex--; + } + else + { + // Wrap around. + SubmenuIndex = (N_SUBMENUS -1); + } + + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } +} \ No newline at end of file diff --git a/2020TPCApp1.cydsn/Menu/HardwareSettings/HardwareMenuItem.h b/2020TPCApp1.cydsn/Menu/HardwareSettings/HardwareMenuItem.h new file mode 100644 index 0000000..eef5484 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/HardwareSettings/HardwareMenuItem.h @@ -0,0 +1,6 @@ +#ifndef HARDWAREMENUITEM_H +#define HARDWAREMENUITEM_H + +const MenuItem_T HardwareMenuItem; + +#endif // HARDWAREMENUITEM_H diff --git a/2020TPCApp1.cydsn/Menu/HardwareSettings/VolumeMenuItem.c b/2020TPCApp1.cydsn/Menu/HardwareSettings/VolumeMenuItem.c new file mode 100644 index 0000000..88650c2 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/HardwareSettings/VolumeMenuItem.c @@ -0,0 +1,72 @@ +/* Include Files */ +#include "KTag.h" + +#define MAX_VOLUME 30 +#define MIN_VOLUME 5 + +static void OnFocus(bool IncludeDetails); +static MenuItem_T const * OnSelect(); +static void OnIncrement(); +static void OnDecrement(); + +const MenuItem_T VolumeMenuItem = +{ + .OnFocus = OnFocus, + .OnSelect = OnSelect, + .OnIncrement = OnIncrement, + .OnDecrement = OnDecrement + +}; + +static void OnFocus(bool IncludeDetails) +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_VOLUME_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + if (IncludeDetails == true) + { + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_VOLUME}; + xQueueSend(xQueueAudio, &volume_action, 0); + } +} + +static MenuItem_T const * OnSelect() +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_SELECTION_INDICATOR, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + return NULL; +} + +static void OnIncrement() +{ + if (NVM_VOLUME < MAX_VOLUME) + { + NVM_VOLUME++; + } + + AudioAction_T set_volume_action = {.ID = AUDIO_SET_VOLUME, .Data = (void *)&NVM_VOLUME}; + xQueueSend(xQueueAudio, &set_volume_action, 0); + + AudioAction_T audio_action = {.ID = AUDIO_PLAY_VOLUME_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_VOLUME}; + xQueueSend(xQueueAudio, &volume_action, 0); +} + +static void OnDecrement() +{ + if (NVM_VOLUME > MIN_VOLUME) + { + NVM_VOLUME--; + } + + AudioAction_T set_volume_action = {.ID = AUDIO_SET_VOLUME, .Data = (void *)&NVM_VOLUME}; + xQueueSend(xQueueAudio, &set_volume_action, 0); + + AudioAction_T audio_action = {.ID = AUDIO_PLAY_VOLUME_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + AudioAction_T volume_action = {.ID = AUDIO_PRONOUNCE_NUMBER_0_TO_100, .Play_To_Completion = true, .Data = (void *)&NVM_VOLUME}; + xQueueSend(xQueueAudio, &volume_action, 0); +} \ No newline at end of file diff --git a/2020TPCApp1.cydsn/Menu/HardwareSettings/VolumeMenuItem.h b/2020TPCApp1.cydsn/Menu/HardwareSettings/VolumeMenuItem.h new file mode 100644 index 0000000..8766f65 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/HardwareSettings/VolumeMenuItem.h @@ -0,0 +1,6 @@ +#ifndef VOLUMEMENUITEM_H +#define VOLUMEMENUITEM_H + +const MenuItem_T VolumeMenuItem; + +#endif // VOLUMEMENUITEM_H diff --git a/2020TPCApp1.cydsn/Menu/Menu.c b/2020TPCApp1.cydsn/Menu/Menu.c new file mode 100644 index 0000000..e4c263d --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/Menu.c @@ -0,0 +1,86 @@ +/* Include Files */ +#include "KTag.h" + +static uint8_t SubmenuIndex = 0; +static MenuItem_T const * const Submenus[] = +{ + &GameMenuItem, + &HardwareMenuItem +}; +static const uint8_t N_SUBMENUS = (sizeof(Submenus) / sizeof(MenuItem_T *)); + +static void RootMenuOnFocus(bool IncludeDetails); +static MenuItem_T const * RootMenuOnSelect(); +static void RootMenuOnIncrement(); +static void RootMenuOnDecrement(); + +static const MenuItem_T Root_Menu_Item = +{ + .OnFocus = RootMenuOnFocus, + .OnSelect = RootMenuOnSelect, + .OnIncrement = RootMenuOnIncrement, + .OnDecrement = RootMenuOnDecrement + +}; + +MenuItem_T const * const RootMenu = &Root_Menu_Item; + +static void RootMenuOnFocus(bool IncludeDetails) +{ + AudioAction_T audio_action = {.ID = AUDIO_PLAY_MENU_PROMPT, .Play_To_Completion = true, .Data = (void *)0x00}; + xQueueSend(xQueueAudio, &audio_action, 0); + + if (IncludeDetails == true) + { + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } + } +} + +static MenuItem_T const * RootMenuOnSelect() +{ + if (Submenus[SubmenuIndex]->OnSelect != NULL) + { + Submenus[SubmenuIndex]->OnSelect(); + } + + return Submenus[SubmenuIndex]; +} + +static void RootMenuOnIncrement() +{ + if (SubmenuIndex < (N_SUBMENUS -1)) + { + SubmenuIndex++; + } + else + { + // Wrap around. + SubmenuIndex = 0; + } + + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } +} + +static void RootMenuOnDecrement() +{ + if (SubmenuIndex > 0) + { + SubmenuIndex--; + } + else + { + // Wrap around. + SubmenuIndex = (N_SUBMENUS -1); + } + + if (Submenus[SubmenuIndex]->OnFocus != NULL) + { + Submenus[SubmenuIndex]->OnFocus(false); + } +} \ No newline at end of file diff --git a/2020TPCApp1.cydsn/Menu/Menu.h b/2020TPCApp1.cydsn/Menu/Menu.h new file mode 100644 index 0000000..ee64501 --- /dev/null +++ b/2020TPCApp1.cydsn/Menu/Menu.h @@ -0,0 +1,28 @@ +#ifndef MENU_H +#define MENU_H + +#include +#include + + +typedef struct MenuItem_S +{ + // Performs the actions required when this MenuItem receives focus. + void (*OnFocus)(bool IncludeDetails); + // Performs the actions required when this MenuItem receives focus. + struct MenuItem_S const * (*OnSelect)(void); + void (*OnIncrement)(void); + void (*OnDecrement)(void); + +} MenuItem_T; + +MenuItem_T const * const RootMenu; + +#include "GameSettings/GameMenuItem.h" +#include "GameSettings/PlayerIDMenuItem.h" +#include "GameSettings/TeamIDMenuItem.h" +#include "HardwareSettings/HardwareMenuItem.h" +#include "HardwareSettings/VolumeMenuItem.h" +#include "HardwareSettings/HandedMenuItem.h" + +#endif // MENU_H diff --git a/2020TPCApp1.cydsn/NVM/NVM.h b/2020TPCApp1.cydsn/NVM/NVM.h new file mode 100644 index 0000000..ffd8cad --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM.h @@ -0,0 +1,105 @@ +/** \dir NVM + * + * \brief Non-Volatile Memory + * + * This directory/namespace contains all the software used to manage non-volatile memory for this CPU. + * + */ + +/** \file + * \brief This file defines the interface to the NVM package. + * + * This file should be included by any file outside the NVM package wishing to make use + * of any of the NVM functionality. + */ + +#ifndef NVM_H +#define NVM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +//! Enumeration of the various states of a nonvolatile memory entry. +typedef enum +{ + //! This entry has not yet been initialized. + NVM_STATE_UNINITIALIZED = 0, + + //! This entry has been read from nonvolatile memory, and the cyclic redundancy check failed. + NVM_STATE_CRC_FAILED, + + //! No changes are pending for this entry. + NVM_STATE_IDLE, + + //! A request has been made to save this entry to NVM. + NVM_STATE_SAVE_REQUESTED +} NVM_Entry_State_T; + + +typedef struct +{ + // Size of the NVM data. + const size_t Size; + + // Address of the NVM data in the EEPROM memory. + const uint16_t EE_Address; + + // Address of the calculated CRC value in the EEPROM memory. + const uint16_t EE_CRC_Address; + + // Address of the NVM data in RAM. + uint8_t * const Value; + + // Address of the default data in ROM. + uint8_t const * const Default; + + // Current state of this NVM entry + NVM_Entry_State_T State; + +} NVM_EEPROMEntry_T; + + +/* Include Files */ +#include "NVM_CRC.h" + +#if (CONFIG__HAS_EXTERNAL_NVM) +#include "NVM_ExternalEEPROM.h" +#include "NVM_ExternalEEPROMEntries.h" +#endif // CONFIG__HAS_EXTERNAL_NVM + +#if (CONFIG__HAS_INTERNAL_NVM) +#include "NVM_OnChipEEPROM.h" +#include "NVM_OnChipEEPROMEntries.h" +#endif // CONFIG__HAS_INTERNAL_NVM + +/* Public Variables */ + +/* Public Functions */ + +inline bool IsNVMInitialized() +{ + taskENTER_CRITICAL(); + bool is_initialized = + +#if (CONFIG__HAS_EXTERNAL_NVM) + NVM_IsExternalEEPROMInitialized && +#endif // CONFIG__HAS_EXTERNAL_NVM + +#if (CONFIG__HAS_INTERNAL_NVM) + NVM_IsOnChipEEPROMInitialized && +#endif // CONFIG__HAS_INTERNAL_NVM + + true; + taskEXIT_CRITICAL(); + + return is_initialized; +} + +#ifdef __cplusplus +} +#endif + +#endif // NVM_H \ No newline at end of file diff --git a/2020TPCApp1.cydsn/NVM/NVM_CRC.c b/2020TPCApp1.cydsn/NVM/NVM_CRC.c new file mode 100644 index 0000000..09a9026 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_CRC.c @@ -0,0 +1,72 @@ +/** + * \file + * Functions and types for CRC checks. + * + * Generated on Sat Jun 15 14:34:15 2019 + * by pycrc v0.9.2, https://pycrc.org + * using the configuration: + * - Width = 16 + * - Poly = 0xed2f + * - XorIn = 0xbeef + * - ReflectIn = False + * - XorOut = 0x0000 + * - ReflectOut = False + * - Algorithm = table-driven + */ +#include "NVM_CRC.h" /* include the header file generated with pycrc */ +#include +#include + + + +/** + * Static table used for the table_driven implementation. + */ +static const NVM_CRC_t crc_table[256] = { + 0x0000, 0xed2f, 0x3771, 0xda5e, 0x6ee2, 0x83cd, 0x5993, 0xb4bc, + 0xddc4, 0x30eb, 0xeab5, 0x079a, 0xb326, 0x5e09, 0x8457, 0x6978, + 0x56a7, 0xbb88, 0x61d6, 0x8cf9, 0x3845, 0xd56a, 0x0f34, 0xe21b, + 0x8b63, 0x664c, 0xbc12, 0x513d, 0xe581, 0x08ae, 0xd2f0, 0x3fdf, + 0xad4e, 0x4061, 0x9a3f, 0x7710, 0xc3ac, 0x2e83, 0xf4dd, 0x19f2, + 0x708a, 0x9da5, 0x47fb, 0xaad4, 0x1e68, 0xf347, 0x2919, 0xc436, + 0xfbe9, 0x16c6, 0xcc98, 0x21b7, 0x950b, 0x7824, 0xa27a, 0x4f55, + 0x262d, 0xcb02, 0x115c, 0xfc73, 0x48cf, 0xa5e0, 0x7fbe, 0x9291, + 0xb7b3, 0x5a9c, 0x80c2, 0x6ded, 0xd951, 0x347e, 0xee20, 0x030f, + 0x6a77, 0x8758, 0x5d06, 0xb029, 0x0495, 0xe9ba, 0x33e4, 0xdecb, + 0xe114, 0x0c3b, 0xd665, 0x3b4a, 0x8ff6, 0x62d9, 0xb887, 0x55a8, + 0x3cd0, 0xd1ff, 0x0ba1, 0xe68e, 0x5232, 0xbf1d, 0x6543, 0x886c, + 0x1afd, 0xf7d2, 0x2d8c, 0xc0a3, 0x741f, 0x9930, 0x436e, 0xae41, + 0xc739, 0x2a16, 0xf048, 0x1d67, 0xa9db, 0x44f4, 0x9eaa, 0x7385, + 0x4c5a, 0xa175, 0x7b2b, 0x9604, 0x22b8, 0xcf97, 0x15c9, 0xf8e6, + 0x919e, 0x7cb1, 0xa6ef, 0x4bc0, 0xff7c, 0x1253, 0xc80d, 0x2522, + 0x8249, 0x6f66, 0xb538, 0x5817, 0xecab, 0x0184, 0xdbda, 0x36f5, + 0x5f8d, 0xb2a2, 0x68fc, 0x85d3, 0x316f, 0xdc40, 0x061e, 0xeb31, + 0xd4ee, 0x39c1, 0xe39f, 0x0eb0, 0xba0c, 0x5723, 0x8d7d, 0x6052, + 0x092a, 0xe405, 0x3e5b, 0xd374, 0x67c8, 0x8ae7, 0x50b9, 0xbd96, + 0x2f07, 0xc228, 0x1876, 0xf559, 0x41e5, 0xacca, 0x7694, 0x9bbb, + 0xf2c3, 0x1fec, 0xc5b2, 0x289d, 0x9c21, 0x710e, 0xab50, 0x467f, + 0x79a0, 0x948f, 0x4ed1, 0xa3fe, 0x1742, 0xfa6d, 0x2033, 0xcd1c, + 0xa464, 0x494b, 0x9315, 0x7e3a, 0xca86, 0x27a9, 0xfdf7, 0x10d8, + 0x35fa, 0xd8d5, 0x028b, 0xefa4, 0x5b18, 0xb637, 0x6c69, 0x8146, + 0xe83e, 0x0511, 0xdf4f, 0x3260, 0x86dc, 0x6bf3, 0xb1ad, 0x5c82, + 0x635d, 0x8e72, 0x542c, 0xb903, 0x0dbf, 0xe090, 0x3ace, 0xd7e1, + 0xbe99, 0x53b6, 0x89e8, 0x64c7, 0xd07b, 0x3d54, 0xe70a, 0x0a25, + 0x98b4, 0x759b, 0xafc5, 0x42ea, 0xf656, 0x1b79, 0xc127, 0x2c08, + 0x4570, 0xa85f, 0x7201, 0x9f2e, 0x2b92, 0xc6bd, 0x1ce3, 0xf1cc, + 0xce13, 0x233c, 0xf962, 0x144d, 0xa0f1, 0x4dde, 0x9780, 0x7aaf, + 0x13d7, 0xfef8, 0x24a6, 0xc989, 0x7d35, 0x901a, 0x4a44, 0xa76b +}; + + +NVM_CRC_t NVM_CRC_update(NVM_CRC_t crc, const void *data, size_t data_len) +{ + const unsigned char *d = (const unsigned char *)data; + unsigned int tbl_idx; + + while (data_len--) { + tbl_idx = ((crc >> 8) ^ *d) & 0xff; + crc = (crc_table[tbl_idx] ^ (crc << 8)) & 0xffff; + d++; + } + return crc & 0xffff; +} \ No newline at end of file diff --git a/2020TPCApp1.cydsn/NVM/NVM_CRC.h b/2020TPCApp1.cydsn/NVM/NVM_CRC.h new file mode 100644 index 0000000..bbb2807 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_CRC.h @@ -0,0 +1,115 @@ +/** + * \file + * Functions and types for CRC checks. + * + * Generated on Sat Jun 15 14:34:05 2019 + * by pycrc v0.9.2, https://pycrc.org + * using the configuration: + * - Width = 16 + * - Poly = 0xed2f + * - XorIn = 0xbeef + * - ReflectIn = False + * - XorOut = 0x0000 + * - ReflectOut = False + * - Algorithm = table-driven + * + * This file defines the functions NVM_CRC_init(), NVM_CRC_update() and NVM_CRC_finalize(). + * + * The NVM_CRC_init() function returns the inital \c crc value and must be called + * before the first call to NVM_CRC_update(). + * Similarly, the NVM_CRC_finalize() function must be called after the last call + * to NVM_CRC_update(), before the \c crc is being used. + * is being used. + * + * The NVM_CRC_update() function can be called any number of times (including zero + * times) in between the NVM_CRC_init() and NVM_CRC_finalize() calls. + * + * This pseudo-code shows an example usage of the API: + * \code{.c} + * NVM_CRC_t crc; + * unsigned char data[MAX_DATA_LEN]; + * size_t data_len; + * + * crc = NVM_CRC_init(); + * while ((data_len = read_data(data, MAX_DATA_LEN)) > 0) { + * crc = NVM_CRC_update(crc, data, data_len); + * } + * crc = NVM_CRC_finalize(crc); + * \endcode + * + * ## Additional Notes + * + * The CRC polynomial (0xED2F) was chosen based on the research published by Philip Koopman of Carnegie Mellon + * University [here](http://users.ece.cmu.edu/~koopman/crc/). Dr. Koopman claims this polynomial has a + * Hamming Distance of 10. + * + * The initial value, 0xBEEF, was chosen simply to avoid the most common EE values of 0xFFFF and 0x0000. + * + */ +#ifndef NVM_CRC_H +#define NVM_CRC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * The definition of the used algorithm. + * + * This is not used anywhere in the generated code, but it may be used by the + * application code to call algorithm-specific code, if desired. + */ +#define CRC_ALGO_TABLE_DRIVEN 1 + + +/** + * The type of the CRC values. + * + * CRCs are sixteen bits wide. + */ +typedef uint16_t NVM_CRC_t; + + +/** + * Calculate the initial crc value. + * + * \return The initial crc value. + */ +static inline NVM_CRC_t NVM_CRC_init(void) +{ + return 0xbeef; +} + + +/** + * Update the crc value with new data. + * + * \param[in] crc The current crc value. + * \param[in] data Pointer to a buffer of \a data_len bytes. + * \param[in] data_len Number of bytes in the \a data buffer. + * \return The updated crc value. + */ +NVM_CRC_t NVM_CRC_update(NVM_CRC_t crc, const void *data, size_t data_len); + + +/** + * Calculate the final crc value. + * + * \param[in] crc The current crc value. + * \return The final crc value. + */ +static inline NVM_CRC_t NVM_CRC_finalize(NVM_CRC_t crc) +{ + return crc; +} + + +#ifdef __cplusplus +} /* closing brace for extern "C" */ +#endif + +#endif /* NVM_CRC_H */ \ No newline at end of file diff --git a/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROM.c b/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROM.c new file mode 100644 index 0000000..84cf845 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROM.c @@ -0,0 +1,302 @@ +/** \file + * \brief This file contains functions that manage the external EEPROM. + * + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +//! This is the same for both the MCP98243 and the CAT24C256. +#define EXTERNAL_EEPROM_I2C_ADDRESS 0x50 +#define EXTERNAL_EEPROM_TEMP_SENSOR_I2C_ADDRESS 0x18 + +//! Read-only register used to identify the temperature sensor capability. +#define MCP98243_REGISTER_CAPABILITY 0x00 +//! Sensor configuration register. +#define MCP98243_REGISTER_CONFIG 0x01 +//! Upper temperature limit register. +#define MCP98243_REGISTER_T_UPPER 0x02 +//! Lower temperature limit register. +#define MCP98243_REGISTER_T_LOWER 0x03 +//! Critical temperature limit register. +#define MCP98243_REGISTER_T_CRIT 0x04 +//! Ambient temperature register. +#define MCP98243_REGISTER_T_A 0x05 +//! Read-only register used to identify the manufacturer of the device. +#define MCP98243_REGISTER_MANUFACTURER_ID 0x06 +//! Read-only register indicating the device identification and device revision. +#define MCP98243_REGISTER_DEVICE_ID 0x07 +//! Temperature sensor resolution register. +#define MCP98243_REGISTER_RESOLUTION 0x08 + + +/* External Variables [Only if necessary!] */ + +/* External Function Prototypes [Only if necessary!] */ + +/* Public Variables */ + +//! Mutex controlling access to the EEPROM to ensure data/CRC integrity. +SemaphoreHandle_t xSemaphoreExternalEEPROMLock; + +TaskHandle_t NVM_ExternalEEPROM_Task_Handle; + +volatile bool NVM_IsExternalEEPROMInitialized = false; + +/* Private Variables */ + +static QueueHandle_t xQueueExternalEEPROM; + +//! Shared master transfer configuration variable. +static cy_stc_scb_i2c_master_xfer_config_t Master_Transfer_Config = +{ + .slaveAddress = EXTERNAL_EEPROM_I2C_ADDRESS, + .buffer = NULL, + .bufferSize = 0U, + .xferPending = false +}; + + +/* Private Function Prototypes */ + +/* Inline Functions */ + +//! Waits a given time for an I²C transfer to complete. +/*! + * \param timeout_in_ms The time (in milliseconds) to wait for the transfer to complete. + * \return #true if the transfer completed, or #false if the time ran out without + * a successful transfer. + */ +static inline bool Wait_For_Transfer_To_Complete(uint16_t timeout_in_ms) +{ + bool success = false; + + // Time to wait for an in-process transfer before looking again. This wait grows longer as time + // passes, until timeout_in_ms runs out. + uint16_t HOLDOFF_TIME_IN_ms = 1; + + while ((success == false) && (timeout_in_ms > 0)) + { + vTaskDelay(pdMS_TO_TICKS(HOLDOFF_TIME_IN_ms)); + + if (timeout_in_ms > HOLDOFF_TIME_IN_ms) + { + timeout_in_ms -= HOLDOFF_TIME_IN_ms; + + // Wait a little longer next time. + HOLDOFF_TIME_IN_ms++; + } + else + { + timeout_in_ms = 0; + } + + if ((I2C_MasterGetStatus() & CY_SCB_I2C_MASTER_BUSY) != CY_SCB_I2C_MASTER_BUSY) + { + success = true; + } + } + + return success; +} + +//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination. +static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n) +{ + uint8_t xfer_buffer[5]; + + if (xSemaphoreTake(COMM_I2C_Bus_Mutex, portMAX_DELAY) == pdTRUE) + { + // Write the initial address to the EEPROM. + xfer_buffer[0] = (source >> 8); + xfer_buffer[1] = source & 0xFF; + + Master_Transfer_Config.buffer = (uint8_t *)xfer_buffer; + Master_Transfer_Config.bufferSize = 2; + + cy_en_scb_i2c_status_t errStatus = I2C_MasterWrite(&Master_Transfer_Config); + + if (errStatus == CY_SCB_I2C_SUCCESS) + { + (void) Wait_For_Transfer_To_Complete(100); + } + else + { + // What? + } + + // Read n bytes at EEPROM[source]. + Master_Transfer_Config.buffer = (uint8_t *)destination; + Master_Transfer_Config.bufferSize = n; + + errStatus = I2C_MasterRead(&Master_Transfer_Config); + + if (errStatus == CY_SCB_I2C_SUCCESS) + { + (void) Wait_For_Transfer_To_Complete(100); + } + else + { + // What? + } + + xSemaphoreGive(COMM_I2C_Bus_Mutex); + } +} + +//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination. +static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n) +{ + uint8_t xfer_buffer[4]; + + if (xSemaphoreTake(COMM_I2C_Bus_Mutex, portMAX_DELAY) == pdTRUE) + { + // Write the data one byte at a time. + for (uint8_t i = 0; i < n; i++) + { + uint16_t destination_address = destination + i; + xfer_buffer[0] = (destination_address >> 8); + xfer_buffer[1] = destination_address & 0xFF; + xfer_buffer[2] = *(source + i); + + Master_Transfer_Config.buffer = (uint8_t *)xfer_buffer; + Master_Transfer_Config.bufferSize = 3; + + cy_en_scb_i2c_status_t errStatus = I2C_MasterWrite(&Master_Transfer_Config); + + if (errStatus == CY_SCB_I2C_SUCCESS) + { + (void) Wait_For_Transfer_To_Complete(100); + } + else + { + // What? + } + + // The CAT24C256 has a nominal Write Cycle time (t_WR) of 5ms (no maximum specified). + // Wait 6ms between writes to have some margin (and avoid being NAKed). + vTaskDelay(pdMS_TO_TICKS(6)); + } + + xSemaphoreGive(COMM_I2C_Bus_Mutex); + } +} + + +/* Public Functions */ + +//! Sets up the external EEPROM, but does not read from it (yet). +void NVM_InitExternalEEPROM(void) +{ + /// Create a mutex-type semaphore. + xSemaphoreExternalEEPROMLock = xSemaphoreCreateMutex(); + + if (xSemaphoreExternalEEPROMLock == NULL) + { + CY_ASSERT(0); + } + + xQueueExternalEEPROM = xQueueCreate(5, sizeof(uint8_t)); +} + +//! Handles the ongoing external EEPROM tasks. +/*! + * First, it loops through all the external EEPROM entries, and reads them in to RAM. + * Then, it priodically loops through all the external EEPROM entries, and saves the ones that have been flagged. + */ +void NVM_ExternalEEPROMTask(void * pvParameters) +{ + portBASE_TYPE xStatus; + static TickType_t xTicksToWait = pdMS_TO_TICKS(NVM_EXTERNAL_EEPROM_TASK_RATE_IN_ms); + + for (uint8_t i = 0; i < NVM_N_EXTERNAL_EEPROM_ENTRIES; i++) + { + NVM_CRC_t calculated_crc; + NVM_CRC_t stored_crc = 0; + + EEPROM_read_block(NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->EE_Address, NVM_ExternalEEPROMEntries[i]->Size); + EEPROM_read_block((uint8_t *)&stored_crc, NVM_ExternalEEPROMEntries[i]->EE_CRC_Address, sizeof(NVM_CRC_t)); + + calculated_crc = NVM_CRC_init(); + calculated_crc = NVM_CRC_update(calculated_crc, NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->Size); + calculated_crc = NVM_CRC_finalize(calculated_crc); + + if (calculated_crc == stored_crc) + { + NVM_ExternalEEPROMEntries[i]->State = NVM_STATE_IDLE; + } + else + { + NVM_ExternalEEPROMEntries[i]->State = NVM_STATE_CRC_FAILED; + + COMM_Console_Print_String("[NVMEx "); + COMM_Console_Print_UInt16((uint16_t) i); + COMM_Console_Print_String("] Calculated/Stored CRCs: "); + COMM_Console_Print_UInt16((uint16_t) calculated_crc); + COMM_Console_Print_String("/"); + COMM_Console_Print_UInt16((uint16_t) stored_crc); + COMM_Console_Print_String("\n"); + + COMM_Console_Print_String("[NVMEx "); + COMM_Console_Print_UInt16((uint16_t) i); + COMM_Console_Print_String("] Applying defaults.\n"); + + memcpy(NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->Default, NVM_ExternalEEPROMEntries[i]->Size); + + // Auto-fix the CRC. + NVM_SaveExternalEEPROMEntry(NVM_ExternalEEPROMEntries[i]); + } + } + + taskENTER_CRITICAL(); + NVM_IsExternalEEPROMInitialized = true; + taskEXIT_CRITICAL(); + + while(true) + { + uint8_t dummy; + + // Wait for a call to NVM_SaveExternalEEPROMEntry(). + xStatus = xQueueReceive(xQueueExternalEEPROM, &dummy, xTicksToWait); + + if (xStatus == pdPASS) + { + for (uint8_t i = 0; i < NVM_N_EXTERNAL_EEPROM_ENTRIES; i++) + { + NVM_CRC_t crc; + + if (NVM_ExternalEEPROMEntries[i]->State == NVM_STATE_SAVE_REQUESTED) + { + if (xSemaphoreTake(xSemaphoreExternalEEPROMLock, portMAX_DELAY) == pdTRUE) + { + EEPROM_write_block(NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->EE_Address, NVM_ExternalEEPROMEntries[i]->Size); + + // Calculate the CRC. + crc = NVM_CRC_init(); + crc = NVM_CRC_update(crc, NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->Size); + crc = NVM_CRC_finalize(crc); + EEPROM_write_block((uint8_t *)&crc, NVM_ExternalEEPROMEntries[i]->EE_CRC_Address, sizeof(uint16_t)); + NVM_ExternalEEPROMEntries[i]->State = NVM_STATE_IDLE; + xSemaphoreGive(xSemaphoreExternalEEPROMLock); + } + } + } + } + } +} + +//! Flags the given external EEPROM entry to be saved next time the NVM_ExternalEEPROMTask() is run. +void NVM_SaveExternalEEPROMEntry(NVM_EEPROMEntry_T * const this) +{ + if (xSemaphoreTake(xSemaphoreExternalEEPROMLock, portMAX_DELAY) == pdTRUE) + { + this->State = NVM_STATE_SAVE_REQUESTED; + xSemaphoreGive(xSemaphoreExternalEEPROMLock); + uint8_t dummy = 0; + xQueueSend(xQueueExternalEEPROM, &dummy, 0); + } +} + +/* Private Functions */ diff --git a/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROM.h b/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROM.h new file mode 100644 index 0000000..afa7440 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROM.h @@ -0,0 +1,44 @@ +/** \file + * \brief This file contains the public interface to the external EEPROM. + * + * On the 2020TPC, the external EEPROM is the Onsemi [CAT24C256](https://www.onsemi.com/pdf/datasheet/cat24c256-d.pdf). + * + */ + +#ifndef NVM_EXTERNALEEPROM_H +#define NVM_EXTERNALEEPROM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +#define NVM_EXTERNAL_EEPROM_TASK_STACK_SIZE_in_bytes 256 + +//! The time between calls to NVM_ExternalEEPROMTask(). +#define NVM_EXTERNAL_EEPROM_TASK_RATE_IN_ms 2000 + +/* Include Files */ + +/* Public Variables */ + +extern SemaphoreHandle_t xSemaphoreExternalEEPROMLock; + +//! Handle of the NVM_ExternalEEPROMTask() given when the task was created. +extern TaskHandle_t NVM_ExternalEEPROM_Task_Handle; + +extern volatile bool NVM_IsExternalEEPROMInitialized; + +/* Public Functions */ +void NVM_InitExternalEEPROM(void); +void NVM_ExternalEEPROMTask(void * pvParameters); +void NVM_SaveExternalEEPROMEntry(NVM_EEPROMEntry_T * const this); + +/* Inline Functions */ + +#ifdef __cplusplus +} +#endif + +#endif // NVM_EXTERNALEEPROM_H diff --git a/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROMEntries.c b/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROMEntries.c new file mode 100644 index 0000000..832da53 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROMEntries.c @@ -0,0 +1,153 @@ +/* + * __ ________ _____ ______ __ + * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ + * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ + * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ + * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ + * /____/ + * + * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞 + * + */ + +/** \file + * \brief [Autogenerated] This file defines the External EEPROM entries. + * + * \note AUTOGENERATED: This file was generated automatically on Friday, April 28, 2023 at 11:31:31 AM. + * DO NOT MODIFY THIS FILE MANUALLY! + */ + +/* Include Files */ +#include "KTag.h" + +/* EEPROM Entries */ + +/** \defgroup NVM_EXTERNAL_EEPROM NVM External EEPROM + * + * The External EEPROM is divided into logical "entries", represented by instances of the #NVM_EEPROMEntry_T type. + * At startup, these entries are loaded into their respective RAM copies by NVM_InitExternalEEPROM(). The application + * then updates the RAM copies directly, and requests that the NVM_ExternalEEPROMTask() save these back to the EEPROM + * when necessary. + * @{ */ + +static NVM_External_Test_T RAM_External_Test; + +static const NVM_External_Test_T DEFAULT_External_Test = +{ + //! Test Code 3 + .External_Test_3 = UINT16_MAX, + //! Test Code 4 + .External_Test_4 = UINT32_MAX, +}; + +NVM_EEPROMEntry_T NVM_External_Test = +{ + //! Size == sizeof(NVM_External_Test_T) + .Size = 6, + .EE_Address = 0, + .EE_CRC_Address = 6, + .Value = (uint8_t *)&RAM_External_Test, + .Default = (uint8_t *)&DEFAULT_External_Test, + .State = NVM_STATE_UNINITIALIZED +}; +static NVM_Info_T RAM_Info; + +static const NVM_Info_T DEFAULT_Info = +{ + //! Date this unit was first programmed. + .Date_Code_as_YYYYMMDD = 20200101, +}; + +NVM_EEPROMEntry_T NVM_Info = +{ + //! Size == sizeof(NVM_Info_T) + .Size = 4, + .EE_Address = 8, + .EE_CRC_Address = 12, + .Value = (uint8_t *)&RAM_Info, + .Default = (uint8_t *)&DEFAULT_Info, + .State = NVM_STATE_UNINITIALIZED +}; +static NVM_Hardware_Settings_T RAM_Hardware_Settings; + +static const NVM_Hardware_Settings_T DEFAULT_Hardware_Settings = +{ + //! Color order for the barrel Neopixels. + .Barrel_Color_Order = 2, + //! Color order for the receiver NeoPixels. + .Receiver_Color_Order = 0, + //! Color order for the display NeoPixels. + .Display_Color_Order = 2, + //! Color order for the effects NeoPixels. + .Effects_Color_Order = 2, + //! true if this unit is configured for a right-handed person; false if for a left-handed person. + .Is_Right_Handed = true, + //! Audio volume. + .Volume = 20, +}; + +NVM_EEPROMEntry_T NVM_Hardware_Settings = +{ + //! Size == sizeof(NVM_Hardware_Settings_T) + .Size = 6, + .EE_Address = 14, + .EE_CRC_Address = 20, + .Value = (uint8_t *)&RAM_Hardware_Settings, + .Default = (uint8_t *)&DEFAULT_Hardware_Settings, + .State = NVM_STATE_UNINITIALIZED +}; +static NVM_Game_Settings_T RAM_Game_Settings; + +static const NVM_Game_Settings_T DEFAULT_Game_Settings = +{ + //! Selected weapon. + .Weapon_ID = LASER_X_ID, + //! Player identification (is this used?) + .Player_ID = 0, + //! Selected team. + .Team_ID = 1, +}; + +NVM_EEPROMEntry_T NVM_Game_Settings = +{ + //! Size == sizeof(NVM_Game_Settings_T) + .Size = 3, + .EE_Address = 22, + .EE_CRC_Address = 25, + .Value = (uint8_t *)&RAM_Game_Settings, + .Default = (uint8_t *)&DEFAULT_Game_Settings, + .State = NVM_STATE_UNINITIALIZED +}; +static NVM_Hourmeter_T RAM_Hourmeter; + +static const NVM_Hourmeter_T DEFAULT_Hourmeter = +{ + //! Total number of startups for this unit. + .Hourmeter_Startups = 0, +}; + +NVM_EEPROMEntry_T NVM_Hourmeter = +{ + //! Size == sizeof(NVM_Hourmeter_T) + .Size = 2, + .EE_Address = 27, + .EE_CRC_Address = 29, + .Value = (uint8_t *)&RAM_Hourmeter, + .Default = (uint8_t *)&DEFAULT_Hourmeter, + .State = NVM_STATE_UNINITIALIZED +}; + +/** @} */ + +NVM_EEPROMEntry_T * const NVM_ExternalEEPROMEntries[] = +{ + &NVM_External_Test, + &NVM_Info, + &NVM_Hardware_Settings, + &NVM_Game_Settings, + &NVM_Hourmeter, +}; + +//! Size of the #NVM_ExternalEEPROMEntries array (i.e. the number of External EEPROM entries). +const uint8_t NVM_N_EXTERNAL_EEPROM_ENTRIES = (uint8_t) (sizeof(NVM_ExternalEEPROMEntries) / sizeof(NVM_EEPROMEntry_T *)); + diff --git a/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROMEntries.h b/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROMEntries.h new file mode 100644 index 0000000..61d7103 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_ExternalEEPROMEntries.h @@ -0,0 +1,135 @@ +/* + * __ ________ _____ ______ __ + * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ + * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ + * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ + * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ + * /____/ + * + * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞 + * + */ + +/** \file + * \brief [Autogenerated] This file declares the External EEPROM entries. + * + * \note AUTOGENERATED: This file was generated automatically on Friday, April 28, 2023 at 11:31:31 AM. + * DO NOT MODIFY THIS FILE MANUALLY! + */ + +#ifndef NVM_EXTERNALEEPROMENTRIES_H +#define NVM_EXTERNALEEPROMENTRIES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +typedef struct __attribute__((packed)) +{ + //! Test Code 3 + uint16_t External_Test_3; + //! Test Code 4 + uint32_t External_Test_4; +} NVM_External_Test_T; + +typedef struct __attribute__((packed)) +{ + //! Date this unit was first programmed. + uint32_t Date_Code_as_YYYYMMDD; +} NVM_Info_T; + +typedef struct __attribute__((packed)) +{ + //! Color order for the barrel Neopixels. + uint8_t Barrel_Color_Order; + //! Color order for the receiver NeoPixels. + uint8_t Receiver_Color_Order; + //! Color order for the display NeoPixels. + uint8_t Display_Color_Order; + //! Color order for the effects NeoPixels. + uint8_t Effects_Color_Order; + //! true if this unit is configured for a right-handed person; false if for a left-handed person. + bool Is_Right_Handed; + //! Audio volume. + uint8_t Volume; +} NVM_Hardware_Settings_T; + +typedef struct __attribute__((packed)) +{ + //! Selected weapon. + uint8_t Weapon_ID; + //! Player identification (is this used?) + uint8_t Player_ID; + //! Selected team. + uint8_t Team_ID; +} NVM_Game_Settings_T; + +typedef struct __attribute__((packed)) +{ + //! Total number of startups for this unit. + uint16_t Hourmeter_Startups; +} NVM_Hourmeter_T; + + +/* Include Files */ + +/* Public Variables */ + +extern NVM_EEPROMEntry_T NVM_External_Test; +extern NVM_EEPROMEntry_T NVM_Info; +extern NVM_EEPROMEntry_T NVM_Hardware_Settings; +extern NVM_EEPROMEntry_T NVM_Game_Settings; +extern NVM_EEPROMEntry_T NVM_Hourmeter; + +extern NVM_EEPROMEntry_T * const NVM_ExternalEEPROMEntries[]; +extern const uint8_t NVM_N_EXTERNAL_EEPROM_ENTRIES; + +// Shorthand macros, to save you time. +#define NVM_EXTERNAL_TEST_3 (((NVM_External_Test_T*)NVM_External_Test.Value)->External_Test_3) +#define NVM_EXTERNAL_TEST_3_ENTRY_PTR (&NVM_External_Test) + +#define NVM_EXTERNAL_TEST_4 (((NVM_External_Test_T*)NVM_External_Test.Value)->External_Test_4) +#define NVM_EXTERNAL_TEST_4_ENTRY_PTR (&NVM_External_Test) + +#define NVM_DATE_CODE_AS_YYYYMMDD (((NVM_Info_T*)NVM_Info.Value)->Date_Code_as_YYYYMMDD) +#define NVM_DATE_CODE_AS_YYYYMMDD_ENTRY_PTR (&NVM_Info) + +#define NVM_BARREL_COLOR_ORDER (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Barrel_Color_Order) +#define NVM_BARREL_COLOR_ORDER_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_RECEIVER_COLOR_ORDER (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Receiver_Color_Order) +#define NVM_RECEIVER_COLOR_ORDER_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_DISPLAY_COLOR_ORDER (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Display_Color_Order) +#define NVM_DISPLAY_COLOR_ORDER_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_EFFECTS_COLOR_ORDER (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Effects_Color_Order) +#define NVM_EFFECTS_COLOR_ORDER_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_IS_RIGHT_HANDED (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Is_Right_Handed) +#define NVM_IS_RIGHT_HANDED_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_VOLUME (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Volume) +#define NVM_VOLUME_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_WEAPON_ID (((NVM_Game_Settings_T*)NVM_Game_Settings.Value)->Weapon_ID) +#define NVM_WEAPON_ID_ENTRY_PTR (&NVM_Game_Settings) + +#define NVM_PLAYER_ID (((NVM_Game_Settings_T*)NVM_Game_Settings.Value)->Player_ID) +#define NVM_PLAYER_ID_ENTRY_PTR (&NVM_Game_Settings) + +#define NVM_TEAM_ID (((NVM_Game_Settings_T*)NVM_Game_Settings.Value)->Team_ID) +#define NVM_TEAM_ID_ENTRY_PTR (&NVM_Game_Settings) + +#define NVM_HOURMETER_STARTUPS (((NVM_Hourmeter_T*)NVM_Hourmeter.Value)->Hourmeter_Startups) +#define NVM_HOURMETER_STARTUPS_ENTRY_PTR (&NVM_Hourmeter) + + +#ifdef __cplusplus +} +#endif + +#endif // NVM_EXTERNALEEPROMENTRIES_H + diff --git a/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROM.c b/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROM.c new file mode 100644 index 0000000..5fd56b0 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROM.c @@ -0,0 +1,260 @@ +/** \file + * \brief This file contains functions that manage the on-chip EEPROM. + * + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/* External Variables [Only if necessary!] */ + +/* External Function Prototypes [Only if necessary!] */ + +/* Public Variables */ + +//! Mutex controlling access to the EEPROM to ensure data/CRC integrity. +SemaphoreHandle_t xSemaphoreOnChipEEPROMLock; + +TaskHandle_t NVM_OnChipEEPROM_Task_Handle; + +volatile bool NVM_IsOnChipEEPROMInitialized = false; + +/* Private Variables */ + +static QueueHandle_t xQueueOnChipEEPROM; + +#if CY_PSOC4 +const uint8_t Emulated_EEPROM_Storage[On_Chip_Emulated_EEPROM_PHYSICAL_SIZE] +__ALIGNED(CY_FLASH_SIZEOF_ROW) = {0u}; +#endif // CY_PSOC4 + +/* Private Function Prototypes */ + +/* Inline Functions */ + +#if CY_PSOC4 +//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination. +static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n) +{ + On_Chip_Emulated_EEPROM_Read(source, destination, n); +} + +//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination. +static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n) +{ + On_Chip_Emulated_EEPROM_Write(destination, source, n); +} +#endif // CY_PSOC4 + +#if CY_PSOC5 +//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination. +static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n) +{ + for (uint_fast16_t i = 0; i < n; i++) + { + uint8_t temp = On_Chip_EEPROM_ReadByte(source + i); + *(destination + i) = temp; + } +} + +//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination. +static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n) +{ + for (uint_fast16_t i = 0; i < n; i++) + { + On_Chip_EEPROM_WriteByte(*(source + i), destination + i); + } +} +#endif // CY_PSOC5 + +#if CY_PSOC6 +//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination. +static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n) +{ + cy_en_em_eeprom_status_t result = On_Chip_EEPROM_Read(source, destination, n); + + if (result != CY_EM_EEPROM_SUCCESS) + { + CY_ASSERT(0); + } +} + +//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination. +static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n) +{ + cy_en_em_eeprom_status_t result = On_Chip_EEPROM_Write(destination, source, n); + + if (result != CY_EM_EEPROM_SUCCESS) + { + CY_ASSERT(0); + } +} +#endif // CY_PSOC6 + +/* Public Functions */ + +//! Sets up the on-chip EEPROM, but does not read from it (yet). +void NVM_InitOnChipEEPROM(void) +{ + /// Create a mutex-type semaphore. + xSemaphoreOnChipEEPROMLock = xSemaphoreCreateMutex(); + + if (xSemaphoreOnChipEEPROMLock == NULL) + { + CY_ASSERT(0); + } + + xQueueOnChipEEPROM = xQueueCreate(5, sizeof(uint8_t)); + +#if CY_PSOC4 + On_Chip_Emulated_EEPROM_Init((uint32_t)Emulated_EEPROM_Storage); +#endif // CY_PSOC4 + +#if CY_PSOC5 + On_Chip_EEPROM_Start(); +#endif // CY_PSOC5 + +#if CY_PSOC6 + // From the docs: "For PSoC 6, if Emulated EEPROM is selected for EEPROM storage, the start address will be + // overwritten to some address from Emulated EEPROM flash area." + On_Chip_EEPROM_Init(0); +#endif // CY_PSOC6 +} + +//! Handles the ongoing on-chip EEPROM tasks. +/*! + * First, it loops through all the on-chip EEPROM entries, and reads them in to RAM. + * Then, it priodically loops through all the on-chip EEPROM entries, and saves the ones that have been flagged. + */ +void NVM_OnChipEEPROMTask(void * pvParameters) +{ + portBASE_TYPE xStatus; + static TickType_t xTicksToWait = pdMS_TO_TICKS(NVM_ON_CHIP_EEPROM_TASK_RATE_IN_ms); + + for (uint8_t i = 0; i < NVM_N_ONCHIP_EEPROM_ENTRIES; i++) + { + NVM_CRC_t calculated_crc; + NVM_CRC_t stored_crc = 0; + + EEPROM_read_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size); + EEPROM_read_block((uint8_t *)&stored_crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(NVM_CRC_t)); + + calculated_crc = NVM_CRC_init(); + calculated_crc = NVM_CRC_update(calculated_crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size); + calculated_crc = NVM_CRC_finalize(calculated_crc); + + if (calculated_crc == stored_crc) + { + NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE; + } + else + { + NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_CRC_FAILED; + + COMM_Console_Print_String("[NVMOn "); + COMM_Console_Print_UInt16((uint16_t) i); + COMM_Console_Print_String("] Calculated/Stored CRCs: "); + COMM_Console_Print_UInt16((uint16_t) calculated_crc); + COMM_Console_Print_String("/"); + COMM_Console_Print_UInt16((uint16_t) stored_crc); + COMM_Console_Print_String("\n"); + + COMM_Console_Print_String("[NVMOn "); + COMM_Console_Print_UInt16((uint16_t) i); + COMM_Console_Print_String("] Applying defaults.\n"); + + memcpy(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Default, NVM_OnChipEEPROMEntries[i]->Size); + + // Auto-fix the CRC. + NVM_SaveOnChipEEPROMEntry(NVM_OnChipEEPROMEntries[i]); + } + } + + taskENTER_CRITICAL(); + NVM_IsOnChipEEPROMInitialized = true; + taskEXIT_CRITICAL(); + + while(true) + { + uint8_t dummy; + + // Wait for a call to NVM_SaveOnChipEEPROMEntry(). + xStatus = xQueueReceive(xQueueOnChipEEPROM, &dummy, xTicksToWait); + + if (xStatus == pdPASS) + { + for (uint8_t i = 0; i < NVM_N_ONCHIP_EEPROM_ENTRIES; i++) + { + NVM_CRC_t crc; + +#if (defined CY_PSOC4) || (defined CY_PSOC6) + if (NVM_OnChipEEPROMEntries[i]->State == NVM_STATE_SAVE_REQUESTED) + { + if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE) + { + EEPROM_write_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size); + + // Calculate the CRC. + crc = NVM_CRC_init(); + crc = NVM_CRC_update(crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size); + crc = NVM_CRC_finalize(crc); + + EEPROM_write_block((uint8_t *)&crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(uint16_t)); + NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE; + xSemaphoreGive(xSemaphoreOnChipEEPROMLock); + } + } +#endif // (defined CY_PSOC4) || (defined CY_PSOC6) + +#if CY_PSOC5 + // From the component datasheet: + // "[On_Chip_EEPROM_UpdateTemperature()] updates the store temperature value. This should + // be called anytime the EEPROM is active and temperature may have changed by more than + // 10°C." + if (On_Chip_EEPROM_UpdateTemperature() == CYRET_SUCCESS) + { + if (NVM_OnChipEEPROMEntries[i]->State == NVM_STATE_SAVE_REQUESTED) + { + if (On_Chip_EEPROM_Query() == CYRET_SUCCESS) + { + if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE) + { + EEPROM_write_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size); + + // Calculate the CRC. + crc = NVM_CRC_init(); + crc = NVM_CRC_update(crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size); + crc = NVM_CRC_finalize(crc); + + EEPROM_write_block((uint8_t *)&crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(uint16_t)); + NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE; + xSemaphoreGive(xSemaphoreOnChipEEPROMLock); + } + } + } + } + else + { + vSerialPutString("ERROR: Couldn't update EEPROM temperature!", 80); + } +#endif // CY_PSOC5 + } + } + } +} + +//! Flags the given on-chip EEPROM entry to be saved next time the NVM_OnChipEEPROMTask() is run. +void NVM_SaveOnChipEEPROMEntry(NVM_EEPROMEntry_T * const this) +{ + if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE) + { + this->State = NVM_STATE_SAVE_REQUESTED; + xSemaphoreGive(xSemaphoreOnChipEEPROMLock); + uint8_t dummy = 0; + xQueueSend(xQueueOnChipEEPROM, &dummy, 0); + } +} + +/* Private Functions */ \ No newline at end of file diff --git a/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROM.h b/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROM.h new file mode 100644 index 0000000..325ef39 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROM.h @@ -0,0 +1,42 @@ +/** \file + * \brief This file contains the public interface to the on-chip EEPROM driver. + * + */ + +#ifndef NVM_ONCHIPEEPROM_H +#define NVM_ONCHIPEEPROM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +#define NVM_ON_CHIP_EEPROM_TASK_STACK_SIZE_in_bytes 256 + +//! The time between calls to NVM_OnChipEEPROMTask(). +#define NVM_ON_CHIP_EEPROM_TASK_RATE_IN_ms 2000 + +/* Include Files */ + +/* Public Variables */ + +extern SemaphoreHandle_t xSemaphoreOnChipEEPROMLock; + +//! Handle of the NVM_OnChipEEPROMTask() given when the task was created. +extern TaskHandle_t NVM_OnChipEEPROM_Task_Handle; + +extern volatile bool NVM_IsOnChipEEPROMInitialized; + +/* Public Functions */ +void NVM_InitOnChipEEPROM(void); +void NVM_OnChipEEPROMTask(void * pvParameters); +void NVM_SaveOnChipEEPROMEntry(NVM_EEPROMEntry_T * const this); + +/* Inline Functions */ + +#ifdef __cplusplus +} +#endif + +#endif // NVM_ONCHIPEEPROM_H \ No newline at end of file diff --git a/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROMEntries.c b/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROMEntries.c new file mode 100644 index 0000000..08b72a4 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROMEntries.c @@ -0,0 +1,63 @@ +/* + * __ ________ _____ ______ __ + * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ + * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ + * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ + * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ + * /____/ + * + * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞 + * + */ + +/** \file + * \brief [Autogenerated] This file defines the OnChip EEPROM entries. + * + * \note AUTOGENERATED: This file was generated automatically on Friday, April 28, 2023 at 11:31:31 AM. + * DO NOT MODIFY THIS FILE MANUALLY! + */ + +/* Include Files */ +#include "KTag.h" + +/* EEPROM Entries */ + +/** \defgroup NVM_ONCHIP_EEPROM NVM OnChip EEPROM + * + * The OnChip EEPROM is divided into logical "entries", represented by instances of the #NVM_EEPROMEntry_T type. + * At startup, these entries are loaded into their respective RAM copies by NVM_InitOnChipEEPROM(). The application + * then updates the RAM copies directly, and requests that the NVM_OnChipEEPROMTask() save these back to the EEPROM + * when necessary. + * @{ */ + +static NVM_OnChip_Test_T RAM_OnChip_Test; + +static const NVM_OnChip_Test_T DEFAULT_OnChip_Test = +{ + //! Test Code 1 + .OnChip_Test_1 = UINT16_MAX, + //! Test Code 2 + .OnChip_Test_2 = UINT32_MAX, +}; + +NVM_EEPROMEntry_T NVM_OnChip_Test = +{ + //! Size == sizeof(NVM_OnChip_Test_T) + .Size = 6, + .EE_Address = 0, + .EE_CRC_Address = 6, + .Value = (uint8_t *)&RAM_OnChip_Test, + .Default = (uint8_t *)&DEFAULT_OnChip_Test, + .State = NVM_STATE_UNINITIALIZED +}; + +/** @} */ + +NVM_EEPROMEntry_T * const NVM_OnChipEEPROMEntries[] = +{ + &NVM_OnChip_Test, +}; + +//! Size of the #NVM_OnChipEEPROMEntries array (i.e. the number of OnChip EEPROM entries). +const uint8_t NVM_N_ONCHIP_EEPROM_ENTRIES = (uint8_t) (sizeof(NVM_OnChipEEPROMEntries) / sizeof(NVM_EEPROMEntry_T *)); + diff --git a/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROMEntries.h b/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROMEntries.h new file mode 100644 index 0000000..507737a --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_OnChipEEPROMEntries.h @@ -0,0 +1,60 @@ +/* + * __ ________ _____ ______ __ + * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ + * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ + * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ + * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ + * /____/ + * + * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞 + * + */ + +/** \file + * \brief [Autogenerated] This file declares the OnChip EEPROM entries. + * + * \note AUTOGENERATED: This file was generated automatically on Friday, April 28, 2023 at 11:31:31 AM. + * DO NOT MODIFY THIS FILE MANUALLY! + */ + +#ifndef NVM_ONCHIPEEPROMENTRIES_H +#define NVM_ONCHIPEEPROMENTRIES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +typedef struct __attribute__((packed)) +{ + //! Test Code 1 + uint16_t OnChip_Test_1; + //! Test Code 2 + uint32_t OnChip_Test_2; +} NVM_OnChip_Test_T; + + +/* Include Files */ + +/* Public Variables */ + +extern NVM_EEPROMEntry_T NVM_OnChip_Test; + +extern NVM_EEPROMEntry_T * const NVM_OnChipEEPROMEntries[]; +extern const uint8_t NVM_N_ONCHIP_EEPROM_ENTRIES; + +// Shorthand macros, to save you time. +#define NVM_ONCHIP_TEST_1 (((NVM_OnChip_Test_T*)NVM_OnChip_Test.Value)->OnChip_Test_1) +#define NVM_ONCHIP_TEST_1_ENTRY_PTR (&NVM_OnChip_Test) + +#define NVM_ONCHIP_TEST_2 (((NVM_OnChip_Test_T*)NVM_OnChip_Test.Value)->OnChip_Test_2) +#define NVM_ONCHIP_TEST_2_ENTRY_PTR (&NVM_OnChip_Test) + + +#ifdef __cplusplus +} +#endif + +#endif // NVM_ONCHIPEEPROMENTRIES_H + diff --git a/2020TPCApp1.cydsn/NVM/NVM_Settings.c b/2020TPCApp1.cydsn/NVM/NVM_Settings.c new file mode 100644 index 0000000..4585506 --- /dev/null +++ b/2020TPCApp1.cydsn/NVM/NVM_Settings.c @@ -0,0 +1,125 @@ +/** \file + * \brief This file contains functions that implement the settings interface for SystemK. + * + */ + +/* Include Files */ +#include "KTag.h" + + +SystemKResult_T SETTINGS_get_uint8_t(SystemKSettingID_T id, uint8_t * value) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + switch (id) + { + case SYSTEMK_SETTING_IS_RIGHT_HANDED: + *value = NVM_IS_RIGHT_HANDED; + break; + + case SYSTEMK_SETTING_AUDIO_VOLUME: + *value = NVM_VOLUME; + break; + + case SYSTEMK_SETTING_TEAMID: + *value = NVM_TEAM_ID; + break; + + case SYSTEMK_SETTING_PLAYERID: + *value = NVM_PLAYER_ID; + break; + + case SYSTEMK_SETTING_WEAPONID: + *value = NVM_WEAPON_ID; + break; + + default: + result = SYSTEMK_RESULT_WRONG_DATATYPE; + break; + } + + return result; +} + +SystemKResult_T SETTINGS_set_uint8_t(SystemKSettingID_T id, uint8_t value) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + switch (id) + { + case SYSTEMK_SETTING_IS_RIGHT_HANDED: + NVM_IS_RIGHT_HANDED = value; + break; + + case SYSTEMK_SETTING_AUDIO_VOLUME: + NVM_VOLUME = value; + break; + + case SYSTEMK_SETTING_TEAMID: + NVM_TEAM_ID = value; + break; + + case SYSTEMK_SETTING_PLAYERID: + NVM_PLAYER_ID = value; + break; + + case SYSTEMK_SETTING_WEAPONID: + NVM_WEAPON_ID = value; + break; + + default: + result = SYSTEMK_RESULT_WRONG_DATATYPE; + break; + } + + return result; +} + +SystemKResult_T SETTINGS_get_uint32_t(SystemKSettingID_T id, uint32_t * value) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + switch (id) + { + case SYSTEMK_SETTING_T_START_GAME_in_ms: + *value = CONFIG_KTAG_T_DEFAULT_START_GAME_in_ms; + break; + + default: + result = SYSTEMK_RESULT_WRONG_DATATYPE; + break; + } + + return result; +} + +SystemKResult_T SETTINGS_set_uint32_t(SystemKSettingID_T id, uint32_t value) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + switch (id) + { + case SYSTEMK_SETTING_T_START_GAME_in_ms: + result = SYSTEMK_RESULT_NOT_IMPLEMENTED; + break; + + default: + result = SYSTEMK_RESULT_WRONG_DATATYPE; + break; + } + + return result; +} + +SystemKResult_T SETTINGS_Save(void) +{ +#if (CONFIG__HAS_EXTERNAL_NVM) + NVM_SaveExternalEEPROMEntry(&NVM_Hardware_Settings); + NVM_SaveExternalEEPROMEntry(&NVM_Game_Settings); +#else // CONFIG__HAS_EXTERNAL_NVM + NVM_SaveOnChipEEPROMEntry(&NVM_Hardware_Settings); + NVM_SaveOnChipEEPROMEntry(&NVM_Game_Settings); +#endif // CONFIG__HAS_EXTERNAL_NVM + + return SYSTEMK_RESULT_SUCCESS; +} diff --git a/2020TPCApp1.cydsn/Sample_Tasks.c b/2020TPCApp1.cydsn/Sample_Tasks.c new file mode 100644 index 0000000..46bf192 --- /dev/null +++ b/2020TPCApp1.cydsn/Sample_Tasks.c @@ -0,0 +1,93 @@ +/* Include Files */ +#include "KTag.h" + +TaskHandle_t Sample_Task_Handle; + +// LED Functionality +static void LED_CoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ); +#define LED_COROUTINE_PRIORITY 0 +static const TickType_t Delay_50ms = 50 / portTICK_PERIOD_MS; +static const TickType_t Delay_100ms = 100 / portTICK_PERIOD_MS; +static const TickType_t Delay_600ms = 600 / portTICK_PERIOD_MS; + +// Serial Debug Functionality +static void Serial_Debug_CoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ); +#define SERIAL_DEBUG_COROUTINE_PRIORITY 0 +static const TickType_t Delay_1s = 1000 / portTICK_PERIOD_MS; + +void Sample_Task_Init(void) +{ +} + +//! Sample task: blinks the LED and sends text out on the UART. +/*! + * \param pvParameters (not used) + * \return None (infinite loop) + */ +void Sample_Task(void * pvParameters) +{ + xCoRoutineCreate(LED_CoRoutine, LED_COROUTINE_PRIORITY, 0 ); + xCoRoutineCreate(Serial_Debug_CoRoutine, SERIAL_DEBUG_COROUTINE_PRIORITY, 0 ); + + while (true) + { + vCoRoutineSchedule(); + + // Delay a bit here so as to not starve the idle task. + vTaskDelay(10 / portTICK_PERIOD_MS); + } +} + +//! Blinks the LED. +static void LED_CoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) +{ + crSTART( xHandle ); + + static bool is_startup = false; + + while (true) + { + if (is_startup == false) + { + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 1); + crDELAY(xHandle, Delay_100ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 0); + crDELAY(xHandle, Delay_50ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 1); + crDELAY(xHandle, Delay_100ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 0); + crDELAY(xHandle, Delay_50ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 1); + crDELAY(xHandle, Delay_100ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 0); + + is_startup = true; + } + crDELAY(xHandle, Delay_600ms); + } + + crEND(); +} + +static void Serial_Debug_CoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) +{ + crSTART( xHandle ); + + //static uint32_t i = 0; + + while (true) + { + //Debug_printf("%lu\n", i++); + //vSerialPutString(" * ", 50); + crDELAY(xHandle, Delay_1s); + } + + crEND(); +} + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/Sample_Tasks.h b/2020TPCApp1.cydsn/Sample_Tasks.h new file mode 100644 index 0000000..4d0780a --- /dev/null +++ b/2020TPCApp1.cydsn/Sample_Tasks.h @@ -0,0 +1,9 @@ +#ifndef SAMPLE_TASKS_H +#define SAMPLE_TASKS_H + +extern TaskHandle_t Sample_Task_Handle; + +void Sample_Task_Init(void); +void Sample_Task(void * pvParameters); + +#endif // SAMPLE_TASKS_H diff --git a/2020TPCApp1.cydsn/Switches.c b/2020TPCApp1.cydsn/Switches.c new file mode 100644 index 0000000..8fbdbeb --- /dev/null +++ b/2020TPCApp1.cydsn/Switches.c @@ -0,0 +1,196 @@ +/* Include Files */ +#include "KTag.h" + +TaskHandle_t Switches_Task_Handle; + +#define SWITCHES_TASK_PERIOD_IN_TICKS (100 / portTICK_PERIOD_MS) + +//! Continuously pressing a switch for this length of time will be interpreted as a long press. +/*! + * #Duration_Of_Long_Press_in_Ticks must be an integer multiple of #SWITCHES_TASK_PERIOD_IN_TICKS! + */ +static const TickType_t Duration_Of_Long_Press_in_Ticks = (10 * SWITCHES_TASK_PERIOD_IN_TICKS); + +#if (defined LIL_BRUV) || (defined LITTLE_BOY_BLUE) +static TickType_t Up_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Up_Switch_Time_Released_in_Ticks = 0; +static TickType_t Down_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Down_Switch_Time_Released_in_Ticks = 0; +static TickType_t Forward_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Forward_Switch_Time_Released_in_Ticks = 0; +static TickType_t Backward_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Backward_Switch_Time_Released_in_Ticks = 0; +#elif (defined TWENTY20TPC) +static TickType_t Accessory_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Accessory_Switch_Total_Time_Pressed_in_Ticks = 0; +static TickType_t Accessory_Switch_Time_Released_in_Ticks = 0; +static TickType_t Accessory_Switch_Time_Since_Last_Release_in_Ticks = 0; +#endif // Model + +void Switches_Init(void) +{ + +} + + +//! Reads the hardware switches and creates press and release events. +/*! + * This is a periodic task--see https://www.freertos.org/vtaskdelayuntil.html. + */ +void Switches_Task(void * pvParameters) +{ + TickType_t xLastWakeTime; + + // Initialize the xLastWakeTime variable with the current time. + xLastWakeTime = xTaskGetTickCount(); + + while (true) + { +#if (defined LIL_BRUV) || (defined LITTLE_BOY_BLUE) + if (Cy_GPIO_Read(Pin_Up_PORT, Pin_Up_NUM) == 0) + { + if (Up_Switch_Time_Pressed_in_Ticks == 0) + { + Up_Switch_Time_Released_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_UP_SWITCH_PRESSED, .Data = &Up_Switch_Time_Released_in_Ticks}; + Post_KEvent(&switch_event); + } + else if (Up_Switch_Time_Pressed_in_Ticks == Duration_Of_Long_Press_in_Ticks) + { + KEvent_T switch_event = {.ID = KEVENT_UP_SWITCH_LONG_PRESSED, .Data = &Up_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Up_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + else + { + if (Up_Switch_Time_Released_in_Ticks == 0) + { + Up_Switch_Time_Pressed_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_UP_SWITCH_RELEASED, .Data = &Up_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Up_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + + if (Cy_GPIO_Read(Pin_Down_PORT, Pin_Down_NUM) == 0) + { + if (Down_Switch_Time_Pressed_in_Ticks == 0) + { + Down_Switch_Time_Released_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_DOWN_SWITCH_PRESSED, .Data = &Down_Switch_Time_Released_in_Ticks}; + Post_KEvent(&switch_event); + } + else if (Down_Switch_Time_Pressed_in_Ticks == Duration_Of_Long_Press_in_Ticks) + { + KEvent_T switch_event = {.ID = KEVENT_DOWN_SWITCH_LONG_PRESSED, .Data = &Down_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Down_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + else + { + if (Down_Switch_Time_Released_in_Ticks == 0) + { + Down_Switch_Time_Pressed_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_DOWN_SWITCH_RELEASED, .Data = &Down_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Down_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + + if (Cy_GPIO_Read(Pin_Forward_PORT, Pin_Forward_NUM) == 0) + { + if (Forward_Switch_Time_Pressed_in_Ticks == 0) + { + Forward_Switch_Time_Released_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_FORWARD_SWITCH_PRESSED, .Data = &Forward_Switch_Time_Released_in_Ticks}; + Post_KEvent(&switch_event); + } + else if (Forward_Switch_Time_Pressed_in_Ticks == Duration_Of_Long_Press_in_Ticks) + { + KEvent_T switch_event = {.ID = KEVENT_FORWARD_SWITCH_LONG_PRESSED, .Data = &Forward_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Forward_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + else + { + if (Forward_Switch_Time_Released_in_Ticks == 0) + { + Forward_Switch_Time_Pressed_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_FORWARD_SWITCH_RELEASED, .Data = &Forward_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Forward_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + + if (Cy_GPIO_Read(Pin_Backward_PORT, Pin_Backward_NUM) == 0) + { + if (Backward_Switch_Time_Pressed_in_Ticks == 0) + { + Backward_Switch_Time_Released_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_BACKWARD_SWITCH_PRESSED, .Data = &Backward_Switch_Time_Released_in_Ticks}; + Post_KEvent(&switch_event); + } + else if (Backward_Switch_Time_Pressed_in_Ticks == Duration_Of_Long_Press_in_Ticks) + { + KEvent_T switch_event = {.ID = KEVENT_BACKWARD_SWITCH_LONG_PRESSED, .Data = &Backward_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Backward_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + else + { + if (Backward_Switch_Time_Released_in_Ticks == 0) + { + Backward_Switch_Time_Pressed_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_BACKWARD_SWITCH_RELEASED, .Data = &Backward_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Backward_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } +#elif (defined TWENTY20TPC) + // Use the Remote Trigger pin as the Accessory input, since we never got around to using remote triggers. + if (Cy_GPIO_Read(Pin_Remote_Trigger_PORT, Pin_Remote_Trigger_NUM) == 0) + { + if (Accessory_Switch_Time_Pressed_in_Ticks == 0) + { + Accessory_Switch_Time_Since_Last_Release_in_Ticks = Accessory_Switch_Time_Released_in_Ticks; + KEvent_T switch_event = {.ID = KEVENT_ACCESSORY_SWITCH_PRESSED, .Data = (void *) pdTICKS_TO_MS(Accessory_Switch_Time_Since_Last_Release_in_Ticks)}; + Post_KEvent(&switch_event); + Accessory_Switch_Time_Released_in_Ticks = 0; + } + if ((UINT32_MAX - Accessory_Switch_Time_Pressed_in_Ticks) > SWITCHES_TASK_PERIOD_IN_TICKS) + { + Accessory_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + } + else + { + if (Accessory_Switch_Time_Released_in_Ticks == 0) + { + Accessory_Switch_Total_Time_Pressed_in_Ticks = Accessory_Switch_Time_Pressed_in_Ticks; + KEvent_T switch_event = {.ID = KEVENT_ACCESSORY_SWITCH_RELEASED, .Data = (void *) pdTICKS_TO_MS(Accessory_Switch_Total_Time_Pressed_in_Ticks)}; + Post_KEvent(&switch_event); + Accessory_Switch_Time_Pressed_in_Ticks = 0; + } + if ((UINT32_MAX - Accessory_Switch_Time_Released_in_Ticks) > SWITCHES_TASK_PERIOD_IN_TICKS) + { + Accessory_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + } +#endif // Model + + // Wait for the next cycle. + vTaskDelayUntil(&xLastWakeTime, SWITCHES_TASK_PERIOD_IN_TICKS); + } +} diff --git a/2020TPCApp1.cydsn/Switches.h b/2020TPCApp1.cydsn/Switches.h new file mode 100644 index 0000000..5472fdf --- /dev/null +++ b/2020TPCApp1.cydsn/Switches.h @@ -0,0 +1,9 @@ +#ifndef SWITCHES_H +#define SWITCHES_H + +extern TaskHandle_t Switches_Task_Handle; + +void Switches_Init(void); +void Switches_Task(void * pvParameters); + +#endif // SWITCHES_H diff --git a/2020TPCApp1.cydsn/SystemK b/2020TPCApp1.cydsn/SystemK new file mode 160000 index 0000000..4fe072f --- /dev/null +++ b/2020TPCApp1.cydsn/SystemK @@ -0,0 +1 @@ +Subproject commit 4fe072f2d3280b19aa53e197bd22ec44b174ff88 diff --git a/2020TPCApp1.cydsn/Tag_Sensors.c b/2020TPCApp1.cydsn/Tag_Sensors.c new file mode 100644 index 0000000..2b535e1 --- /dev/null +++ b/2020TPCApp1.cydsn/Tag_Sensors.c @@ -0,0 +1,582 @@ +/* Include Files */ +#include "KTag.h" + +TaskHandle_t Tag_Sensors_Task_Handle; + +//#define DEBUG_TAG_SENSORS + +#define MAX_RX_PULSES (2 * MAX_PULSES) + +typedef enum +{ + FALLING_EDGE, + RISING_EDGE +} EdgeDirection_T; + +static volatile uint32_t LocalIncomingPulseDurations[MAX_RX_PULSES]; +static volatile uint32_t RemoteIncomingPulseDurations[MAX_RX_PULSES]; +static volatile uint16_t LocalPulseIndex = 0; +static volatile uint16_t RemotePulseIndex = 0; +static volatile uint16_t NumberOfLocalIncomingPulses = 0; +static volatile uint16_t NumberOfRemoteIncomingPulses = 0; +static volatile TagSensorLocation_T LocalActiveSensor = TAG_SENSOR_NONE; +static uint32_t LocalProcessingPulseDurations[MAX_RX_PULSES]; +static uint32_t RemoteProcessingPulseDurations[MAX_RX_PULSES]; +static uint16_t NumberOfLocalProcessingPulses = 0; +static uint16_t NumberOfRemoteProcessingPulses = 0; +static TimedPulseTrain_T LocalProcessingPulses; +static TimedPulseTrain_T RemoteProcessingPulses; +static TagSensorLocation_T LocalProcessingSensor = TAG_SENSOR_NONE; +static volatile EdgeDirection_T LocalExpectedEdgeDirection = FALLING_EDGE; +static volatile EdgeDirection_T RemoteExpectedEdgeDirection = FALLING_EDGE; + + +void On_Forward_Tag_Sensor_Rising_Edge(); +void On_Forward_Tag_Sensor_Falling_Edge(); +void On_Left_Tag_Sensor_Rising_Edge(); +void On_Left_Tag_Sensor_Falling_Edge(); +void On_Right_Tag_Sensor_Rising_Edge(); +void On_Right_Tag_Sensor_Falling_Edge(); +void On_Remote_Tag_Sensor_Rising_Edge(); +void On_Remote_Tag_Sensor_Falling_Edge(); +void On_Local_Tag_Sensor_Bit_Stream_Timer(); +void On_Remote_Tag_Sensor_Bit_Stream_Timer(); + +QueueHandle_t xQueueTagSensors; + +#ifdef DEBUG_TAG_SENSORS +static char8 buffer[30]; +#endif // DEBUG_TAG_SENSORS + +inline static void AppendLocalPulse(uint32_t duration) +{ + LocalIncomingPulseDurations[LocalPulseIndex] = duration; + + if (LocalPulseIndex < (MAX_RX_PULSES - 1)) + { + LocalPulseIndex++; + } +} + +inline static void AppendRemotePulse(uint32_t duration) +{ + RemoteIncomingPulseDurations[RemotePulseIndex] = duration; + + if (RemotePulseIndex < (MAX_RX_PULSES - 1)) + { + RemotePulseIndex++; + } +} + +inline static void EnableAllLocalEdgeISRs(void) +{ + NVIC_EnableIRQ(Forward_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Forward_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Left_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Right_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Right_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void EnableAllRemoteEdgeISRs(void) +{ + NVIC_EnableIRQ(Remote_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Remote_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllLocalRisingEdgeISRs(void) +{ + NVIC_DisableIRQ(Forward_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_DisableIRQ(Left_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_DisableIRQ(Right_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllRemoteRisingEdgeISRs(void) +{ + NVIC_DisableIRQ(Remote_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllLocalFallingEdgeISRs(void) +{ + NVIC_DisableIRQ(Forward_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_DisableIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_DisableIRQ(Right_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllRemoteFallingEdgeISRs(void) +{ + NVIC_DisableIRQ(Remote_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllLocalEdgeISRs(void) +{ + DisableAllLocalRisingEdgeISRs(); + DisableAllLocalFallingEdgeISRs(); +} + +inline static void DisableAllRemoteEdgeISRs(void) +{ + DisableAllRemoteRisingEdgeISRs(); + DisableAllRemoteFallingEdgeISRs(); +} + +inline static void ClearAllPendingLocalEdgeISRs(void) +{ + NVIC_ClearPendingIRQ(Forward_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Forward_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Right_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Right_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void ClearAllPendingRemoteEdgeISRs(void) +{ + NVIC_ClearPendingIRQ(Remote_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Remote_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +void Tag_Sensors_Init(void) +{ + // Register the Local ISRs. + Cy_SysInt_Init(&Forward_Tag_Sensor_Rising_Edge_ISR_cfg, On_Forward_Tag_Sensor_Rising_Edge); + Cy_SysInt_Init(&Forward_Tag_Sensor_Falling_Edge_ISR_cfg, On_Forward_Tag_Sensor_Falling_Edge); + Cy_SysInt_Init(&Left_Tag_Sensor_Rising_Edge_ISR_cfg, On_Left_Tag_Sensor_Rising_Edge); + Cy_SysInt_Init(&Left_Tag_Sensor_Falling_Edge_ISR_cfg, On_Left_Tag_Sensor_Falling_Edge); + Cy_SysInt_Init(&Right_Tag_Sensor_Rising_Edge_ISR_cfg, On_Right_Tag_Sensor_Rising_Edge); + Cy_SysInt_Init(&Right_Tag_Sensor_Falling_Edge_ISR_cfg, On_Right_Tag_Sensor_Falling_Edge); + Cy_SysInt_Init(&Local_Tag_Sensor_Bit_Stream_Timer_Interrupt_cfg, On_Local_Tag_Sensor_Bit_Stream_Timer); + + // Register the Remote ISRs. + Cy_SysInt_Init(&Remote_Tag_Sensor_Rising_Edge_ISR_cfg, On_Remote_Tag_Sensor_Rising_Edge); + Cy_SysInt_Init(&Remote_Tag_Sensor_Falling_Edge_ISR_cfg, On_Remote_Tag_Sensor_Falling_Edge); + Cy_SysInt_Init(&Remote_Tag_Sensor_Bit_Stream_Timer_Interrupt_cfg, On_Remote_Tag_Sensor_Bit_Stream_Timer); + + // Enable the forward, left, right, and remote sensors. + Tag_Sensor_Register_Write(0xFF - 0x0F); + + xQueueTagSensors = xQueueCreate(5, sizeof(TagSensorsAction_T)); + + // Enable the timers. + NVIC_EnableIRQ(Local_Tag_Sensor_Bit_Stream_Timer_Interrupt_cfg.intrSrc); + NVIC_EnableIRQ(Remote_Tag_Sensor_Bit_Stream_Timer_Interrupt_cfg.intrSrc); + + // Enable the sensors. + EnableAllLocalEdgeISRs(); + EnableAllRemoteEdgeISRs(); + +} + +void Tag_Sensors_Task(void * pvParameters) +{ + portBASE_TYPE xStatus; + + while (true) + { + TagSensorsAction_T action; + + xStatus = xQueueReceive(xQueueTagSensors, &action, 0); + + if (xStatus == pdPASS) + { + switch (action) + { + case TAG_SENSOR_PROCESS_LOCAL_BUFFER: + { + for (uint8_t i = 0; i < NumberOfLocalIncomingPulses; i++) + { + LocalProcessingPulseDurations[i] = LocalIncomingPulseDurations[i]; + } + NumberOfLocalProcessingPulses = NumberOfLocalIncomingPulses; + NumberOfLocalIncomingPulses = 0; + LocalProcessingSensor = LocalActiveSensor; + LocalActiveSensor = TAG_SENSOR_NONE; + EnableAllLocalEdgeISRs(); + +#ifdef DEBUG_TAG_SENSORS + COMM_Console_Print_String("\n"); + + switch (LocalProcessingSensor) + { + case TAG_SENSOR_FORWARD: + COMM_Console_Print_String("Tag Rx'd FORWARD\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + break; + + case TAG_SENSOR_LEFT: + COMM_Console_Print_String("Tag Rx'd LEFT\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + break; + + case TAG_SENSOR_RIGHT: + COMM_Console_Print_String("Tag Rx'd RIGHT\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + break; + + default: + case TAG_SENSOR_REMOTE: + case TAG_SENSOR_NONE: + break; + } + + for (uint_fast16_t i = 0; i < NumberOfLocalProcessingPulses; i++) + { + // Even pulses are marks; odd pulses are spaces. + if ((i % 2) == 0) + { + COMM_Console_Print_String("{.symbol = MARK, .time = "); + sprintf(buffer, "%lu}, // %d\n", LocalProcessingPulseDurations[i], i); + COMM_Console_Print_String(buffer); + vTaskDelay(pdMS_TO_TICKS(10)); + } + // A falling edge is the end of space. + else + { + COMM_Console_Print_String("{.symbol = SPACE, .time = "); + sprintf(buffer, "%lu}, // %d\n", LocalProcessingPulseDurations[i], i); + COMM_Console_Print_String(buffer); + vTaskDelay(pdMS_TO_TICKS(10)); + } + } +#endif // DEBUG_TAG_SENSORS + + LocalProcessingPulses.count = NumberOfLocalProcessingPulses; + for (uint_fast16_t i = 0; (i < NumberOfLocalProcessingPulses) && (i < MAX_RX_PULSES); i++) + { + if ((i % 2) == 0) + { + LocalProcessingPulses.bitstream[i].symbol = MARK; + } + else + { + LocalProcessingPulses.bitstream[i].symbol = SPACE; + } + LocalProcessingPulses.bitstream[i].duration = LocalProcessingPulseDurations[i]; + } + LocalProcessingPulses.bitstream[NumberOfLocalProcessingPulses].duration = LAST_PULSE; + LocalProcessingPulses.receiver = LocalProcessingSensor; + + DecodedPacket_T * result = PROTOCOLS_MaybeDecodePacket(&LocalProcessingPulses); + + if (result != NULL) + { + if (result->Generic.type == DECODED_PACKET_TYPE_TAG_RECEIVED) + { + KEvent_T tag_received_event = {.ID = KEVENT_TAG_RECEIVED, .Data = result}; + Post_KEvent(&tag_received_event); + } + else if (result->Generic.type == DECODED_PACKET_TYPE_COMMAND_RECEIVED) + { + KEvent_T command_received_event = {.ID = KEVENT_COMMAND_RECEIVED, .Data = result}; + Post_KEvent(&command_received_event); + } + } + else + { + KEvent_T near_miss_event = {.ID = KEVENT_NEAR_MISS, .Data = NULL}; + Post_KEvent(&near_miss_event); + } + } + break; + + case TAG_SENSOR_PROCESS_REMOTE_BUFFER: + { + for (uint8_t i = 0; i < NumberOfRemoteIncomingPulses; i++) + { + RemoteProcessingPulseDurations[i] = RemoteIncomingPulseDurations[i]; + } + NumberOfRemoteProcessingPulses = NumberOfRemoteIncomingPulses; + NumberOfRemoteIncomingPulses = 0; + EnableAllRemoteEdgeISRs(); + +#ifdef DEBUG_TAG_SENSORS + COMM_Console_Print_String("\n"); + + COMM_Console_Print_String("Tag Rx'd REMOTE\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + + for (uint_fast16_t i = 0; i < NumberOfRemoteProcessingPulses; i++) + { + // Even pulses are marks; odd pulses are spaces. + if ((i % 2) == 0) + { + COMM_Console_Print_String("{.symbol = MARK, .time = "); + sprintf(buffer, "%lu}, // %d\n", RemoteProcessingPulseDurations[i], i); + COMM_Console_Print_String(buffer); + vTaskDelay(pdMS_TO_TICKS(10)); + } + // A falling edge is the end of space. + else + { + COMM_Console_Print_String("{.symbol = SPACE, .time = "); + sprintf(buffer, "%lu}, // %d\n", RemoteProcessingPulseDurations[i], i); + COMM_Console_Print_String(buffer); + vTaskDelay(pdMS_TO_TICKS(10)); + } + } +#endif // DEBUG_TAG_SENSORS + RemoteProcessingPulses.count = NumberOfRemoteProcessingPulses; + for (uint_fast16_t i = 0; (i < NumberOfRemoteProcessingPulses) && (i < MAX_RX_PULSES); i++) + { + if ((i % 2) == 0) + { + RemoteProcessingPulses.bitstream[i].symbol = MARK; + } + else + { + RemoteProcessingPulses.bitstream[i].symbol = SPACE; + } + RemoteProcessingPulses.bitstream[i].duration = RemoteProcessingPulseDurations[i]; + } + RemoteProcessingPulses.bitstream[NumberOfRemoteProcessingPulses].duration = LAST_PULSE; + RemoteProcessingPulses.receiver = TAG_SENSOR_REMOTE; + + DecodedPacket_T * result = PROTOCOLS_MaybeDecodePacket(&RemoteProcessingPulses); + + if (result != NULL) + { + if (result->Generic.type == DECODED_PACKET_TYPE_TAG_RECEIVED) + { + KEvent_T tag_received_event = {.ID = KEVENT_TAG_RECEIVED, .Data = result}; + Post_KEvent(&tag_received_event); + } + else if (result->Generic.type == DECODED_PACKET_TYPE_COMMAND_RECEIVED) + { + KEvent_T command_received_event = {.ID = KEVENT_COMMAND_RECEIVED, .Data = result}; + Post_KEvent(&command_received_event); + } + } + else + { + KEvent_T near_miss_event = {.ID = KEVENT_NEAR_MISS, .Data = NULL}; + Post_KEvent(&near_miss_event); + } + } + break; + + default: + break; + } + } + + vTaskDelay(100 / portTICK_PERIOD_MS); + } +} + +// A rising edge means the IR carrier frequency is no longer detected. +void On_Forward_Tag_Sensor_Rising_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (LocalActiveSensor == TAG_SENSOR_FORWARD) + { + if (LocalExpectedEdgeDirection == RISING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Forward_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + + AppendLocalPulse(counter); + LocalExpectedEdgeDirection = FALLING_EDGE; + } + } +} + +// A falling edge means the IR carrier frequency has been detected. +void On_Forward_Tag_Sensor_Falling_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if ((LocalActiveSensor == TAG_SENSOR_FORWARD) || (LocalActiveSensor == TAG_SENSOR_NONE)) + { + if (LocalExpectedEdgeDirection == FALLING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Forward_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + + if (LocalPulseIndex == 0) + { + Local_Tag_Sensor_Bit_Stream_Timer_Start(); + LocalActiveSensor = TAG_SENSOR_FORWARD; + } + else + { + AppendLocalPulse(counter); + } + LocalExpectedEdgeDirection = RISING_EDGE; + } + } +} + +// A rising edge means the IR carrier frequency is no longer detected. +void On_Left_Tag_Sensor_Rising_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (LocalActiveSensor == TAG_SENSOR_LEFT) + { + if (LocalExpectedEdgeDirection == RISING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + + AppendLocalPulse(counter); + LocalExpectedEdgeDirection = FALLING_EDGE; + } + } +} + +// A falling edge means the IR carrier frequency has been detected. +void On_Left_Tag_Sensor_Falling_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if ((LocalActiveSensor == TAG_SENSOR_LEFT) || (LocalActiveSensor == TAG_SENSOR_NONE)) + { + if (LocalExpectedEdgeDirection == FALLING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + + if (LocalPulseIndex == 0) + { + Local_Tag_Sensor_Bit_Stream_Timer_Start(); + LocalActiveSensor = TAG_SENSOR_LEFT; + } + else + { + AppendLocalPulse(counter); + } + LocalExpectedEdgeDirection = RISING_EDGE; + } + } +} + +// A rising edge means the IR carrier frequency is no longer detected. +void On_Right_Tag_Sensor_Rising_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (LocalActiveSensor == TAG_SENSOR_RIGHT) + { + if (LocalExpectedEdgeDirection == RISING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Right_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + + AppendLocalPulse(counter); + LocalExpectedEdgeDirection = FALLING_EDGE; + } + } +} + +// A falling edge means the IR carrier frequency has been detected. +void On_Right_Tag_Sensor_Falling_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if ((LocalActiveSensor == TAG_SENSOR_RIGHT) || (LocalActiveSensor == TAG_SENSOR_NONE)) + { + if (LocalExpectedEdgeDirection == FALLING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + + if (LocalPulseIndex == 0) + { + Local_Tag_Sensor_Bit_Stream_Timer_Start(); + LocalActiveSensor = TAG_SENSOR_RIGHT; + } + else + { + AppendLocalPulse(counter); + } + LocalExpectedEdgeDirection = RISING_EDGE; + } + } +} + +// A rising edge means the IR carrier frequency is no longer detected. +void On_Remote_Tag_Sensor_Rising_Edge() +{ + uint32_t counter = Remote_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (RemoteExpectedEdgeDirection == RISING_EDGE) + { + Remote_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Remote_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + + AppendRemotePulse(counter); + RemoteExpectedEdgeDirection = FALLING_EDGE; + } +} + +// A falling edge means the IR carrier frequency has been detected. +void On_Remote_Tag_Sensor_Falling_Edge() +{ + uint32_t counter = Remote_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (RemoteExpectedEdgeDirection == FALLING_EDGE) + { + Remote_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Remote_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + + if (RemotePulseIndex == 0) + { + Remote_Tag_Sensor_Bit_Stream_Timer_Start(); + } + else + { + AppendRemotePulse(counter); + } + RemoteExpectedEdgeDirection = RISING_EDGE; + } +} + +void On_Local_Tag_Sensor_Bit_Stream_Timer() +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + // Read and clear the interrupt status. + uint32_t status = Local_Tag_Sensor_Bit_Stream_Timer_GetInterruptStatus(); + Local_Tag_Sensor_Bit_Stream_Timer_ClearInterrupt(CY_TCPWM_INT_ON_TC); + + if (status & CY_TCPWM_INT_ON_TC) + { + // The timer expired. + Local_Tag_Sensor_Bit_Stream_Timer_TriggerStop(); + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NumberOfLocalIncomingPulses = LocalPulseIndex; + LocalPulseIndex = 0; + DisableAllLocalEdgeISRs(); + LocalExpectedEdgeDirection = FALLING_EDGE; + const TagSensorsAction_T action = TAG_SENSOR_PROCESS_LOCAL_BUFFER; + xQueueSendFromISR(xQueueTagSensors, &action, &xHigherPriorityTaskWoken); + } + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + +void On_Remote_Tag_Sensor_Bit_Stream_Timer() +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + // Read and clear the interrupt status. + uint32_t status = Remote_Tag_Sensor_Bit_Stream_Timer_GetInterruptStatus(); + Remote_Tag_Sensor_Bit_Stream_Timer_ClearInterrupt(CY_TCPWM_INT_ON_TC); + + if (status & CY_TCPWM_INT_ON_TC) + { + // The timer expired. + Remote_Tag_Sensor_Bit_Stream_Timer_TriggerStop(); + Remote_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NumberOfRemoteIncomingPulses = RemotePulseIndex; + RemotePulseIndex = 0; + DisableAllRemoteEdgeISRs(); + RemoteExpectedEdgeDirection = FALLING_EDGE; + const TagSensorsAction_T action = TAG_SENSOR_PROCESS_REMOTE_BUFFER; + xQueueSendFromISR(xQueueTagSensors, &action, &xHigherPriorityTaskWoken); + } + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + diff --git a/2020TPCApp1.cydsn/Tag_Sensors.h b/2020TPCApp1.cydsn/Tag_Sensors.h new file mode 100644 index 0000000..d32d049 --- /dev/null +++ b/2020TPCApp1.cydsn/Tag_Sensors.h @@ -0,0 +1,16 @@ +#ifndef TAG_SENSORS_H +#define TAG_SENSORS_H + + +extern TaskHandle_t Tag_Sensors_Task_Handle; + +void Tag_Sensors_Init(void); +void Tag_Sensors_Task(void * pvParameters); + +typedef enum +{ + TAG_SENSOR_PROCESS_LOCAL_BUFFER, + TAG_SENSOR_PROCESS_REMOTE_BUFFER +} TagSensorsAction_T; + +#endif // TAG_SENSORS_H \ No newline at end of file diff --git a/2020TPCApp1.cydsn/TopDesign/TopDesign.cysch b/2020TPCApp1.cydsn/TopDesign/TopDesign.cysch new file mode 100644 index 0000000000000000000000000000000000000000..1c3e630cefd6aa3b001f25cfc397d88620cf4f49 GIT binary patch literal 648476 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Increments a value using modular arithmetic. +/*! + * \param value the value to be incremented + * \param modulus the modulus to use + * \return (value + 1) modulo modulus + */ +inline uint16_t ModuloIncrement(const uint16_t value, const uint16_t modulus) +{ + uint16_t nextValue = value + 1; + if (nextValue >= modulus) + { + nextValue = 0; + } + return (nextValue); +} + +//! Initializes the circular buffer, and clears the flags. +/*! + * \param this pointer to the circular buffer in question + * \param buffer pointer to the memory allocated to store this circular buffer + * \param size size (in bytes) of this circular buffer + */ +void UTIL_InitCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t * buffer, uint16_t size) +{ + this->buffer = buffer; + this->size = size; + this->head = 0; + this->tail = 0; + this->count = 0; + // Note that there is no need to zero out the actual buffer, + // since it will be overwritten when values are added. +} + +//! Adds a value to the end of the circular buffer. +/*! + * If the buffer is full, the value is dropped and the overflow flag is set. + * + * \param this pointer to the circular buffer in question + * \param value the value to be added to the buffer + */ +UTIL_CircularBufferResult_T UTIL_PushToCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t value) +{ + UTIL_CircularBufferResult_T result = UTIL_CIRCULARBUFFERRESULT_UNKNOWN; + + //UBaseType_t uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + portDISABLE_INTERRUPTS(); + + if (this->count < this->size) + { + this->buffer[this->head] = value; + this->head = ModuloIncrement(this->head, this->size); + this->count++; + result = UTIL_CIRCULARBUFFERRESULT_SUCCESS; + } + else + { + result = UTIL_CIRCULARBUFFERRESULT_ERROR_OVERFLOW; + } + + portENABLE_INTERRUPTS(); + //taskEXIT_CRITICAL_FROM_ISR(uxSavedInterruptStatus); + + return result; +} + +//! Retrieves a value from the beginning of the circular buffer (FIFO). +/*! + * If the buffer is empty, zero is returned and the underflow flag is set. + * + * \param this pointer to the circular buffer in question + * \return the oldest value in the buffer + */ +UTIL_CircularBufferResult_T UTIL_PopFromCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t * const value) +{ + UTIL_CircularBufferResult_T result = UTIL_CIRCULARBUFFERRESULT_UNKNOWN; + + //UBaseType_t uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + portDISABLE_INTERRUPTS(); + + if (this->count > 0) + { + *value = this->buffer[this->tail]; + this->tail = ModuloIncrement(this->tail, this->size); + this->count--; + result = UTIL_CIRCULARBUFFERRESULT_SUCCESS; + } + else + { + *value = 0; + result = UTIL_CIRCULARBUFFERRESULT_ERROR_UNDERFLOW; + } + + portENABLE_INTERRUPTS(); + //taskEXIT_CRITICAL_FROM_ISR(uxSavedInterruptStatus); + + return result; +} + +//! Determines whether or not the circular buffer is empty. +/*! + * \param this pointer to the circular buffer in question + * \return true if the buffer is empty; false otherwise + */ +bool UTIL_IsCircularBufferEmpty(UTIL_CircularBuffer_T * const this) +{ + bool result = false; + + if (this->count == 0) + { + result = true; + } + + return result; +} + +//! Determines whether or not the circular buffer is full. +/*! + * \param this pointer to the circular buffer in question + * \return true if the buffer is full; false otherwise + */ +bool UTIL_IsCircularBufferFull(UTIL_CircularBuffer_T * const this) +{ + bool result = false; + + if (this->count >= this->size) + { + result = true; + } + + return result; +} diff --git a/2020TPCApp1.cydsn/UTIL/UTIL_CircularBuffer.h b/2020TPCApp1.cydsn/UTIL/UTIL_CircularBuffer.h new file mode 100644 index 0000000..1e5fa9b --- /dev/null +++ b/2020TPCApp1.cydsn/UTIL/UTIL_CircularBuffer.h @@ -0,0 +1,41 @@ +/** \file + * \brief This file contains definitions for a circular buffer. + * + */ + +#ifndef UTIL_CIRCULARBUFFER_H +#define UTIL_CIRCULARBUFFER_H + +/* Definitions */ + +typedef enum +{ + //! The result could not be determined. + UTIL_CIRCULARBUFFERRESULT_UNKNOWN = 0, + //! The requested action completed successfully. + UTIL_CIRCULARBUFFERRESULT_SUCCESS, + //! There is no more room in the buffer. + UTIL_CIRCULARBUFFERRESULT_ERROR_OVERFLOW, + //! There is no data left in the buffer. + UTIL_CIRCULARBUFFERRESULT_ERROR_UNDERFLOW +} UTIL_CircularBufferResult_T; + +//! Circular buffer data structure. +typedef struct +{ + uint8_t * buffer; + uint16_t size; + volatile uint16_t head; + volatile uint16_t tail; + volatile uint16_t count; +} UTIL_CircularBuffer_T; + +/* Function Declarations */ + +void UTIL_InitCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t * buffer, uint16_t size); +UTIL_CircularBufferResult_T UTIL_PushToCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t value); +UTIL_CircularBufferResult_T UTIL_PopFromCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t * const value); +bool UTIL_IsCircularBufferEmpty(UTIL_CircularBuffer_T * const this); +bool UTIL_IsCircularBufferFull(UTIL_CircularBuffer_T * const this); + +#endif // UTIL_CIRCULARBUFFER_H diff --git a/2020TPCApp1.cydsn/common.h b/2020TPCApp1.cydsn/common.h new file mode 100644 index 0000000..be6c623 --- /dev/null +++ b/2020TPCApp1.cydsn/common.h @@ -0,0 +1,94 @@ +/******************************************************************************* +* File Name: common.h +* +* Version 1.0 +* +* Description: +* Contains the function prototypes and constants available to the example +* project. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifndef COMMON_H +#define COMMON_H + +#include +#include + +/*************************************** +* Conditional Compilation Parameters +***************************************/ +#define ENABLED (1u) +#define DISABLED (0u) +#define DEBUG_UART_ENABLED ENABLED + + +/*************************************** +* API Constants +***************************************/ +#define ADV_TIMER_TIMEOUT (1u) /* Сounts in seconds */ +#define SW2_PRESS_TIME_DEL_BOND_LIST (0x04u) + +/* BAS service defines */ +#define BATTERY_TIMEOUT (30u) /* Battery simulation timeout */ + +/*************************************** +* External Function Prototypes +***************************************/ +int HostMain(void); + +/* Function prototypes from debug.c */ +void ShowValue(cy_stc_ble_gatt_value_t *value); +char HexToAscii(uint8_t value, uint8_t nibble); +void Set32ByPtr(uint8_t ptr[], uint32_t value); +void PrintStackVersion(void); +void PrintApiResult(cy_en_ble_api_result_t apiResult); +void ShowError(void); + +/* Function prototypes from bond.c */ +void App_DisplayBondList(void); +void App_RemoveDevicesFromBondListBySW2Press(uint32_t seconds); +void App_RemoveDevicesFromBondList(void); +void App_SetRemoveBondListFlag(void); +bool App_IsRemoveBondListFlag(void); +bool App_IsDeviceInBondList(uint32_t bdHandle); +uint32_t App_GetCountOfBondedDevices(void); + + +/*************************************** +* UART_DEB Macros / prototypes +***************************************/ +#if (DEBUG_UART_ENABLED == ENABLED) + #define DBG_PRINTF(...) (printf(__VA_ARGS__)) + #define UART_DEB_PUT_CHAR(...) while(1UL != UART_DEB_Put(__VA_ARGS__)) + #define UART_DEB_GET_CHAR(...) (UART_DEB_Get()) + #define UART_DEB_IS_TX_COMPLETE(...) (UART_DEB_IsTxComplete()) + #define UART_DEB_WAIT_TX_COMPLETE(...) while(UART_DEB_IS_TX_COMPLETE() == 0) ; + #define UART_DEB_SCB_CLEAR_RX_FIFO(...) (Cy_SCB_ClearRxFifo(UART_DEB_SCB__HW)) + #define UART_START(...) (UART_DEB_Start(__VA_ARGS__)) +#else + #define DBG_PRINTF(...) + #define UART_DEB_PUT_CHAR(...) + #define UART_DEB_GET_CHAR(...) (0u) + #define UART_DEB_IS_TX_COMPLETE(...) (1u) + #define UART_DEB_WAIT_TX_COMPLETE(...) (0u) + #define UART_DEB_SCB_CLEAR_RX_FIFO(...) (0u) + #define UART_START(...) +#endif /* (DEBUG_UART_ENABLED == ENABLED) */ + +#define UART_DEB_NO_DATA (char8) CY_SCB_UART_RX_NO_DATA + + +/*************************************** +* External data references +***************************************/ +extern cy_stc_ble_conn_handle_t appConnHandle; + + +#endif /* COMMON_H */ + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.icf b/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.icf new file mode 100644 index 0000000..71ba887 --- /dev/null +++ b/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.icf @@ -0,0 +1,218 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.icf +* \version 2.20 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.ld b/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.ld new file mode 100644 index 0000000..90fb447 --- /dev/null +++ b/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.ld @@ -0,0 +1,402 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.ld +* \version 2.20 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x24000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x4000 /* 16 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.scat b/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.scat new file mode 100644 index 0000000..6c49340 --- /dev/null +++ b/2020TPCApp1.cydsn/cy8c6xx7_cm0plus.scat @@ -0,0 +1,207 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm0plus.scat +;* \version 2.20 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00024000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_FLASH FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.icf b/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.icf new file mode 100644 index 0000000..0f831e7 --- /dev/null +++ b/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,219 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.icf +* \version 2.20 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +place at start of IROM1_region { block RO }; +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.ld b/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.ld new file mode 100644 index 0000000..54e5e5e --- /dev/null +++ b/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,408 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.20 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x23800 + flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14004000, LENGTH = 0x4000 /* 16 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.scat b/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.scat new file mode 100644 index 0000000..d45ccea --- /dev/null +++ b/2020TPCApp1.cydsn/cy8c6xx7_cm4_dual.scat @@ -0,0 +1,213 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.scat +;* \version 2.20 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08024000 +#define RAM_SIZE 0x00023800 +; Flash +#define FLASH_START 0x10080000 +#define FLASH_SIZE 0x00080000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_FLASH FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/cy_ble_config.h b/2020TPCApp1.cydsn/cy_ble_config.h new file mode 100644 index 0000000..2f382ef --- /dev/null +++ b/2020TPCApp1.cydsn/cy_ble_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** +* \file cy_ble_config.h +* \version 2.80 +* +* \brief +* The user BLE configuration file. Allows redefining the configuration #define(s) +* generated by the BLE customizer. +* +******************************************************************************** +* \copyright +* Copyright 2017-2023, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef CY_BLE_CONF_H +#define CY_BLE_CONF_H + +#include "ble/cy_ble_defines.h" + +/** + * The BLE_config.h file is generated by the BLE customizer and includes all common + * configuration defines (CY_BLE_CONFIG_***). + */ +#include "BLE_config.h" + +#include +#ifndef CY_IP_MXBLESS + #error "The BLE middleware is not supported on this device" +#endif + +/** + * The BLE Interrupt Notification Feature - Exposes BLE interrupt notifications + * to an application that indicates a different link layer and radio state + * transition to the user from the BLESS interrupt context. + * This callback is triggered at the beginning of a received BLESS interrupt + * (based on the registered interrupt mask). After this feature is enabled, + * the following APIs are available: + * Cy_BLE_RegisterInterruptCallback() and Cy_BLE_UnRegisterInterruptCallback(). + * + * The valid value: 1u - enable / 0u - disable. + * + * BLE Dual mode requires an additional define IPC channel and IPC Interrupt + * structure to send notification from the controller core to host core. + * Use the following defines: + * #define CY_BLE_INTR_NOTIFY_IPC_CHAN (9..15) + * #define CY_BLE_INTR_NOTIFY_IPC_INTR (9..15) + * #define CY_BLE_INTR_NOTIFY_IPC_INTR_PRIOR (0..7) + */ +#define CY_BLE_INTR_NOTIFY_FEATURE_ENABLE (0u) + + +/** + * To redefine the config #define(s) generated by the BLE customizer, + * use the construction #undef... #define. + * + * #undef CY_BLE_CONFIG_ENABLE_LL_PRIVACY + * #define CY_BLE_CONFIG_ENABLE_LL_PRIVACY (1u) + * + */ + + +#endif /* !defined(CY_BLE_CONF_H)*/ + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/cy_si_config.h b/2020TPCApp1.cydsn/cy_si_config.h new file mode 100644 index 0000000..47c088d --- /dev/null +++ b/2020TPCApp1.cydsn/cy_si_config.h @@ -0,0 +1,129 @@ +/***************************************************************************//** +* \file cy_si_config.h +* \version 1.0.1 +* +* \brief +* Definitions and function prototypes for Secure Image. +* +******************************************************************************** +* \copyright +* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef _CY_SI_CONFIG_H_ +#define _CY_SI_CONFIG_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*************************************** +* Macros +***************************************/ +/* +* Macros to define the secure image version and ID. +*/ +#define CY_SI_VERSION_MAJOR 1UL /**< Major version */ +#define CY_SI_VERSION_MINOR 0UL /**< Minor version */ +#define CY_SI_APP_VERSION ((CY_SI_VERSION_MAJOR << 24u) | (CY_SI_VERSION_MINOR << 16u)) /**< App Version */ +#define CY_SI_ID CY_PDL_DRV_ID(0x38u) /**< Secure Image ID */ +#define CY_SI_ID_INFO (uint32_t)( CY_SI_ID | CY_PDL_STATUS_INFO ) /**< Secure Image INFO ID */ +#define CY_SI_ID_WARNING (uint32_t)( CY_SI_ID | CY_PDL_STATUS_WARNING) /**< Secure Image WARNING ID */ +#define CY_SI_ID_ERROR (uint32_t)( CY_SI_ID | CY_PDL_STATUS_ERROR) /**< Secure Image ERROR ID */ +#define CY_SI_CHECKID(val) ((uint32_t)(val) & (CY_PDL_MODULE_ID_Msk << CY_PDL_MODULE_ID_Pos)) /**< Check ID macro */ + +/* +* Clock selection for Flash boot execution. +*/ +#define CY_SI_FLASHBOOT_CLK_25MHZ (0x00UL) /**< 25MHz clock selection for Flashboot */ +#define CY_SI_FLASHBOOT_CLK_8MHZ (0x01UL) /**< 8MHz clock selection for Flashboot */ +#define CY_SI_FLASHBOOT_CLK_50MHZ (0x02UL) /**< 50MHz clock selection for Flashboot */ + +/* +* Debugger wait window selection for Flash boot execution. +*/ +#define CY_SI_FLASHBOOT_WAIT_20MS (0x00UL) /**< 20ms debugger wait window for Flashboot */ +#define CY_SI_FLASHBOOT_WAIT_10MS (0x01UL) /**< 10ms debugger wait window for Flashboot */ +#define CY_SI_FLASHBOOT_WAIT_1MS (0x02UL) /**< 1ms debugger wait window for Flashboot */ +#define CY_SI_FLASHBOOT_WAIT_0MS (0x03UL) /**< 0ms debugger wait window for Flashboot */ +#define CY_SI_FLASHBOOT_WAIT_100MS (0x04UL) /**< 100ms debugger wait window for Flashboot */ + +/* +* Flash boot validation selection in chip NORMAL mode. +*/ +#define CY_SI_FLASHBOOT_VALIDATE_NO (0x00UL) /**< Do not validate app1 in NORMAL mode */ +#define CY_SI_FLASHBOOT_VALIDATE_YES (0x01UL) /**< Validate app1 in NORMAL mode */ + +/* +* Application format selection for secure boot. +*/ +#define CY_SI_APP_FORMAT_BASIC (0UL) /**< Basic application format (no header) */ +#define CY_SI_APP_FORMAT_CYPRESS (1UL) /**< Cypress application format (Cypress header) */ + + +/* +* Application type selection for secure boot. +*/ +#define CY_SI_APP_ID_FLASHBOOT (0x8001UL) /**< Flash boot ID Type */ +#define CY_SI_APP_ID_SECUREIMG (0x8002UL) /**< Secure image ID Type */ +#define CY_SI_APP_ID_BOOTLOADER (0x8003UL) /**< Bootloader ID Type */ + + +/*************************************** +* Constants +***************************************/ +#define CY_ARM_CM0P_CPUID (0xC6000000u) /** CM0+ partNo value from ARM CPUID[15:4] register shifted to [31:20] bits */ +#define CY_ARM_CM4_CPUID (0xC2400000u) /** CM4 partNo value from ARM CPUID[15:4] register shifted to [31:20] bits */ + +#define CY_SI_TOC_FLAGS_CLOCKS_MASK (0x00000003UL) /**< Mask for Flashboot clock selection */ +#define CY_SI_TOC_FLAGS_CLOCKS_POS (0UL) /**< Bit position of Flashboot clock selection */ +#define CY_SI_TOC_FLAGS_DELAY_MASK (0x0000001CUL) /**< Mask for Flashboot wait window selection */ +#define CY_SI_TOC_FLAGS_DELAY_POS (2UL) /**< Bit position of Flashboot wait window selection */ +#define CY_SI_TOC_FLAGS_APP_VERIFY_MASK (0x80000000UL) /**< Mask for Flashboot NORMAL mode app1 validation */ +#define CY_SI_TOC_FLAGS_APP_VERIFY_POS (31UL) /**< Bit position of Flashboot NORMAL mode app1 validation */ + +#define CY_SI_TOC2_MAGICNUMBER (0x01211220UL) /**< TOC2 identifier */ + +/*************************************** +* Structs +***************************************/ +/** Table of Content structure */ +typedef struct{ + volatile uint32_t objSize; /**< Object size (Bytes) */ + volatile uint32_t magicNum; /**< TOC ID (magic number) */ + volatile uint32_t userKeyAddr; /**< Secure key address in user Flash */ + volatile uint32_t smifCfgAddr; /**< SMIF configuration structure */ + volatile uint32_t appAddr1; /**< First user application object address */ + volatile uint32_t appFormat1; /**< First user application format */ + volatile uint32_t appAddr2; /**< Second user application object address */ + volatile uint32_t appFormat2; /**< Second user application format */ + volatile uint32_t shashObj; /**< Number of additional objects to be verified (S-HASH) */ + volatile uint32_t sigKeyAddr; /**< Signature verification key address */ + volatile uint32_t addObj[116]; /**< Additional objects to include in S-HASH */ + volatile uint32_t tocFlags; /**< Flags in TOC to control Flash boot options */ + volatile uint32_t crc; /**< CRC16-CCITT */ +}cy_stc_si_toc_t; + +/** User application header in Cypress format */ +typedef struct{ + volatile uint32_t objSize; /**< Object size (Bytes) */ + volatile uint32_t appId; /**< Application ID/version */ + volatile uint32_t appAttributes; /**< Attributes (reserved for future use) */ + volatile uint32_t numCores; /**< Number of cores */ + volatile uint32_t core0Vt; /**< (CM0+)VT offset - offset to the vector table from that entry */ + volatile uint32_t core1Vt; /**< (CM4)VT offset - offset to the vector table from that entry */ + volatile uint32_t core0Id; /**< CM0+ core ID */ + volatile uint32_t core1Id; /**< CM4 core ID */ +}cy_stc_user_appheader_t; + + +#if defined(__cplusplus) +} +#endif + +#endif /* _CY_SI_CONFIG_H_ */ + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/debug.c b/2020TPCApp1.cydsn/debug.c new file mode 100644 index 0000000..0652b22 --- /dev/null +++ b/2020TPCApp1.cydsn/debug.c @@ -0,0 +1,297 @@ +/******************************************************************************* +* File Name: debug.c +* +* Version: 1.0 +* +* Description: +* This file contains functions for printf functionality. +* +* Hardware Dependency: +* CY8CKIT-062 PSoC6 BLE Pioneer Kit +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "common.h" +#include "user_interface.h" + +#if (DEBUG_UART_ENABLED == ENABLED) + +#if defined(__ARMCC_VERSION) + +/* For MDK/RVDS compiler revise fputc function for printf functionality */ +struct __FILE +{ + int handle; +}; + +enum +{ + STDIN_HANDLE, + STDOUT_HANDLE, + STDERR_HANDLE +}; + +FILE __stdin = {STDIN_HANDLE}; +FILE __stdout = {STDOUT_HANDLE}; +FILE __stderr = {STDERR_HANDLE}; + +int fputc(int ch, FILE *file) +{ + int ret = EOF; + + switch( file->handle ) + { + case STDOUT_HANDLE: + UART_DEB_PUT_CHAR(ch); + ret = ch ; + break ; + + case STDERR_HANDLE: + ret = ch ; + break ; + + default: + file = file; + break ; + } + return ret ; +} + +#elif defined (__ICCARM__) /* IAR */ + +/* For IAR compiler revise __write() function for printf functionality */ +size_t __write(int handle, const unsigned char * buffer, size_t size) +{ + size_t nChars = 0; + + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we + * don't we just return. (Remember, "handle" == -1 means that all + * handles should be flushed.) + */ + return (0); + } + + for (/* Empty */; size != 0; --size) + { + UART_DEB_PUT_CHAR(*buffer); + ++buffer; + ++nChars; + } + + return (nChars); +} + +#else /* (__GNUC__) GCC */ + +/* For GCC compiler revise _write() function for printf functionality */ +int _write(int file, char *ptr, int len) +{ + int i; + file = file; + for (i = 0; i < len; i++) + { + UART_DEB_PUT_CHAR(*ptr); + ++ptr; + } + return len; +} + + +#endif /* (__ARMCC_VERSION) */ + +#endif /* DEBUG_UART_ENABLED == ENABLED */ + +void ShowValue(cy_stc_ble_gatt_value_t *value) +{ + int16_t i; + + for(i = 0; i < value->len; i++) + { + DBG_PRINTF("%2.2x ", value->val[i]); + } + DBG_PRINTF("\r\n"); +} + + +void Set32ByPtr(uint8_t ptr[], uint32_t value) +{ + ptr[0u] = (uint8_t) value; + ptr[1u] = (uint8_t) (value >> 8u); + ptr[2u] = (uint8_t) (value >> 16u); + ptr[3u] = (uint8_t) (value >> 24u); +} + + +/******************************************************************************* +* Function Name: ShowError +******************************************************************************** +* +* Summary: +* Shows error condition: Turn On all LEDs - white color will indicate error. +* +*******************************************************************************/ +void ShowError(void) +{ + EnableAllLeds(); + + /* Halt CPU in Debug mode */ + CY_ASSERT(0u != 0u); +} + + +/******************************************************************************* +* Function Name: HexToAscii +******************************************************************************** +* +* Summary: +* Hexadecimal to ASCII converter +* +* Parameters: +* value: Hexadecimal value +* digit: Which nibble to be obtained +* +* Return: +* char: the ASCII equivalent of that nibble +* +* Theory: +* Converts hexadecimal to ASCII +* +*******************************************************************************/ +char HexToAscii(uint8_t value, uint8_t nibble) +{ + if(nibble == 1) + { + value = value & 0xf0; + value = value >> 4; + + /* bit-shift the result to the right by four bits (i.e. quickly divides by 16) */ + if (value > 9) + { + value = value - 10 + 'A'; + } + else + { + value = value + '0'; + } + } + else if (nibble == 0) + { + /* means use a bitwise AND to take the bottom four bits from the byte, + 0x0F is 00001111 in binary */ + value = value & 0x0F; + if (value > 9) + { + value = value - 10 + 'A'; + } + else + { + value = value + '0'; + } + } + else + { + value = ' '; + } + + return value; +} + +/******************************************************************************* +* Function Name: PrintStackVersion +******************************************************************************** +* +* Summary: +* Prints the BLE Stack version if the PRINT_STACK_VERSION is defined. +* +*******************************************************************************/ +void PrintStackVersion(void) +{ + cy_stc_ble_stack_lib_version_t stackVersion; + cy_en_ble_api_result_t apiResult; + + apiResult = Cy_BLE_GetStackLibraryVersion(&stackVersion); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("Cy_BLE_GetStackLibraryVersion API Error: "); + PrintApiResult(apiResult); + } + else + { + DBG_PRINTF("BLE Stack Version: %d.%d.%d.%d\r\n", stackVersion.majorVersion, + stackVersion.minorVersion, + stackVersion.patch, + stackVersion.buildNumber); + } +} + +/******************************************************************************* +* Function Name: PrintApiResult +******************************************************************************** +* +* Summary: +* Decodes and prints the apiResult global variable value. +* +*******************************************************************************/ +void PrintApiResult(cy_en_ble_api_result_t apiResult) +{ + DBG_PRINTF("0x%2.2x ", apiResult); + + switch(apiResult) + { + case CY_BLE_SUCCESS: + DBG_PRINTF("ok\r\n"); + break; + + case CY_BLE_ERROR_INVALID_PARAMETER: + DBG_PRINTF("invalid parameter\r\n"); + break; + + case CY_BLE_ERROR_INVALID_OPERATION: + DBG_PRINTF("invalid operation\r\n"); + break; + + case CY_BLE_ERROR_NO_DEVICE_ENTITY: + DBG_PRINTF("no device entity\r\n"); + break; + + case CY_BLE_ERROR_NTF_DISABLED: + DBG_PRINTF("notification is disabled\r\n"); + break; + + case CY_BLE_ERROR_IND_DISABLED: + DBG_PRINTF("indication is disabled\r\n"); + break; + + case CY_BLE_ERROR_CHAR_IS_NOT_DISCOVERED: + DBG_PRINTF("characteristic is not discovered\r\n"); + break; + + case CY_BLE_ERROR_INVALID_STATE: + DBG_PRINTF("invalid state"); + break; + + case CY_BLE_ERROR_GATT_DB_INVALID_ATTR_HANDLE: + DBG_PRINTF("invalid attribute handle\r\n"); + break; + + case CY_BLE_ERROR_FLASH_WRITE_NOT_PERMITED: + DBG_PRINTF("flash write not permitted\r\n"); + break; + + default: + DBG_PRINTF("other api result\r\n"); + break; + } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/dfu_cm0p.icf b/2020TPCApp1.cydsn/dfu_cm0p.icf new file mode 100644 index 0000000..2495c11 --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_cm0p.icf @@ -0,0 +1,251 @@ +/***************************************************************************//** +* \file dfu_cm0p.icf +* \version 3.0 +* +* The linker file for the the IAR compiler. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case, you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ + + +/******************************************************************************* +* Start of CM4 and CM0+ linker script common region +*******************************************************************************/ + +/*-Memory Regions-*/ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + + +define memory mem with size = 4G; + +/* Memory regions for all applications are defined here */ +define region FLASH_app0_core0 = mem:[from 0x10000000 size 0x10000]; +define region FLASH_app0_core1 = mem:[from 0x10010000 size 0x10000]; +define region FLASH_app1_core0 = mem:[from 0x10040000 size 0x10000]; +define region FLASH_app1_core1 = mem:[from 0x10050000 size 0x10000]; + +/* +* The region for DFU SDK metadata +* when it is outside of any application +*/ +define region FLASH_boot_meta = mem:[from 0x100FFA00 size 0x200]; + + +/* eFuse */ +define region ROM_EFUSE = mem:[from 0x90700000 size 0x100000]; + +/* SFlash NAR */ +define region SFLASH_NAR = mem:[from 0x16001A00 size 0x200]; + +/* SFlash User Data */ +define region SFLASH_USER_DATA = mem:[from 0x16000800 size 0x800]; + +/* SFlash Public Key, 6 SFlash rows */ +define region SFLASH_PUBLIC_KEY = mem:[from 0x16005A00 size 0xC00]; + +/* Table of Content part 2, two SFlash rows */ +define region SFLASH_TOC = mem:[from 0x16007C00 size 0x400]; + + +/* Emulated EEPROM app regions */ +define region EM_EEPROM_app0_core0 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app0_core1 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app1_core0 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app1_core1 = mem:[from 0x14000000 size 0x8000]; + +/* XIP/SMIF app regions */ +define region EROM_app0_core0 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app0_core1 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app1_core0 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app1_core1 = mem:[from 0x18000000 size 0x1000]; + +/* used for RAM sharing across applications */ +define region IRAM_common = mem:[from 0x08000000 size 0x0100]; + +/* note: all the IRAM_appX_core0 regions has to be 0x100 aligned */ +/* and the IRAM_appX_core1 regions has to be 0x400 aligned */ +/* as they contain Interrupt Vector Table Remapped at the start */ +define region IRAM_app0_core0 = mem:[from 0x08000100 size 0x1F00]; +define region IRAM_app0_core1 = mem:[from 0x08002000 size 0x8000]; +define region IRAM_app1_core0 = mem:[from 0x08000100 size 0x1F00]; +define region IRAM_app1_core1 = mem:[from 0x08002000 size 0x8000]; + + +/* Used by all DFU SDK and CyMCUElfTool */ +define exported symbol __cy_boot_metadata_addr = 0x100FFA00; +define exported symbol __cy_boot_metadata_length = __cy_memory_0_row_size; + +/* Used by CyMCUElfTool to generate ProductID for DFU SDK apps */ +define exported symbol __cy_product_id = 0x01020304; + +/* Used by CyMCUElfTool to generate ChecksumType for DFU SDK apps */ +define exported symbol __cy_checksum_type = 0; + +/* +* The size of the application signature. +* E.g. 4 for CRC-32, +* 32 for SHA256, +* 256 for RSA 2048. +*/ +define exported symbol __cy_boot_signature_size = 4; + +/* Used by DFU SDK projects, in dfu_user.c to fill in the metadata table */ +define exported symbol __cy_app0_verify_start = start(FLASH_app0_core0); +define exported symbol __cy_app0_verify_length = size (FLASH_app0_core0) + size (FLASH_app0_core1) + - __cy_boot_signature_size; + +define exported symbol __cy_app1_verify_start = start(FLASH_app1_core0); +define exported symbol __cy_app1_verify_length = size (FLASH_app1_core0) + size (FLASH_app1_core1) + - __cy_boot_signature_size; + +/******************************************************************************* +* End of CM4 and CM0+ linker script common region +*******************************************************************************/ + + +/* +* Used by CM0+ to start the CM4 core in DFU SDK applications. +* Make sure the correct app no. is entered here. +*/ +define exported symbol __cy_app_core1_start_addr = start(FLASH_app0_core1); + +/* CyMCUElfTool uses this symbol to set a proper app number */ +define exported symbol __cy_app_id = 0; + +/* CyMCUElfTool uses these to generate an application signature */ +/* The size of the default signature (CRC-32C) is 4 bytes */ +define exported symbol __cy_app_verify_start = start(FLASH_app0_core0); +define exported symbol __cy_app_verify_length = size(FLASH_app0_core0) + size(FLASH_app0_core1) + - __cy_boot_signature_size; + + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + + +define region IROM1_region = FLASH_app0_core0; /* Flash, user app */ +define region IROM2_region = EM_EEPROM_app0_core0; /* Emulated EEPROM */ +define region IROM3_region = SFLASH_USER_DATA; /* SFlash User Data */ +define region IROM4_region = SFLASH_NAR; /* SFlash NAR */ +define region IROM5_region = SFLASH_PUBLIC_KEY; /* SFlash Public Key */ +define region IROM6_region = SFLASH_TOC; /* SFlash TOC part 2 */ +define region IROM7_region = ROM_EFUSE; /* eFuse */ +define region EROM1_region = EROM_app0_core0; /* XIP / SMIF */ +define region IRAM1_region = IRAM_app0_core0; /* RAM */ + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram, + section .cy_boot_noinit.appId, section .cy_boot_noinit }; + + +/*-Placement-*/ + +/* Flash */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM7_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM_common { readwrite section .cy_boot_noinit.appId }; +place in IRAM_common { readwrite section .cy_boot_noinit }; +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_sflash_toc_2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + section .cy_boot_noinit, + section .cy_boot_noinit.appId, + }; + + + +/* EOF */ diff --git a/2020TPCApp1.cydsn/dfu_cm0p.ld b/2020TPCApp1.cydsn/dfu_cm0p.ld new file mode 100644 index 0000000..a081163 --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_cm0p.ld @@ -0,0 +1,485 @@ +/***************************************************************************//** +* \file dfu_cm0p.ld +* \version 3.0 +* +* The linker file for the GNU C compiler. +* Used for DFU SDK core0 firmware projects. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case, you may see warnings during the +* build process. In your project, simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* +* Forces symbol to be added to the output file. +* Otherwise linker may remove it if founds that it is not used in the project. +* This command has the same effect as the -u command-line option. +*/ +EXTERN(Reset_Handler) + + +/******************************************************************************* +* Start of CM4 and CM0+ linker script common region +*******************************************************************************/ + +/* +* Memory regions, for each application and MCU core. +*/ +MEMORY +{ + flash_app0_core0 (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + flash_app0_core1 (rx) : ORIGIN = 0x10010000, LENGTH = 0x30000 + flash_app1_core0 (rx) : ORIGIN = 0x10040000, LENGTH = 0x30000 + flash_app1_core1 (rx) : ORIGIN = 0x10070000, LENGTH = 0x50000 + + flash_storage (rw) : ORIGIN = 0x100D0000, LENGTH = 0x1000 + flash_boot_meta (rw) : ORIGIN = 0x100FFA00, LENGTH = 0x400 + + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400 + + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 + + ram_common (rwx) : ORIGIN = 0x08000000, LENGTH = 0x0100 + + /* note: all the ram_appX_core0 regions has to be 0x100 aligned */ + /* and the ram_appX_core1 regions has to be 0x400 aligned */ + /* as they contain Interrupt Vector Table Remapped at the start */ + ram_app0_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00 + ram_app0_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x8000 + + ram_app1_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00 + ram_app1_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x30000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x4000 /* 16 KB */ + + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x08000000 +} + +/* Regions parameters */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* The DFU SDK metadata limits */ +__cy_boot_metadata_addr = ORIGIN(flash_boot_meta); +__cy_boot_metadata_length = __cy_memory_0_row_size; + +/* The Product ID, used by CyMCUElfTool to generate a updating file */ +__cy_product_id = 0x01020304; + +/* The checksum type used by CyMCUElfTool to generate a updating file */ +__cy_checksum_type = 0x00; + +/* Used by the DFU SDK application to set the metadata */ +__cy_app0_verify_start = ORIGIN(flash_app0_core0); +__cy_app0_verify_length = LENGTH(flash_app0_core0) + LENGTH(flash_app0_core1) - __cy_boot_signature_size; +__cy_app1_verify_start = ORIGIN(flash_app1_core0); +__cy_app1_verify_length = LENGTH(flash_app1_core0) + LENGTH(flash_app1_core1) - __cy_boot_signature_size; + +/* +* The size of the application signature. +* E.g. 4 for CRC-32, +* 32 for SHA256, +* 256 for RSA 2048. +*/ +__cy_boot_signature_size = 256; + +/******************************************************************************* +* End of CM4 and CM0+ linker script common region +*******************************************************************************/ + + +/* +* DFU SDK specific: aliases regions, so the rest of code does not use +* application specific memory region names +*/ +REGION_ALIAS("flash", flash_app1_core0); +REGION_ALIAS("flash_core1", flash_app1_core1); +REGION_ALIAS("ram", ram_app1_core0); + +/* DFU SDK specific: sets an app Id */ +__cy_app_id = 1; + +/* +* DFU SDK specific: sets a start address of the Core1 application image, +* more specifically an address of the Core1 interrupt vector table. +* CM0+ uses this information to launch Core1. +*/ +__cy_app_core1_start_addr = ORIGIN(flash_core1); /* used to start Core1 from Core0 */ + +/* DFU SDK specific */ +/* CyMCUElfTool uses these ELF symbols to generate an application signature */ +__cy_app_verify_start = ORIGIN(flash); +__cy_app_verify_length = LENGTH(flash) + LENGTH(flash_core1) - __cy_boot_signature_size; + + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* The linker script defines how to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * This linker script defines the symbols, which can be used by code without a definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * + * For the DFU SDK, these additional symbols are defined: + * __cy_app_id + * __cy_product_id + * __cy_checksum_type + * __cy_app_core1_start_addr + * __cy_boot_metadata_addr + * __cy_boot_metadata_length + */ + + +SECTIONS +{ + /* DFU SDK specific */ + /* The noinit section, used across all the applications */ + .cy_boot_noinit (NOLOAD) : + { + KEEP(*(.cy_boot_noinit)); + } > ram_common + + /* The last byte of the section is used for AppId to be shared between all the applications */ + .cy_boot_noinit.appId ORIGIN(ram_common) + LENGTH(ram_common) - 1 (NOLOAD) : + { + KEEP(*(.cy_boot_noinit.appId)); + } > ram_common + + /* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */ + .cy_boot_metadata : + { + KEEP(*(.cy_boot_metadata)) + } > flash_boot_meta + + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to the RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_{device}_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from Flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_{device}_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells the linker that the .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes the linker: A) not allocate the section in memory; + * B) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get the PROGBITS type. + * This makes the linker: A) allocate the zeroed section in memory; B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* The .stack_dummy section doesn't contain any symbols. It is only + * used for the linker to calculate the size of the stack sections, and assign + * values to the stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set the stack top to the end of RAM, and the stack limit move down by + * the size of the stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Places the code in the Execute in the Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* EOF */ diff --git a/2020TPCApp1.cydsn/dfu_cm0p.scat b/2020TPCApp1.cydsn/dfu_cm0p.scat new file mode 100644 index 0000000..a774dc4 --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_cm0p.scat @@ -0,0 +1,189 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file dfu_cm0p.scat +;* \version 3.0 +;* +;* The linker file for the ARMCC. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case, you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +;* DFU SDK specific: includes defines common across all the applications +#include "dfu_mdk_common.h" + +;* DFU SDK specific: defines the memory regions +;* Make sure the correct app no. is entered here. + +; Flash +#define FLASH_START CY_APP0_CORE0_FLASH_ADDR +#define FLASH_SIZE CY_APP0_CORE0_FLASH_LENGTH + +; Emulated EEPROM Flash area +#define EM_EEPROM_START CY_APP0_CORE0_EM_EEPROM_ADDR +#define EM_EEPROM_SIZE CY_APP0_CORE0_EM_EEPROM_LENGTH + +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000400 + +; External memory +#define XIP_START CY_APP0_CORE0_SMIF_ADDR +#define XIP_SIZE CY_APP0_CORE0_SMIF_LENGTH + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; RAM +#define RAM_START CY_APP0_CORE0_RAM_ADDR +#define RAM_SIZE CY_APP0_CORE0_RAM_LENGTH + + +LR_FLASH FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_COMMON CY_APP_RAM_COMMON_ADDR UNINIT + { + * (.cy_boot_noinit.appId) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Places the code in the Execute in the Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/dfu_cm4.icf b/2020TPCApp1.cydsn/dfu_cm4.icf new file mode 100644 index 0000000..ca971bc --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_cm4.icf @@ -0,0 +1,248 @@ +/***************************************************************************//** +* \file dfu_cm4.icf +* \version 3.0 +* +* The linker file for the the IAR compiler. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case, you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ + + +/******************************************************************************* +* Start of CM4 and CM0+ linker script common region +*******************************************************************************/ + +/*-Memory Regions-*/ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + + +define memory mem with size = 4G; + +/* Memory regions for all applications are defined here */ +define region FLASH_app0_core0 = mem:[from 0x10000000 size 0x10000]; +define region FLASH_app0_core1 = mem:[from 0x10010000 size 0x10000]; +define region FLASH_app1_core0 = mem:[from 0x10040000 size 0x10000]; +define region FLASH_app1_core1 = mem:[from 0x10050000 size 0x10000]; + +/* +* The region for DFU SDK metadata +* when it is outside of any application +*/ +define region FLASH_boot_meta = mem:[from 0x100FFA00 size 0x200]; + + +/* eFuse */ +define region ROM_EFUSE = mem:[from 0x90700000 size 0x100000]; + +/* SFlash NAR */ +define region SFLASH_NAR = mem:[from 0x16001A00 size 0x200]; + +/* SFlash User Data */ +define region SFLASH_USER_DATA = mem:[from 0x16000800 size 0x800]; + +/* SFlash Public Key, 6 SFlash rows */ +define region SFLASH_PUBLIC_KEY = mem:[from 0x16005A00 size 0xC00]; + +/* Table of Content part 2, two SFlash rows */ +define region SFLASH_TOC = mem:[from 0x16007C00 size 0x400]; + + +/* Emulated EEPROM app regions */ +define region EM_EEPROM_app0_core0 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app0_core1 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app1_core0 = mem:[from 0x14000000 size 0x8000]; +define region EM_EEPROM_app1_core1 = mem:[from 0x14000000 size 0x8000]; + +/* XIP/SMIF app regions */ +define region EROM_app0_core0 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app0_core1 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app1_core0 = mem:[from 0x18000000 size 0x1000]; +define region EROM_app1_core1 = mem:[from 0x18000000 size 0x1000]; + +/* used for RAM sharing across applications */ +define region IRAM_common = mem:[from 0x08000000 size 0x0100]; + +/* note: all the IRAM_appX_core0 regions has to be 0x100 aligned */ +/* and the IRAM_appX_core1 regions has to be 0x400 aligned */ +/* as they contain Interrupt Vector Table Remapped at the start */ +define region IRAM_app0_core0 = mem:[from 0x08000100 size 0x1F00]; +define region IRAM_app0_core1 = mem:[from 0x08002000 size 0x8000]; +define region IRAM_app1_core0 = mem:[from 0x08000100 size 0x1F00]; +define region IRAM_app1_core1 = mem:[from 0x08002000 size 0x8000]; + + +/* Used by all DFU SDK and CyMCUElfTool */ +define exported symbol __cy_boot_metadata_addr = 0x100FFA00; +define exported symbol __cy_boot_metadata_length = __cy_memory_0_row_size; + +/* Used by CyMCUElfTool to generate ProductID for DFU SDK apps */ +define exported symbol __cy_product_id = 0x01020304; + +/* Used by CyMCUElfTool to generate ChecksumType for DFU SDK apps */ +define exported symbol __cy_checksum_type = 0; + +/* +* The size of the application signature. +* E.g. 4 for CRC-32, +* 32 for SHA256, +* 256 for RSA 2048. +*/ +define exported symbol __cy_boot_signature_size = 4; + +/* Used by DFU SDK projects, in dfu_user.c to fill in the metadata table */ +define exported symbol __cy_app0_verify_start = start(FLASH_app0_core0); +define exported symbol __cy_app0_verify_length = size (FLASH_app0_core0) + size (FLASH_app0_core1) + - __cy_boot_signature_size; + +define exported symbol __cy_app1_verify_start = start(FLASH_app1_core0); +define exported symbol __cy_app1_verify_length = size (FLASH_app1_core0) + size (FLASH_app1_core1) + - __cy_boot_signature_size; + +/******************************************************************************* +* End of CM4 and CM0+ linker script common region +*******************************************************************************/ + + +/* CyMCUElfTool uses this symbol to set a proper app number */ +define exported symbol __cy_app_id = 0; + +/* CyMCUElfTool uses these to generate an application signature */ +/* The size of the default signature (CRC-32C) is 4 bytes */ +define exported symbol __cy_app_verify_start = start(FLASH_app0_core0); +define exported symbol __cy_app_verify_length = size(FLASH_app0_core0) + size(FLASH_app0_core1) + - __cy_boot_signature_size; + + +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} + + +define region IROM1_region = FLASH_app0_core1; /* Flash, user app */ +define region IROM2_region = EM_EEPROM_app0_core1; /* Emulated EEPROM */ +define region IROM3_region = SFLASH_USER_DATA; /* SFlash User Data */ +define region IROM4_region = SFLASH_NAR; /* SFlash NAR */ +define region IROM5_region = SFLASH_PUBLIC_KEY; /* SFlash Public Key */ +define region IROM6_region = SFLASH_TOC; /* SFlash TOC part 2 */ +define region IROM7_region = ROM_EFUSE; /* eFuse */ +define region EROM1_region = EROM_app0_core1; /* XIP / SMIF */ +define region IRAM1_region = IRAM_app0_core1; /* RAM */ + + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram, + section .cy_boot_noinit.appId, section .cy_boot_noinit }; + + +/*-Placement-*/ + +/* Flash */ +place at start of IROM1_region { block RO }; +".cy_app_signature": place at end of IROM1_region { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM7_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM_common { readwrite section .cy_boot_noinit.appId }; +place in IRAM_common { readwrite section .cy_boot_noinit }; +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + +/* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */ +".cy_boot_metadata" : place at start of FLASH_boot_meta { section .cy_boot_metadata }; + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_sflash_toc_2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + section .cy_boot_metadata, + section .cy_boot_noinit, + section .cy_boot_noinit.appId, + }; + + +/* EOF */ diff --git a/2020TPCApp1.cydsn/dfu_cm4.ld b/2020TPCApp1.cydsn/dfu_cm4.ld new file mode 100644 index 0000000..37ac117 --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_cm4.ld @@ -0,0 +1,484 @@ +/***************************************************************************//** +* \file dfu_cm4.ld +* \version 3.0 +* +* The linker file for the GNU C compiler. +* Used for DFU SDK core1 firmware projects. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case, you may see warnings during the +* build process. In your project, simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* +* Forces symbol to be added to the output file. +* Otherwise linker may remove it if founds that it is not used in the project. +* This command has the same effect as the -u command-line option. +*/ +EXTERN(Reset_Handler) + + +/******************************************************************************* +* Start of CM4 and CM0+ linker script common region +*******************************************************************************/ + +/* +* Memory regions, for each application and MCU core. +*/ +MEMORY +{ + flash_app0_core0 (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + flash_app0_core1 (rx) : ORIGIN = 0x10010000, LENGTH = 0x30000 + flash_app1_core0 (rx) : ORIGIN = 0x10040000, LENGTH = 0x30000 + flash_app1_core1 (rx) : ORIGIN = 0x10070000, LENGTH = 0x50000 + + flash_storage (rw) : ORIGIN = 0x100D0000, LENGTH = 0x1000 + flash_boot_meta (rw) : ORIGIN = 0x100FFA00, LENGTH = 0x400 + + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400 + + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 + + ram_common (rwx) : ORIGIN = 0x08000000, LENGTH = 0x0100 + + /* note: all the ram_appX_core0 regions has to be 0x100 aligned */ + /* and the ram_appX_core1 regions has to be 0x400 aligned */ + /* as they contain Interrupt Vector Table Remapped at the start */ + ram_app0_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00 + ram_app0_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x8000 + + ram_app1_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00 + ram_app1_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x30000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14004000, LENGTH = 0x4000 /* 16 KB */ + + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x08000000 +} + +/* Regions parameters */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* The DFU SDK metadata limits */ +__cy_boot_metadata_addr = ORIGIN(flash_boot_meta); +__cy_boot_metadata_length = __cy_memory_0_row_size; + +/* The Product ID, used by CyMCUElfTool to generate a updating file */ +__cy_product_id = 0x01020304; + +/* The checksum type used by CyMCUElfTool to generate a updating file */ +__cy_checksum_type = 0x00; + +/* Used by the DFU SDK application to set the metadata */ +__cy_app0_verify_start = ORIGIN(flash_app0_core0); +__cy_app0_verify_length = LENGTH(flash_app0_core0) + LENGTH(flash_app0_core1) - __cy_boot_signature_size; +__cy_app1_verify_start = ORIGIN(flash_app1_core0); +__cy_app1_verify_length = LENGTH(flash_app1_core0) + LENGTH(flash_app1_core1) - __cy_boot_signature_size; + +/* +* The size of the application signature. +* E.g. 4 for CRC-32, +* 32 for SHA256, +* 256 for RSA 2048. +*/ +__cy_boot_signature_size = 256; + +/******************************************************************************* +* End of CM4 and CM0+ linker script common region +*******************************************************************************/ + + +/* +* DFU SDK specific: aliases regions, so the rest of code does not use +* application specific memory region names +*/ +REGION_ALIAS("flash_core0", flash_app1_core0); +REGION_ALIAS("flash", flash_app1_core1); +REGION_ALIAS("ram", ram_app1_core1); + +/* DFU SDK specific: sets an app Id */ +__cy_app_id = 1; + + +/* DFU SDK specific */ +/* CyMCUElfTool uses these ELF symbols to generate an application signature */ +__cy_app_verify_start = ORIGIN(flash_core0); +__cy_app_verify_length = LENGTH(flash_core0) + LENGTH(flash) - __cy_boot_signature_size; + + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* The linker script defines how to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * This linker script defines the symbols, which can be used by code without a definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * + * For the DFU SDK, these additional symbols are defined: + * __cy_app_id + * __cy_product_id + * __cy_checksum_type + * __cy_app_core1_start_addr + * __cy_boot_metadata_addr + * __cy_boot_metadata_length + */ + + +SECTIONS +{ + /* DFU SDK specific */ + /* The noinit section, used across all the applications */ + .cy_boot_noinit (NOLOAD) : + { + KEEP(*(.cy_boot_noinit)); + } > ram_common + + /* The last byte of the section is used for AppId to be shared between all the applications */ + .cy_boot_noinit.appId ORIGIN(ram_common) + LENGTH(ram_common) - 1 (NOLOAD) : + { + KEEP(*(.cy_boot_noinit.appId)); + } > ram_common + + /* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */ + .cy_boot_metadata : + { + KEEP(*(.cy_boot_metadata)) + } > flash_boot_meta + + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to the RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_{device}_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_{device}_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + /* + * The DFU SDK section for an app verification signature. + * Must be placed at the end of the application. + * In this case, last N bytes of the last Flash row inside the application. + */ + .cy_app_signature ABSOLUTE(ORIGIN(flash) + LENGTH(flash) - __cy_boot_signature_size) : + { + KEEP(*(.cy_app_signature)) + } > flash = 0 + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells the linker that the .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes the linker: A) not allocate the section in memory; + * B) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get the PROGBITS type. + * This makes the linker: A) allocate the zeroed section in memory; B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* The .stack_dummy section doesn't contain any symbols. It is only + * used for the linker to calculate the size of the stack sections, and assign + * values to the stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set the stack top to the end of RAM, and the stack limit move down by + * the size of the stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Places the code in the Execute in the Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* EOF */ diff --git a/2020TPCApp1.cydsn/dfu_cm4.scat b/2020TPCApp1.cydsn/dfu_cm4.scat new file mode 100644 index 0000000..8aab5d9 --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_cm4.scat @@ -0,0 +1,206 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file dfu_cm4.scat +;* \version 3.0 +;* +;* The linker file for the ARMCC. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case, you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +;* DFU SDK specific: includes defines common across all the applications +#include "dfu_mdk_common.h" + +;* DFU SDK specific: defines the memory regions +;* Make sure the correct app no. is entered here + +; Flash +#define FLASH_START CY_APP0_CORE1_FLASH_ADDR +#define FLASH_SIZE CY_APP0_CORE1_FLASH_LENGTH + +; Flash Toc +#define FLASH_TOC_START CY_TOC_START +#define FLASH_TOC_SIZE CY_TOC_SIZE + +; Emulated EEPROM Flash area +#define EM_EEPROM_START CY_APP0_CORE1_EM_EEPROM_ADDR +#define EM_EEPROM_SIZE CY_APP0_CORE1_EM_EEPROM_LENGTH + +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000400 + +; External memory +#define XIP_START CY_APP0_CORE1_SMIF_ADDR +#define XIP_SIZE CY_APP0_CORE1_SMIF_LENGTH + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; RAM +#define RAM_START CY_APP0_CORE1_RAM_ADDR +#define RAM_SIZE CY_APP0_CORE1_RAM_LENGTH + + +LR_FLASH FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_COMMON CY_APP_RAM_COMMON_ADDR UNINIT + { + * (.cy_boot_noinit.appId) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during + ; a device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + + ; Used for the digital signature of the secure application and the + ; DFU SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - CY_BOOT_SIGNATURE_SIZE) FIXED + { + * (.cy_app_signature) + } +} + +; App0 uses it to initialize DFU SDK metadata, in dfu_user.c file +LR_CY_BOOT_METADATA CY_BOOT_META_FLASH_ADDR CY_BOOT_META_FLASH_LENGTH +{ + .cy_boot_metadata + 0 + { + * (.cy_boot_metadata) + } +} + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory Flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory Flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory Flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory Flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/dfu_mdk_common.h b/2020TPCApp1.cydsn/dfu_mdk_common.h new file mode 100644 index 0000000..e50b562 --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_mdk_common.h @@ -0,0 +1,114 @@ +/******************************************************************************* +* \file dfu_mdk_common.h +* \version 3.0 +* +* This file provides only macro definitions to use for +* project configuration. +* They may be used in both scatter files and source code files. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef DFU_MDK_COMMON_H_ +#define DFU_MDK_COMMON_H_ + +/* DFU SDK parameters */ +/* The user application may either update them or leave the defaults if they fit */ +#define CY_BOOT_METADATA_ADDR 0x100FFA00 +#define CY_BOOT_METADATA_LENGTH 0x200 +#define CY_PRODUCT_ID 0x01020304 +#define CY_CHECKSUM_TYPE 0x00 + +/* +* The size of the section .cy_app_signature. +* 1,2, or 4 for a checksum +* 4 for CRC-32 +* 20 for SHA1 +* 32 for SHA256 +* 256 for RSASSA-PKCS1-v1.5 with the 2048 bit RSA key. +* +* SHA1 must be used. +*/ +#define CY_BOOT_SIGNATURE_SIZE 4 + +/* For the MDK linker script, defines TOC parameters */ +/* Update per device series to be in the last Flash row */ +#define CY_TOC_START 0x16007C00 +#define CY_TOC_SIZE 0x400 + + +/* Memory region ranges per core and app */ +#define CY_APP0_CORE0_FLASH_ADDR 0x10000000 +#define CY_APP0_CORE0_FLASH_LENGTH 0x10000 + +#define CY_APP0_CORE1_FLASH_ADDR 0x10010000 +#define CY_APP0_CORE1_FLASH_LENGTH 0x10000 + +#define CY_APP1_CORE0_FLASH_ADDR 0x10040000 +#define CY_APP1_CORE0_FLASH_LENGTH 0x10000 + +#define CY_APP1_CORE1_FLASH_ADDR 0x10050000 +#define CY_APP1_CORE1_FLASH_LENGTH 0x10000 + +/* DFU SDK metadata address range in Flash */ +#define CY_BOOT_META_FLASH_ADDR 0x100FFA00 +#define CY_BOOT_META_FLASH_LENGTH 0x200 + +/* Application ranges in emulated EEPROM */ +#define CY_APP0_CORE0_EM_EEPROM_ADDR 0x14000000 +#define CY_APP0_CORE0_EM_EEPROM_LENGTH 0x00000000 + +#define CY_APP0_CORE1_EM_EEPROM_ADDR (CY_APP0_CORE0_EM_EEPROM_ADDR + CY_APP0_CORE0_EM_EEPROM_LENGTH) +#define CY_APP0_CORE1_EM_EEPROM_LENGTH 0x0000 + +#define CY_APP1_CORE0_EM_EEPROM_ADDR 0x14000000 +#define CY_APP1_CORE0_EM_EEPROM_LENGTH 0x00000000 + +#define CY_APP1_CORE1_EM_EEPROM_ADDR (CY_APP1_CORE0_EM_EEPROM_ADDR + CY_APP1_CORE0_EM_EEPROM_LENGTH) +#define CY_APP1_CORE1_EM_EEPROM_LENGTH 0x00000000 + +/* Application ranges in SMIF XIP */ +#define CY_APP0_CORE0_SMIF_ADDR 0x18000000 +#define CY_APP0_CORE0_SMIF_LENGTH 0x00000000 + +#define CY_APP0_CORE1_SMIF_ADDR (CY_APP0_CORE0_SMIF_ADDR + CY_APP0_CORE0_SMIF_LENGTH) +#define CY_APP0_CORE1_SMIF_LENGTH 0x00000000 + +#define CY_APP1_CORE0_SMIF_ADDR 0x14000200 +#define CY_APP1_CORE0_SMIF_LENGTH 0x00000000 + +#define CY_APP1_CORE1_SMIF_ADDR (CY_APP1_CORE0_SMIF_ADDR + CY_APP1_CORE0_SMIF_LENGTH) +#define CY_APP1_CORE1_SMIF_LENGTH 0x00000000 + +/* Application ranges in RAM */ +#define CY_APP_RAM_COMMON_ADDR 0x08000000 +#define CY_APP_RAM_COMMON_LENGTH 0x00000100 + +/* note: all the CY_APPX_CORE0_RAM regions has to be 0x100 aligned */ +/* and the CY_APPX_CORE1_RAM regions has to be 0x400 aligned */ +/* as they contain Interrupt Vector Table Remapped at the start */ + +#define CY_APP0_CORE0_RAM_ADDR 0x08000100 +#define CY_APP0_CORE0_RAM_LENGTH 0x00001F00 + +#define CY_APP0_CORE1_RAM_ADDR (CY_APP0_CORE0_RAM_ADDR + CY_APP0_CORE0_RAM_LENGTH) +#define CY_APP0_CORE1_RAM_LENGTH 0x00008000 + +#define CY_APP1_CORE0_RAM_ADDR CY_APP0_CORE0_RAM_ADDR +#define CY_APP1_CORE0_RAM_LENGTH 0x00001F00 + +#define CY_APP1_CORE1_RAM_ADDR (CY_APP1_CORE0_RAM_ADDR + CY_APP1_CORE0_RAM_LENGTH) +#define CY_APP1_CORE1_RAM_LENGTH 0x00008000 + + +__asm void cy_DFU_mdkAsmDummy(void); + +#endif /* DFU_MDK_COMMON_H_ */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/dfu_mdk_symbols.c b/2020TPCApp1.cydsn/dfu_mdk_symbols.c new file mode 100644 index 0000000..fd3a950 --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_mdk_symbols.c @@ -0,0 +1,66 @@ +/******************************************************************************* +* \file dfu_mdk_symbols.c +* \version 3.0 +* +* This file provides symbols to add to an ELF file required by +* CyMCUElfTool to generate correct HEX and CYACD2 files. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "dfu_mdk_common.h" + +/******************************************************************************* +* Function Name: cy_DFU_mdkAsmDummy +******************************************************************************** +* This function provides ELF file symbols through +* the inline assembly. +* The inline assembly in the *.c file is chosen, because it allows using +* #include where the user configuration is updated. +* +* Note that this function does not have code, so no additional memory +* is allocated for it. +*******************************************************************************/ +__asm void cy_DFU_mdkAsmDummy(void) +{ + EXPORT __cy_boot_metadata_addr + EXPORT __cy_boot_metadata_length + + EXPORT __cy_app_core1_start_addr + + EXPORT __cy_product_id + EXPORT __cy_checksum_type + EXPORT __cy_app_id + + EXPORT __cy_app_verify_start + EXPORT __cy_app_verify_length + +/* Used by all DFU SDK applications to switch to another app */ +__cy_boot_metadata_addr EQU __cpp(CY_BOOT_METADATA_ADDR) +/* Used by CyMCUElfTool to update DFU SDK metadata with CRC-32C */ +__cy_boot_metadata_length EQU __cpp(CY_BOOT_METADATA_LENGTH) + +/* Used by CM0+ to start CM4 core in the DFU SDK applications. */ +/* Make sure the correct app no. is entered here */ +__cy_app_core1_start_addr EQU __cpp(CY_APP0_CORE1_FLASH_ADDR) + +/* Used by CyMCUElfTool to generate ProductID */ +__cy_product_id EQU __cpp(CY_PRODUCT_ID) +/* Used by CyMCUElfTool to generate ChecksumType */ +__cy_checksum_type EQU __cpp(CY_CHECKSUM_TYPE) +/* Application number (ID) */ +__cy_app_id EQU 0 + +/* CyMCUElfTool uses these to generate an application signature */ +/* The size of the default signature (CRC-32C) is 4 bytes */ +__cy_app_verify_start EQU __cpp(CY_APP0_CORE0_FLASH_ADDR) +__cy_app_verify_length EQU __cpp(CY_APP0_CORE0_FLASH_LENGTH + CY_APP0_CORE1_FLASH_LENGTH - CY_BOOT_SIGNATURE_SIZE) +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/dfu_user.h b/2020TPCApp1.cydsn/dfu_user.h new file mode 100644 index 0000000..e832d20 --- /dev/null +++ b/2020TPCApp1.cydsn/dfu_user.h @@ -0,0 +1,151 @@ +/***************************************************************************//** +* \file dfu_user.h +* \version 3.0 +* +* This file provides declarations that can be modified by the user but +* are used by the DFU SDK. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(DFU_USER_H) +#define DFU_USER_H + +#include +#include "cy_flash.h" + + +/** +* \addtogroup group_dfu_macro_config +* \{ +*/ + +/** The size of a buffer to hold DFU commands */ +/* 16 bytes is a maximum overhead of a DFU packet and additional data for the Program Data command */ +#define CY_DFU_SIZEOF_CMD_BUFFER (CY_FLASH_SIZEOF_ROW + 16u) + +/** The size of a buffer to hold an NVM row of data to write or verify */ +#define CY_DFU_SIZEOF_DATA_BUFFER (CY_FLASH_SIZEOF_ROW + 16u) + +/** +* Set to non-zero for the DFU SDK Program Data command to check +* if the Golden image is going to be overwritten while updating. +*/ +#define CY_DFU_OPT_GOLDEN_IMAGE (0) + +/** +* List of Golden Image Application IDs. +* Here "Golden Image Application" means an application that cannot be changed with +* CommandProgramData() +* +* Usage. Define the list of Golden Image Application IDs without enclosing +* parenthesis, e.g. +* \code #define CY_DFU_GOLDEN_IMAGE_IDS() 0u, 1u, 3u \endcode +* later it is used in cy_dfu.c file: +* \code uint8_t goldenImages[] = { CY_DFU_GOLDEN_IMAGE_IDS() }; \endcode +*/ +#define CY_DFU_GOLDEN_IMAGE_IDS() 0u + +/** +* The number of applications in the metadata, +* for 512 bytes in a Flash row - 63 is the maximum possible value, +* because 4 bytes are reserved for the entire metadata CRC. +* +* The smallest metadata size if CY_DFU_MAX_APPS * 8 (bytes per one app) + 4 (bytes for CRC-32C) +*/ +#define CY_DFU_MAX_APPS (2u) + + +/** A non-zero value enables the Verify Data DFU command */ +#define CY_DFU_OPT_VERIFY_DATA (1) + +/** A non-zero value enables the Erase Data DFU command */ +#define CY_DFU_OPT_ERASE_DATA (1) + +/** A non-zero value enables the Verify App DFU command */ +#define CY_DFU_OPT_VERIFY_APP (1) + +/** +* A non-zero value enables the Send Data DFU command. +* If the "Send Data" DFU command is enabled, \c packetBuffer and \c dataBuffer +* must be non-overlapping. +* +* Else, \c dataBuffer must be inside \c packetBuffer with an offset of +* \c CY_DFU_PACKET_DATA_IDX, typically 4 bytes. \n +* params->dataBuffer = &packetBuffer[4]; \n +* \note that \c packetBuffer in this case must be 4 bytes aligned, as +* \c dataBuffer is required to be 4 bytes aligned. +*/ +#define CY_DFU_OPT_SEND_DATA (1) + +/** A non-zero value enables the Get Metadata DFU command */ +#define CY_DFU_OPT_GET_METADATA (1) + +/** A non-zero value enables the Set EI Vector DFU command */ +#define CY_DFU_OPT_SET_EIVECTOR (0) + +/** +* A non-zero value allows writing metadata +* with the Set App Metadata DFU command. +*/ +#define CY_DFU_METADATA_WRITABLE (1) + +/** Non-zero value enables the usage of hardware Crypto API */ +#define CY_DFU_OPT_CRYPTO_HW (0) + +/** A non-zero value enables the usage of CRC-16 for DFU packet verification */ +#define CY_DFU_OPT_PACKET_CRC (0) + +/** Set the default application-format-possible values defined in \ref group_dfu_macro_app_type */ +#define CY_DFU_APP_FORMAT (CY_DFU_BASIC_APP) + +/** Set the default secure application-verification-type possible values + * defined in \ref group_dfu_macro_ver_type */ +#define CY_DFU_SEC_APP_VERIFY_TYPE (CY_DFU_VERIFY_FAST) + +/** \} group_dfu_macro_config */ + +#if !defined(CY_DOXYGEN) + #if defined(__GNUC__) || defined(__ICCARM__) + /* + * These variables are defined in the linker scripts, the values of their addresses define + * corresponding applications start address and length. + */ + extern uint8_t __cy_app0_verify_start; + extern uint8_t __cy_app0_verify_length; + extern uint8_t __cy_app1_verify_start; + extern uint8_t __cy_app1_verify_length; + extern uint8_t __cy_boot_signature_size; + + #define CY_DFU_APP0_VERIFY_START ( (uint32_t)&__cy_app0_verify_start ) + #define CY_DFU_APP0_VERIFY_LENGTH ( (uint32_t)&__cy_app0_verify_length ) + #define CY_DFU_APP1_VERIFY_START ( (uint32_t)&__cy_app1_verify_start ) + #define CY_DFU_APP1_VERIFY_LENGTH ( (uint32_t)&__cy_app1_verify_length ) + #define CY_DFU_SIGNATURE_SIZE ( (uint32_t)&__cy_boot_signature_size ) + + #elif defined(__ARMCC_VERSION) + #include "dfu_mdk_common.h" + + #define CY_DFU_APP0_VERIFY_START ( CY_APP0_CORE0_FLASH_ADDR ) + #define CY_DFU_APP0_VERIFY_LENGTH ( CY_APP0_CORE0_FLASH_LENGTH + CY_APP0_CORE1_FLASH_LENGTH \ + - CY_BOOT_SIGNATURE_SIZE) + #define CY_DFU_APP1_VERIFY_START ( CY_APP1_CORE0_FLASH_ADDR ) + #define CY_DFU_APP1_VERIFY_LENGTH ( CY_APP1_CORE0_FLASH_LENGTH + CY_APP1_CORE1_FLASH_LENGTH \ + - CY_BOOT_SIGNATURE_SIZE) + #define CY_DFU_SIGNATURE_SIZE CY_BOOT_SIGNATURE_SIZE + + #else + #error "Not implemented for this compiler" + #endif /* defined(__GNUC__) || defined(__ICCARM__) */ +#endif /* !defined(CY_DOXYGEN) */ + + +#endif /* !defined(DFU_USER_H) */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/gcc/startup_psoc6_01_cm0plus.S b/2020TPCApp1.cydsn/gcc/startup_psoc6_01_cm0plus.S new file mode 100644 index 0000000..e26df0a --- /dev/null +++ b/2020TPCApp1.cydsn/gcc/startup_psoc6_01_cm0plus.S @@ -0,0 +1,404 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .end + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/gcc/startup_psoc6_01_cm4.S b/2020TPCApp1.cydsn/gcc/startup_psoc6_01_cm4.S new file mode 100644 index 0000000..b904621 --- /dev/null +++ b/2020TPCApp1.cydsn/gcc/startup_psoc6_01_cm4.S @@ -0,0 +1,635 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/host_main.c b/2020TPCApp1.cydsn/host_main.c new file mode 100644 index 0000000..183ae11 --- /dev/null +++ b/2020TPCApp1.cydsn/host_main.c @@ -0,0 +1,505 @@ +/******************************************************************************* +* File Name: host_main.c +* +* Version: 1.0 +* +* Description: +* BLE HID keyboard example project that supports both input and output reports +* in boot and protocol mode. The example also demonstrates handling suspend +* event from the central device and enters low power mode when suspended. +* +* References: +* BLUETOOTH SPECIFICATION Version 5.0 +* HID Usage Tables spec ver 1.12 +* +* Hardware Dependency: +* CY8CKIT-062 PSoC6 BLE Pioneer Kit +* +****************************************************************************** +* Copyright (2019), Cypress Semiconductor Corporation. +****************************************************************************** +* This software is owned by Cypress Semiconductor Corporation (Cypress) and is +* protected by and subject to worldwide patent protection (United States and +* foreign), United States copyright laws and international treaty provisions. +* Cypress hereby grants to licensee a personal, non-exclusive, non-transferable +* license to copy, use, modify, create derivative works of, and compile the +* Cypress Source Code and derivative works for the sole purpose of creating +* custom software in support of licensee product to be used only in conjunction +* with a Cypress integrated circuit as specified in the applicable agreement. +* Any reproduction, modification, translation, compilation, or representation of +* this software except as specified above is prohibited without the express +* written permission of Cypress. +* +* Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH +* REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. +* Cypress reserves the right to make changes without further notice to the +* materials described herein. Cypress does not assume any liability arising out +* of the application or use of any product or circuit described herein. Cypress +* does not authorize its products for use as critical components in life-support +* systems where a malfunction or failure may reasonably be expected to result in +* significant injury to the user. The inclusion of Cypress' product in a life- +* support systems application implies that the manufacturer assumes all risk of +* such use and in doing so indemnifies Cypress against all charges. Use may be +* limited by and subject to the applicable Cypress software license agreement. +*****************************************************************************/ + +#include "dfu/cy_dfu.h" +#include "common.h" +#include "user_interface.h" +#include "ias.h" +#include "scps.h" + +/* Global Variables */ +cy_stc_ble_conn_handle_t appConnHandle; + +static volatile uint32_t mainTimer = 1u; +static cy_stc_ble_timer_info_t timerParam = { .timeout = ADV_TIMER_TIMEOUT }; + +/* Private Function Prototypes */ +static void LowPowerImplementation(void); + + +/******************************************************************************* +* Function Name: AppCallBack() +******************************************************************************** +* +* Summary: +* This is an event callback function to receive events from the BLE Component. +* +* event - the event code +* *eventParam - the event parameters +* +*******************************************************************************/ +void AppCallBack(uint32_t event, void* eventParam) +{ + cy_en_ble_api_result_t apiResult; + uint8_t i; + + static cy_stc_ble_gap_sec_key_info_t keyInfo = + { + .localKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST | + CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST | + CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST, + .exchangeKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST | + CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST | + CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST | + CY_BLE_GAP_SMP_RESP_ENC_KEY_DIST | + CY_BLE_GAP_SMP_RESP_IRK_KEY_DIST | + CY_BLE_GAP_SMP_RESP_CSRK_KEY_DIST, + }; + + switch (event) + { + /********************************************************** + * General Events + ***********************************************************/ + case CY_BLE_EVT_STACK_ON: /* This event is received when the component is Started */ + DBG_PRINTF("CY_BLE_EVT_STACK_ON, StartAdvertisement \r\n"); + + /* Enter into discoverable mode so that remote can find it. */ + apiResult = Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("Cy_BLE_GAPP_StartAdvertisement API Error: 0x%x \r\n", apiResult); + } + + /* Generates the security keys */ + apiResult = Cy_BLE_GAP_GenerateKeys(&keyInfo); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("Cy_BLE_GAP_GenerateKeys API Error: 0x%x \r\n", apiResult); + } + + /* Display Bond list */ + App_DisplayBondList(); + break; + + case CY_BLE_EVT_TIMEOUT: + if((((cy_stc_ble_timeout_param_t *)eventParam)->reasonCode == CY_BLE_GENERIC_APP_TO) && + (((cy_stc_ble_timeout_param_t *)eventParam)->timerHandle == timerParam.timerHandle)) + { + /* Update LED State */ + UpdateLedState(); + + /* Indicate that timer is raised to the main loop */ + mainTimer++; + + /* Press and hold the mechanical button (SW2) during 4 seconds to clear the bond list. */ + App_RemoveDevicesFromBondListBySW2Press(SW2_PRESS_TIME_DEL_BOND_LIST); + } + break; + + case CY_BLE_EVT_HARDWARE_ERROR: /* This event indicates that some internal HW error has occurred. */ + DBG_PRINTF("CY_BLE_EVT_HARDWARE_ERROR \r\n"); + ShowError(); + break; + + /* This event will be triggered by host stack if BLE stack is busy or not busy. + * Parameter corresponding to this event will be the state of BLE stack. + * BLE stack busy = CY_BLE_STACK_STATE_BUSY, + * BLE stack not busy = CY_BLE_STACK_STATE_FREE + */ + case CY_BLE_EVT_STACK_BUSY_STATUS: + DBG_PRINTF("CY_BLE_EVT_STACK_BUSY_STATUS: %x\r\n", *(uint8_t *)eventParam); + break; + + case CY_BLE_EVT_SET_TX_PWR_COMPLETE: + DBG_PRINTF("CY_BLE_EVT_SET_TX_PWR_COMPLETE \r\n"); + break; + + case CY_BLE_EVT_LE_SET_EVENT_MASK_COMPLETE: + DBG_PRINTF("CY_BLE_EVT_LE_SET_EVENT_MASK_COMPLETE \r\n"); + break; + + case CY_BLE_EVT_SET_DEVICE_ADDR_COMPLETE: + DBG_PRINTF("CY_BLE_EVT_SET_DEVICE_ADDR_COMPLETE \r\n"); + + /* Reads the BD device address from BLE Controller's memory */ + apiResult = Cy_BLE_GAP_GetBdAddress(); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("Cy_BLE_GAP_GetBdAddress API Error: 0x%x \r\n", apiResult); + } + break; + + case CY_BLE_EVT_GET_DEVICE_ADDR_COMPLETE: + DBG_PRINTF("CY_BLE_EVT_GET_DEVICE_ADDR_COMPLETE: "); + for(i = CY_BLE_GAP_BD_ADDR_SIZE; i > 0u; i--) + { + DBG_PRINTF("%2.2x", ((cy_stc_ble_bd_addrs_t *) + ((cy_stc_ble_events_param_generic_t *)eventParam)->eventParams)->publicBdAddr[i-1]); + } + DBG_PRINTF("\r\n"); + break; + + case CY_BLE_EVT_STACK_SHUTDOWN_COMPLETE: + DBG_PRINTF("CY_BLE_EVT_STACK_SHUTDOWN_COMPLETE \r\n"); + DBG_PRINTF("Hibernate \r\n"); + UART_DEB_WAIT_TX_COMPLETE(); + /* Hibernate */ + Cy_SysPm_Hibernate(); + break; + + /********************************************************** + * GAP Events + ***********************************************************/ + case CY_BLE_EVT_GAP_AUTH_REQ: + /* This event is received by Peripheral and Central devices. When it is received by a peripheral, + * that peripheral must Call Cy_BLE_GAPP_AuthReqReply() to reply to the authentication request + * from Central. */ + DBG_PRINTF("CY_BLE_EVT_GAP_AUTH_REQ: bdHandle=%x, security=%x, bonding=%x, ekeySize=%x, err=%x \r\n", + (*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle, (*(cy_stc_ble_gap_auth_info_t *)eventParam).security, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding, (*(cy_stc_ble_gap_auth_info_t *)eventParam).ekeySize, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + + if(cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].security == + (CY_BLE_GAP_SEC_MODE_1 | CY_BLE_GAP_SEC_LEVEL_1)) + { + cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].authErr = + CY_BLE_GAP_AUTH_ERROR_PAIRING_NOT_SUPPORTED; + } + + cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].bdHandle = + ((cy_stc_ble_gap_auth_info_t *)eventParam)->bdHandle; + + /* Pass security information for authentication in reply to an authentication request + * from the master device */ + apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]); + if(apiResult != CY_BLE_SUCCESS) + { + Cy_BLE_GAP_RemoveOldestDeviceFromBondedList(); + apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("Cy_BLE_GAPP_AuthReqReply API Error: 0x%x \r\n", apiResult); + } + } + break; + + case CY_BLE_EVT_GAP_PASSKEY_ENTRY_REQUEST: + DBG_PRINTF("CY_BLE_EVT_GAP_PASSKEY_ENTRY_REQUEST\r\n"); + DBG_PRINTF("Please enter the passkey displayed on the peer device:\r\n"); + break; + + case CY_BLE_EVT_GAP_PASSKEY_DISPLAY_REQUEST: + DBG_PRINTF("CY_BLE_EVT_GAP_PASSKEY_DISPLAY_REQUEST: %6.6ld\r\n", *(uint32_t *)eventParam); + break; + + case CY_BLE_EVT_GAP_NUMERIC_COMPARISON_REQUEST: + DBG_PRINTF("Compare this passkey with the one displayed in your peer device and press 'y' or 'n':" + " %6.6lu \r\n", *(uint32_t *)eventParam); + break; + + case CY_BLE_EVT_GAP_KEYINFO_EXCHNGE_CMPLT: + DBG_PRINTF("CY_BLE_EVT_GAP_KEYINFO_EXCHNGE_CMPLT \r\n"); + break; + + case CY_BLE_EVT_GAP_SMP_NEGOTIATED_AUTH_INFO: + DBG_PRINTF("CY_BLE_EVT_GAP_SMP_NEGOTIATED_AUTH_INFO:" + " bdHandle=%x, security=%x, bonding=%x, ekeySize=%x, err=%x \r\n", + (*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).security, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).ekeySize, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + break; + + case CY_BLE_EVT_GAP_AUTH_COMPLETE: + DBG_PRINTF("CY_BLE_EVT_GAP_AUTH_COMPLETE: bdHandle=%x, security=%x, bonding=%x, ekeySize=%x, err=%x \r\n", + (*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).security, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).ekeySize, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + break; + + case CY_BLE_EVT_GAP_AUTH_FAILED: + DBG_PRINTF("CY_BLE_EVT_GAP_AUTH_FAILED: bdHandle=%x, authErr=%x\r\n", + (*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle, + (*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + break; + + case CY_BLE_EVT_GAPP_ADVERTISEMENT_START_STOP: + DBG_PRINTF("CY_BLE_EVT_GAPP_ADVERTISEMENT_START_STOP, state: %d \r\n", Cy_BLE_GetAdvertisementState()); + if((Cy_BLE_GetAdvertisementState() == CY_BLE_ADV_STATE_STOPPED) && (Cy_BLE_GetNumOfActiveConn() == 0u)) + { + /* Fast and slow advertising period complete, go to low power + * mode (Hibernate) and wait for an external + * user event to wake up the device again */ + UpdateLedState(); + Cy_BLE_Stop(); + } + break; + + case CY_BLE_EVT_GAP_DEVICE_CONNECTED: + DBG_PRINTF("CY_BLE_EVT_GAP_DEVICE_CONNECTED: connIntv = %d ms \r\n", + ((cy_stc_ble_gap_connected_param_t *)eventParam)->connIntv * 5u /4u); /* in milliseconds / 1.25ms */ + + + + /* Set security keys for new device which is not already bonded */ + if(App_IsDeviceInBondList((*(cy_stc_ble_gap_connected_param_t *)eventParam).bdHandle) == 0u) + { + keyInfo.SecKeyParam.bdHandle = (*(cy_stc_ble_gap_connected_param_t *)eventParam).bdHandle; + apiResult = Cy_BLE_GAP_SetSecurityKeys(&keyInfo); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("Cy_BLE_GAP_SetSecurityKeys API Error: 0x%x \r\n", apiResult); + } + } + break; + + case CY_BLE_EVT_L2CAP_CONN_PARAM_UPDATE_RSP: + DBG_PRINTF("CY_BLE_EVT_L2CAP_CONN_PARAM_UPDATE_RSP, result = %d\r\n", + (*(cy_stc_ble_l2cap_conn_update_rsp_param_t *)eventParam).result); + break; + + case CY_BLE_EVT_GAP_KEYS_GEN_COMPLETE: + DBG_PRINTF("CY_BLE_EVT_GAP_KEYS_GEN_COMPLETE \r\n"); + keyInfo.SecKeyParam = (*(cy_stc_ble_gap_sec_key_param_t *)eventParam); + Cy_BLE_GAP_SetIdAddress(&cy_ble_deviceAddress); + break; + + case CY_BLE_EVT_GAP_CONNECTION_UPDATE_COMPLETE: + DBG_PRINTF("CY_BLE_EVT_GAP_CONNECTION_UPDATE_COMPLETE: connIntv = %d ms \r\n", /* in milliseconds / 1.25ms */ + ((cy_stc_ble_gap_conn_param_updated_in_controller_t *)eventParam)->connIntv * 5u /4u); + break; + + case CY_BLE_EVT_GAP_DEVICE_DISCONNECTED: + DBG_PRINTF("CY_BLE_EVT_GAP_DEVICE_DISCONNECTED: bdHandle=%x, reason=%x, status=%x\r\n", + (*(cy_stc_ble_gap_disconnect_param_t *)eventParam).bdHandle, + (*(cy_stc_ble_gap_disconnect_param_t *)eventParam).reason, + (*(cy_stc_ble_gap_disconnect_param_t *)eventParam).status); + + /* Put the device into discoverable mode so that a remote can search it. */ + apiResult = Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("StartAdvertisement API Error: 0x%x \r\n", apiResult); + } + break; + + case CY_BLE_EVT_GAP_ENCRYPT_CHANGE: + DBG_PRINTF("CY_BLE_EVT_GAP_ENCRYPT_CHANGE: %x \r\n", *(uint8_t *)eventParam); + break; + + /********************************************************** + * GATT Events + ***********************************************************/ + case CY_BLE_EVT_GATT_CONNECT_IND: + appConnHandle = *(cy_stc_ble_conn_handle_t *)eventParam; + DBG_PRINTF("CY_BLE_EVT_GATT_CONNECT_IND: %x, %x \r\n", + (*(cy_stc_ble_conn_handle_t *)eventParam).attId, (*(cy_stc_ble_conn_handle_t *)eventParam).bdHandle); + + break; + + case CY_BLE_EVT_GATT_DISCONNECT_IND: + DBG_PRINTF("CY_BLE_EVT_GATT_DISCONNECT_IND: %x, %x \r\n", + (*(cy_stc_ble_conn_handle_t *)eventParam).attId, (*(cy_stc_ble_conn_handle_t *)eventParam).bdHandle); + break; + + case CY_BLE_EVT_GATTS_XCNHG_MTU_REQ: + { + cy_stc_ble_gatt_xchg_mtu_param_t mtu = + { + .connHandle = ((cy_stc_ble_gatt_xchg_mtu_param_t *)eventParam)->connHandle + }; + Cy_BLE_GATT_GetMtuSize(&mtu); + DBG_PRINTF("CY_BLE_EVT_GATTS_XCNHG_MTU_REQ %x, %x, final mtu= %d \r\n", + mtu.connHandle.attId, mtu.connHandle.bdHandle, mtu.mtu); + } + break; + + case CY_BLE_EVT_GATTS_READ_CHAR_VAL_ACCESS_REQ: + DBG_PRINTF("CY_BLE_EVT_GATTS_READ_CHAR_VAL_ACCESS_REQ %x %x: handle: %x \r\n", + ((cy_stc_ble_gatts_char_val_read_req_t *)eventParam)->connHandle.attId, + ((cy_stc_ble_gatts_char_val_read_req_t *)eventParam)->connHandle.bdHandle, + ((cy_stc_ble_gatts_char_val_read_req_t *)eventParam)->attrHandle); + break; + + case CY_BLE_EVT_GATTS_WRITE_REQ: + DBG_PRINTF("CY_BLE_EVT_GATTS_WRITE_REQ attr handle: %4.4x , value: ", + ((cy_stc_ble_gatts_write_cmd_req_param_t *)eventParam)->handleValPair.attrHandle); + for(i = 0; i < ((cy_stc_ble_gatts_write_cmd_req_param_t *)eventParam)->handleValPair.value.len; i++) + { + DBG_PRINTF("%2.2x ", ((cy_stc_ble_gatts_write_cmd_req_param_t *)eventParam)->handleValPair.value.val[i]); + } + DBG_PRINTF("\r\n"); + break; + + case CY_BLE_EVT_GATTS_INDICATION_DISABLED: + DBG_PRINTF("CY_BLE_EVT_GATTS_INDICATION_DISABLED \r\n"); + break; + + case CY_BLE_EVT_GATTS_INDICATION_ENABLED: + DBG_PRINTF("CY_BLE_EVT_GATTS_INDICATION_ENABLED \r\n"); + break; + + /********************************************************** + * Other Events + ***********************************************************/ + case CY_BLE_EVT_PENDING_FLASH_WRITE: + /* Inform application that flash write is pending. Stack internal data + * structures are modified and require to be stored in Flash using + * Cy_BLE_StoreBondingData() */ + DBG_PRINTF("CY_BLE_EVT_PENDING_FLASH_WRITE\r\n"); + break; + + default: + DBG_PRINTF("Other event: 0x%lx \r\n", event); + break; + } +} + + +/******************************************************************************* +* Function Name: LowPowerImplementation() +******************************************************************************** +* Summary: +* Implements low power in the project. +* +* Theory: +* The function tries to enter deep sleep as much as possible - whenever the +* BLE is idle and the UART transmission/reception is not happening. +* +*******************************************************************************/ +static void LowPowerImplementation(void) +{ + if(UART_DEB_IS_TX_COMPLETE() != 0u) + { + /* Entering into the Deep Sleep */ + Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT); + } +} + + +/******************************************************************************* +* Function Name: HostMain() +******************************************************************************** +* Summary: +* Main function for the project. +* +*******************************************************************************/ +int HostMain(void) +{ + cy_en_ble_api_result_t apiResult; + + /* Initialization the user interface: LEDs, SW2, ect. */ + InitUserInterface(); + + /* Initialize Debug UART */ + UART_START(); + DBG_PRINTF("BLE HID Keyboard Example\r\n"); + + /* Start BLE component and register generic event handler */ + apiResult = Cy_BLE_Start(AppCallBack); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("Cy_BLE_Start API Error: 0x%x \r\n", apiResult); + } + + /* Initialize BLE Services */ + ScpsInit(); + IasInit(); + + + /*************************************************************************** + * Main polling loop + ***************************************************************************/ + while(1) + { + /* Cy_BLE_ProcessEvents() allows BLE stack to process pending events */ + Cy_BLE_ProcessEvents(); + + /* To achieve low power in the device */ + LowPowerImplementation(); + + /* Restart 1s timer */ + if(mainTimer != 0u) + { + mainTimer = 0u; + Cy_BLE_StartTimer(&timerParam); + } + + /* Remove devices from the bond list. Should be done when no active connections */ + if((Cy_BLE_GetNumOfActiveConn() == 0u) && (App_IsRemoveBondListFlag() == true)) + { + App_RemoveDevicesFromBondList(); + } + + #if(CY_BLE_BONDING_REQUIREMENT == CY_BLE_BONDING_YES) + /* Store bonding data to flash only when all debug information has been sent */ + if(cy_ble_pendingFlashWrite != 0u) + { + apiResult = Cy_BLE_StoreBondingData(); + DBG_PRINTF("Store bonding data, status: %x, pending: %x \r\n", apiResult, cy_ble_pendingFlashWrite); + } + #endif /* CY_BLE_BONDING_REQUIREMENT == CY_BLE_BONDING_YES */ + + if (alertLevel != 0u) + { + cy_stc_ble_gap_disconnect_info_t disconnectInfoParam = + { + .bdHandle = appConnHandle.bdHandle, + .reason = CY_BLE_HCI_ERROR_OTHER_END_TERMINATED_USER + }; + + /* Initiate disconnection from the peer device*/ + if(Cy_BLE_GAP_Disconnect(&disconnectInfoParam) == CY_BLE_SUCCESS) + { + /* Wait for disconnection event */ + while(Cy_BLE_GetConnectionState(appConnHandle) == CY_BLE_CONN_STATE_CONNECTED) + { + /* Process BLE events */ + Cy_BLE_ProcessEvents(); + } + } + /* Stop BLE component. */ + Cy_BLE_Disable(); + Cy_DFU_ExecuteApp(0u); + } + } +} + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/iar/startup_psoc6_01_cm0plus.s b/2020TPCApp1.cydsn/iar/startup_psoc6_01_cm0plus.s new file mode 100644 index 0000000..a867384 --- /dev/null +++ b/2020TPCApp1.cydsn/iar/startup_psoc6_01_cm0plus.s @@ -0,0 +1,423 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Power Mode Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK NvicMux8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux8_IRQHandler + B NvicMux8_IRQHandler + + PUBWEAK NvicMux9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux9_IRQHandler + B NvicMux9_IRQHandler + + PUBWEAK NvicMux10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux10_IRQHandler + B NvicMux10_IRQHandler + + PUBWEAK NvicMux11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux11_IRQHandler + B NvicMux11_IRQHandler + + PUBWEAK NvicMux12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux12_IRQHandler + B NvicMux12_IRQHandler + + PUBWEAK NvicMux13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux13_IRQHandler + B NvicMux13_IRQHandler + + PUBWEAK NvicMux14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux14_IRQHandler + B NvicMux14_IRQHandler + + PUBWEAK NvicMux15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux15_IRQHandler + B NvicMux15_IRQHandler + + PUBWEAK NvicMux16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux16_IRQHandler + B NvicMux16_IRQHandler + + PUBWEAK NvicMux17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux17_IRQHandler + B NvicMux17_IRQHandler + + PUBWEAK NvicMux18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux18_IRQHandler + B NvicMux18_IRQHandler + + PUBWEAK NvicMux19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux19_IRQHandler + B NvicMux19_IRQHandler + + PUBWEAK NvicMux20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux20_IRQHandler + B NvicMux20_IRQHandler + + PUBWEAK NvicMux21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux21_IRQHandler + B NvicMux21_IRQHandler + + PUBWEAK NvicMux22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux22_IRQHandler + B NvicMux22_IRQHandler + + PUBWEAK NvicMux23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux23_IRQHandler + B NvicMux23_IRQHandler + + PUBWEAK NvicMux24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux24_IRQHandler + B NvicMux24_IRQHandler + + PUBWEAK NvicMux25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux25_IRQHandler + B NvicMux25_IRQHandler + + PUBWEAK NvicMux26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux26_IRQHandler + B NvicMux26_IRQHandler + + PUBWEAK NvicMux27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux27_IRQHandler + B NvicMux27_IRQHandler + + PUBWEAK NvicMux28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux28_IRQHandler + B NvicMux28_IRQHandler + + PUBWEAK NvicMux29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux29_IRQHandler + B NvicMux29_IRQHandler + + PUBWEAK NvicMux30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux30_IRQHandler + B NvicMux30_IRQHandler + + PUBWEAK NvicMux31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux31_IRQHandler + B NvicMux31_IRQHandler + + + END + + +; [] END OF FILE diff --git a/2020TPCApp1.cydsn/iar/startup_psoc6_01_cm4.s b/2020TPCApp1.cydsn/iar/startup_psoc6_01_cm4.s new file mode 100644 index 0000000..6f1e869 --- /dev/null +++ b/2020TPCApp1.cydsn/iar/startup_psoc6_01_cm4.s @@ -0,0 +1,1142 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/2020TPCApp1.cydsn/ias.c b/2020TPCApp1.cydsn/ias.c new file mode 100644 index 0000000..43c8e63 --- /dev/null +++ b/2020TPCApp1.cydsn/ias.c @@ -0,0 +1,62 @@ +/******************************************************************************* +* File Name: ias.c +* +* Description: +* This file contains Immediate Alert Service callback handler function. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "ias.h" + + +/* IAS alert level value */ +volatile uint8_t alertLevel = 0; + +/****************************************************************************** +* Function Name: IasInit +******************************************************************************* +* +* Summary: +* Registers the IAS CallBack. +* +******************************************************************************/ +void IasInit(void) +{ + Cy_BLE_IAS_RegisterAttrCallback(IasEventHandler); +} + + +/******************************************************************************* +* Function Name: IasEventHandler +******************************************************************************** +* +* Summary: +* This is an event callback function to receive events from the BLE Component, +* which are specific to Immediate Alert Service. +* +* Parameters: +* event: Write Command event from the BLE component. +* eventParams: A structure instance of CY_BLE_GATT_HANDLE_VALUE_PAIR_T type. +* +*******************************************************************************/ +void IasEventHandler(uint32 event, void *eventParam) +{ + (void) eventParam; + uint8_t alert; + /* Alert Level Characteristic write event */ + if(event == CY_BLE_EVT_IASS_WRITE_CHAR_CMD) + { + /* Read the updated Alert Level value from the GATT database */ + Cy_BLE_IASS_GetCharacteristicValue(CY_BLE_IAS_ALERT_LEVEL, sizeof(alert), &alert); + alertLevel = alert; + } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/ias.h b/2020TPCApp1.cydsn/ias.h new file mode 100644 index 0000000..ae43d33 --- /dev/null +++ b/2020TPCApp1.cydsn/ias.h @@ -0,0 +1,41 @@ +/******************************************************************************* +* File Name: ias.h +* +* Description: +* Contains the function prototypes and constants available to the example +* project. +* +******************************************************************************** +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include + + +/*************************************** +* API Constants +***************************************/ +#define NO_ALERT (0u) +#define MILD_ALERT (1u) +#define HIGH_ALERT (2u) + +#define LED_TOGGLE_TIMEOUT (100u) + + +/*************************************** +* Function Prototypes +***************************************/ +void IasInit(void); +void IasEventHandler(uint32_t event, void *eventParam); + + +/*************************************** +* External data references +***************************************/ +extern volatile uint8_t alertLevel; + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/main_cm0p.c b/2020TPCApp1.cydsn/main_cm0p.c new file mode 100644 index 0000000..4ef1811 --- /dev/null +++ b/2020TPCApp1.cydsn/main_cm0p.c @@ -0,0 +1,81 @@ +#include "dfu/cy_dfu.h" +#include "project.h" +#include "common.h" +#include "cy_si_config.h" + +#include "COMM_IPC_Messages.h" + +/* App1 Start Address, change define if different */ +#define APP_1_START_ADDRESS 0x10040000 + +/* Cypress Standard Application Format Header */ +CY_SECTION(".cy_app_header") __USED +const cy_stc_user_appheader_t applicationHeader = +{ + .objSize = CY_DFU_APP1_VERIFY_LENGTH, /* App Size to authenticate */ + .appId = CY_SI_APP_VERSION, /* App ID */ + .appAttributes = 0UL, /* Reserved */ + .numCores = 2UL, /* Number of cores in the application */ + .core0Vt = (uint32_t)(&__Vectors[0]) - APP_1_START_ADDRESS - offsetof(cy_stc_user_appheader_t, core0Vt), /* Offset to CM0+ Vector Table in flash */ + .core1Vt = (uint32_t)(&__cy_app_core1_start_addr) - APP_1_START_ADDRESS - offsetof(cy_stc_user_appheader_t, core1Vt), /* Offset to CM4 Vector Table in flash */ + .core0Id = CY_ARM_CM0P_CPUID, /* ARM CM0+ CPU ID */ + .core1Id = CY_ARM_CM4_CPUID, /* ARM CM4 CPU ID */ +}; + + +/******************************************************************************* +* Function Name: main() +******************************************************************************** +* +* Summary: +* Main function for the project. +* +* +*******************************************************************************/ +int main(void) +{ + + /* Unfreeze IO after Hibernate */ + if(Cy_SysPm_GetIoFreezeStatus()) + { + Cy_SysPm_IoUnfreeze(); + } + + /* Enable global interrupts. */ + __enable_irq(); + +#if(CY_BLE_CONFIG_HOST_CORE == CY_BLE_CORE_CORTEX_M0P) + COMM_InitIPCMessages(); + + /* Enable CM4. CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */ + Cy_SysEnableCM4( (uint32_t)(&__cy_app_core1_start_addr) ); + + /* Run Host main */ + HostMain(); + +#else + + #if(CY_BLE_STACK_MODE_IPC) + /* Start BLE Controller for dual core mode */ + Cy_BLE_Start(NULL); + #endif /* (CY_BLE_STACK_MODE_IPC)*/ + + COMM_InitIPCMessages(); + + /* Enable CM4. CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */ + Cy_SysEnableCM4( (uint32_t)(&__cy_app_core1_start_addr) ); + + while(true) + { + #if(CY_BLE_STACK_MODE_IPC) + /* Process BLE events continuously for controller in dual core mode */ + Cy_BLE_ProcessEvents(); + #endif /* CY_BLE_STACK_MODE_IPC */ + + /* To achieve low power in the device */ + Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT); + } + +#endif /* (CY_BLE_HOST_CORE == CY_CPU_CORTEX_M0P) */ +} + diff --git a/2020TPCApp1.cydsn/main_cm4.c b/2020TPCApp1.cydsn/main_cm4.c new file mode 100644 index 0000000..b41075e --- /dev/null +++ b/2020TPCApp1.cydsn/main_cm4.c @@ -0,0 +1,114 @@ +/** \file + * \brief This file provides the entry point for the application running on the Cortex-M4 core. + * + * ## CapSense + * To tune the CapSense buttons, do the following: + * 1. Define `TUNE_CAPSENSE` below. + * 2. Rebuild the project, and load it on to your board. + * 3. Right-click on the `CapSense` component on the "CapSense" schematic page in `TopDesign.cysch`, and choose "Launch Tuner". + * 4. Follow the instructions in [AN85951 - PSoC 4 and PSoC 6 MCU CapSense Design Guide](https://www.cypress.com/documentation/application-notes/an85951-psoc-4-and-psoc-6-mcu-capsense-design-guide) to complete the tuning. + * + */ + + +/* Include Files */ +#include "KTag.h" + + +// See the instructions at the top of this file for how to tune CapSense--this is only part of what you need. +//#define TUNE_CAPSENSE + + +/* This section is used to verify an application signature + For sha256 verification, set the number of elements in the array to 64, and + in bootload_common.ld set __cy_boot_signature_size = 256. +*/ +CY_SECTION(".cy_app_signature") __USED static const uint32_t cy_bootload_appSignature[64]; + + +#ifndef TUNE_CAPSENSE +int main() +{ + CONFIG_InitTasks(); + + /* Enable global interrupts. */ + __enable_irq(); + + COMM_InitIPCMessages(); + + CONFIG_RunTasks(); +} +#endif // TUNE_CAPSENSE + + +void vApplicationIdleHook(void) +{ + CyDelay(500); +} + + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + /* Halt the CPU */ + CY_ASSERT(0); +} + + +void vApplicationMallocFailedHook( void ) +{ + /* Halt the CPU */ + CY_ASSERT(0); +} + + +#ifdef TUNE_CAPSENSE +int main() +{ + uint8 header[] = {0x0Du, 0x0Au}; + uint8 tail[] = {0x00u, 0xFFu, 0xFFu}; + + __enable_irq(); /* Enable global interrupts. */ + + UART_Console_Start(); /* Start UART SCB Component */ + CapSense_Start(); /* Initialize Component */ + CapSense_ScanAllWidgets(); /* Scan all widgets */ + + for(;;) + { + /* Do this only when a scan is done */ + if(CapSense_NOT_BUSY == CapSense_IsBusy()) + { + CapSense_ProcessAllWidgets(); /* Process all widgets */ + + /* Send packet header */ + UART_Console_PutArrayBlocking((uint8 *)(&header), sizeof(header)); + /* Send packet with CapSense data */ + UART_Console_PutArrayBlocking((uint8 *)(&CapSense_dsRam), sizeof(CapSense_dsRam)); + /* Send packet tail */ + UART_Console_PutArrayBlocking((uint8 *)(&tail), sizeof(tail)); + + CapSense_ScanAllWidgets(); /* Start next scan */ + } + } +} +#endif // TUNE_CAPSENSE + +void vApplicationGetIdleTaskMemory(StaticTask_t** ppxIdleTaskTCBBuffer, StackType_t** ppxIdleTaskStackBuffer, uint32_t* pulIdleTaskStackSize) +{ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE]; + + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} + +void vApplicationGetTimerTaskMemory(StaticTask_t** ppxTimerTaskTCBBuffer, StackType_t** ppxTimerTaskStackBuffer, uint32_t* pulTimerTaskStackSize) +{ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH]; + + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} \ No newline at end of file diff --git a/2020TPCApp1.cydsn/mdk/startup_psoc6_01_cm0plus.s b/2020TPCApp1.cydsn/mdk/startup_psoc6_01_cm0plus.s new file mode 100644 index 0000000..9358665 --- /dev/null +++ b/2020TPCApp1.cydsn/mdk/startup_psoc6_01_cm0plus.s @@ -0,0 +1,321 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT NvicMux8_IRQHandler [WEAK] + EXPORT NvicMux9_IRQHandler [WEAK] + EXPORT NvicMux10_IRQHandler [WEAK] + EXPORT NvicMux11_IRQHandler [WEAK] + EXPORT NvicMux12_IRQHandler [WEAK] + EXPORT NvicMux13_IRQHandler [WEAK] + EXPORT NvicMux14_IRQHandler [WEAK] + EXPORT NvicMux15_IRQHandler [WEAK] + EXPORT NvicMux16_IRQHandler [WEAK] + EXPORT NvicMux17_IRQHandler [WEAK] + EXPORT NvicMux18_IRQHandler [WEAK] + EXPORT NvicMux19_IRQHandler [WEAK] + EXPORT NvicMux20_IRQHandler [WEAK] + EXPORT NvicMux21_IRQHandler [WEAK] + EXPORT NvicMux22_IRQHandler [WEAK] + EXPORT NvicMux23_IRQHandler [WEAK] + EXPORT NvicMux24_IRQHandler [WEAK] + EXPORT NvicMux25_IRQHandler [WEAK] + EXPORT NvicMux26_IRQHandler [WEAK] + EXPORT NvicMux27_IRQHandler [WEAK] + EXPORT NvicMux28_IRQHandler [WEAK] + EXPORT NvicMux29_IRQHandler [WEAK] + EXPORT NvicMux30_IRQHandler [WEAK] + EXPORT NvicMux31_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +NvicMux8_IRQHandler +NvicMux9_IRQHandler +NvicMux10_IRQHandler +NvicMux11_IRQHandler +NvicMux12_IRQHandler +NvicMux13_IRQHandler +NvicMux14_IRQHandler +NvicMux15_IRQHandler +NvicMux16_IRQHandler +NvicMux17_IRQHandler +NvicMux18_IRQHandler +NvicMux19_IRQHandler +NvicMux20_IRQHandler +NvicMux21_IRQHandler +NvicMux22_IRQHandler +NvicMux23_IRQHandler +NvicMux24_IRQHandler +NvicMux25_IRQHandler +NvicMux26_IRQHandler +NvicMux27_IRQHandler +NvicMux28_IRQHandler +NvicMux29_IRQHandler +NvicMux30_IRQHandler +NvicMux31_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, =Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, =(Heap_Mem + Heap_Size) + LDR R3, =Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END + + +; [] END OF FILE diff --git a/2020TPCApp1.cydsn/mdk/startup_psoc6_01_cm4.s b/2020TPCApp1.cydsn/mdk/startup_psoc6_01_cm4.s new file mode 100644 index 0000000..c41752b --- /dev/null +++ b/2020TPCApp1.cydsn/mdk/startup_psoc6_01_cm4.s @@ -0,0 +1,696 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Power Mode Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END + + +; [] END OF FILE diff --git a/2020TPCApp1.cydsn/post_build_core1.bat b/2020TPCApp1.cydsn/post_build_core1.bat new file mode 100644 index 0000000..569f28d --- /dev/null +++ b/2020TPCApp1.cydsn/post_build_core1.bat @@ -0,0 +1,44 @@ +@rem Usage: +@rem Call post_build_core1.bat +@rem E.g. in PSoC Creator 4.2: +@rem post_build_core1.bat creator ${OutputDir} ${ProjectShortName} + +@echo ------------------------------------------ +@echo Post-build commands for Cortex-M4 core +@echo ------------------------------------------ + +@rem Set proper path to your PDL 3.x and above installation +@set PDL_PATH="C:\Program Files (x86)\Cypress\PDL\3.1.7" + +@set CY_MCU_ELF_TOOL=%PDL_PATH%"\tools\win\elf\cymcuelftool.exe" + +@set IDE=%1 + +@if "%IDE%" == "creator" ( + @set OUTPUT_DIR=%2 + @set PRJ_NAME=%3 + @set ELF_EXT=.elf +) + +@if "%IDE%" == "uvision" ( + @set OUTPUT_DIR=%2 + @set PRJ_NAME=%3 + @set ELF_EXT=.axf +) + +@if "%IDE%" == "iar" ( + @set OUTPUT_DIR=%2 + @set PRJ_NAME=%3 + @set ELF_EXT=.out +) + +@if "%IDE%" == "eclipse" ( + @set OUTPUT_DIR=%2 + @set PRJ_NAME=%3 + @set ELF_EXT=.out +) + +@rem Sign the application with the RSA private key +%CY_MCU_ELF_TOOL% -S %OUTPUT_DIR%\%PRJ_NAME%%ELF_EXT% SHA256 --encrypt RSASSA-PKCS --key ..\Keys\rsa_private.txt --output %OUTPUT_DIR%\%PRJ_NAME%_RSA%ELF_EXT% --hex %OUTPUT_DIR%\%PRJ_NAME%.hex + +%CY_MCU_ELF_TOOL% -P %OUTPUT_DIR%\%PRJ_NAME%_RSA%ELF_EXT% --output %OUTPUT_DIR%\%PRJ_NAME%.cyacd2 \ No newline at end of file diff --git a/2020TPCApp1.cydsn/scps.c b/2020TPCApp1.cydsn/scps.c new file mode 100644 index 0000000..0ee35f2 --- /dev/null +++ b/2020TPCApp1.cydsn/scps.c @@ -0,0 +1,141 @@ +/******************************************************************************* +* File Name: scps.c +* +* Version: 1.0 +* +* Description: +* This file contains the code for the SCPS. +* +* Hardware Dependency: +* CY8CKIT-062 PSoC6 BLE Pioneer Kit +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "common.h" +#include "scps.h" + +/* Static global variables */ +static uint16_t scanInterval = 0u; +static uint16_t scanWindow = 0u; +static bool requestScanRefresh = true; + +/******************************************************************************* +* Function Name: ScpsInit() +******************************************************************************** +* +* Summary: +* Initializes the SCPS Service. +* +*******************************************************************************/ +void ScpsInit(void) +{ + /* Register service specific callback function */ + Cy_BLE_SCPS_RegisterAttrCallback(ScpsCallBack); + + requestScanRefresh = true; +} + + +/******************************************************************************* +* Function Name: ScpsCallBack() +******************************************************************************** +* +* Summary: +* This is an event callback function to receive service specific events from +* SCPS Service. +* +* Parameters: +* event - the event code +* eventParam - the event parameters +* +********************************************************************************/ +void ScpsCallBack (uint32_t event, void *eventParam) +{ + DBG_PRINTF("SCPS event: %lx, ", event); + switch(event) + { + case CY_BLE_EVT_SCPSS_NOTIFICATION_ENABLED: + DBG_PRINTF("CY_BLE_EVT_SCPSS_NOTIFICATION_ENABLED %x %x \r\n", + ((cy_stc_ble_scps_char_value_t *)eventParam)->connHandle.attId, + ((cy_stc_ble_scps_char_value_t *)eventParam)->connHandle.bdHandle); + break; + + case CY_BLE_EVT_SCPSS_NOTIFICATION_DISABLED: + DBG_PRINTF("CY_BLE_EVT_SCPSS_NOTIFICATION_DISABLED %x %x \r\n", + ((cy_stc_ble_scps_char_value_t *)eventParam)->connHandle.attId, + ((cy_stc_ble_scps_char_value_t *)eventParam)->connHandle.bdHandle); + break; + + case CY_BLE_EVT_SCPSS_SCAN_INT_WIN_WRITE_CHAR: + scanInterval = Cy_BLE_Get16ByPtr(((cy_stc_ble_scps_char_value_t *)eventParam)->value->val); + scanWindow = Cy_BLE_Get16ByPtr(((cy_stc_ble_scps_char_value_t *)eventParam)->value->val + + sizeof(scanInterval)); + DBG_PRINTF("CY_BLE_EVT_SCPSS_SCAN_INT_WIN_WRITE_CHAR scanInterval: %x, scanWindow: %x \r\n", + scanInterval, scanWindow); + break; + + case CY_BLE_EVT_SCPSC_NOTIFICATION: + break; + + case CY_BLE_EVT_SCPSC_READ_DESCR_RESPONSE: + break; + + case CY_BLE_EVT_SCPSC_WRITE_DESCR_RESPONSE: + break; + + default: + DBG_PRINTF("Not supported event\r\n"); + break; + } +} + + +/******************************************************************************* +* Function Name: ScpsSendReqUpdateConnParam() +******************************************************************************** +* +* Summary: +* Send notification to request update connection parameters +* +* Parameters: +* connHandle: The connection handle +* +********************************************************************************/ +void ScpsSendReqUpdateConnParam(cy_stc_ble_conn_handle_t connHandle) +{ + cy_en_ble_api_result_t apiResult; + uint8_t refresh = CY_BLE_SCAN_REFRESH_ENABLED; + uint16 cccd = CY_BLE_CCCD_DEFAULT; + + if(requestScanRefresh == true) + { + apiResult = Cy_BLE_SCPSS_GetCharacteristicDescriptor(connHandle, CY_BLE_SCPS_SCAN_REFRESH, + CY_BLE_SCPS_SCAN_REFRESH_CCCD, CY_BLE_CCCD_LEN, + (uint8_t *)&cccd); + + if((apiResult == CY_BLE_SUCCESS) && (cccd == CY_BLE_CCCD_NOTIFICATION)) + { + /* Send notification to request update connection parameters */ + apiResult = Cy_BLE_SCPSS_SendNotification(connHandle, CY_BLE_SCPS_SCAN_REFRESH, sizeof(refresh), &refresh); + if(apiResult != CY_BLE_SUCCESS) + { + DBG_PRINTF("Cy_BLE_SCPSS_SendNotification API Error: 0x%x \r\n", apiResult); + } + else + { + requestScanRefresh = false; + } + } + + /* Cy_BLE_ProcessEvents() allows BLE stack to process pending events */ + Cy_BLE_ProcessEvents(); + } +} + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/scps.h b/2020TPCApp1.cydsn/scps.h new file mode 100644 index 0000000..b565dcd --- /dev/null +++ b/2020TPCApp1.cydsn/scps.h @@ -0,0 +1,26 @@ +/******************************************************************************* +* File Name: scps.h +* +* Version 1.0 +* +* Description: +* Contains the function prototypes and constants available for SCPS +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include + + +/*************************************** +* Function Prototypes +***************************************/ +void ScpsInit(void); +void ScpsCallBack (uint32_t event, void *eventParam); +void ScpsSendReqUpdateConnParam(cy_stc_ble_conn_handle_t connHandle); + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/stdio_user.c b/2020TPCApp1.cydsn/stdio_user.c new file mode 100644 index 0000000..077d110 --- /dev/null +++ b/2020TPCApp1.cydsn/stdio_user.c @@ -0,0 +1,65 @@ +/***************************************************************************//** +* \file stdio_user.c +* \version 1.20 +* +* \brief +* This file provides low level function implementation to retarget +* I/O functions of the standard C run-time library. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "stdio_user.h" + +#if defined (IO_STDOUT_ENABLE) && defined (IO_STDOUT_UART) +/******************************************************************************* +* Function Name: STDIO_PutChar +******************************************************************************** +* +* This function outputs a character through user defined target. +* Note: this is a template function which may be overwritten by the USER in order +* to change the target used in redirecting STDOUT stream. +* +* \param ch +* The character to send. +* +*******************************************************************************/ +void STDIO_PutChar(uint32_t ch) +{ + /* Place the call to your function here. */ + while(0U == Cy_SCB_UART_Put(IO_STDOUT_UART, ch)) + { + /* Wait until FIFO is full */ + } +} +#endif /* IO_STDOUT_ENABLE && IO_STDOUT_UART */ + +#if defined (IO_STDIN_ENABLE) && defined (IO_STDIN_UART) +/******************************************************************************* +* Function Name: STDIO_GetChar +******************************************************************************** +* +* This function retrieves STDIN from a user specified input source. +* Note: this is a template function which may be overwritten by the USER in order +* to change the target used in redirecting STDIN stream. +* +* \return +* The received character. +* +*******************************************************************************/ +uint32_t STDIO_GetChar(void) +{ + /* Place the call to your function here. */ + while(0UL == Cy_SCB_UART_GetNumInRxFifo(IO_STDIN_UART)) + { + } + return (Cy_SCB_UART_Get(IO_STDIN_UART)); +} +#endif /* IO_STDIN_ENABLE && IO_STDIN_UART */ + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/stdio_user.h b/2020TPCApp1.cydsn/stdio_user.h new file mode 100644 index 0000000..a4c3bc1 --- /dev/null +++ b/2020TPCApp1.cydsn/stdio_user.h @@ -0,0 +1,200 @@ +/***************************************************************************//** +* \file stdio_user.h +* \version 1.20 +* +* \brief +* This file provides configuration macros and function prototypes to retarget +* I/O functions of the standard C run-time library. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef STDIO_USER_H +#define STDIO_USER_H +/** +* \addtogroup group_retarget_io +* \{ +* Retarget the I/O functions of the standard C run-time library to the user-defined target. +* +* Application code frequently uses standard I/O library functions, such as +* scanf()/printf() to perform input/output operations. This utility allows you to retarget +* standard C run-time library I/O functions to the user-defined target. +* +*

Design

+* The file retarget.c defines functions that replace weakly linked I/O functions +* in the standard library (i.e. _write() and _read()). The functions in +* retarget.c in turn call the STDIO_PutChar() and STDIO_GetChar() +* implemented in stdio_user.c. +* +*

Use

+* The files for this utility are in this folder: +* \/utilities/retarget_io +* +* The first thing you need to do is add the source files to your project. +* +* For a 3rd Party IDE, add the retarget_io folder to your list of include +* paths and add the files retarget.c and stdio_user.c to your project. +* +* For PSoC Creator, create a PSoC Creator project. Then click +* Project > Build Setting > Peripheral Driver Library. To +* add Retarget I/O source files to your project, enable it as shown on the +* screenshot below. After selecting Retarget I/O in the PDL software package +* list, click OK and build the project. The Retarget I/O source files are +* added to your project and are available for modification. +* ![Figure 1. Build Settings dialog in PSoC Creator](retarget_io_build_settings.png) +* +* For ModusToolbox, create or open existing ModusToolbox project. Open +* Middleware Selector (Project > ModusToolbox Middleware Selector), +* select Retarget I/O item, and click OK (see the screenshot below). +* The Retarget I/O source files are added to your project and are available for +* modification. +* ![Figure 2. Middleware Selector dialog in ModusToolbox](retarget_io_middleware_selector.png) +* +* There are multiple serial communication blocks (SCB) available. By default +* the Retarget I/O files use SCB0. The stdio_user.h file defines these macros: +* \code #define IO_STDOUT_UART SCB0 +* #define IO_STDIN_UART SCB0 \endcode +* +* Modify these macros to use the SCB in your design. Standard library I/O +* calls are then retargeted to that SCB. +* +* If you use PSoC Creator, the code generator creates a symbol UART_HW +* to represent the SCB block used in your design. In this case you can +* include "project.h" to access that symbol, and modify the macros like this: +* \code #define IO_STDOUT_UART UART_HW +* #define IO_STDIN_UART UART_HW \endcode +* +* The functions implemented in retarget.c are weakly linked. If you wish +* to modify those functions, you can write your own implementation, and +* not use stdio_user.c at all. +* +* \note The standard library is not standard in how it treats an I/O stream. +* Some implement a data buffer by default. The buffer is not flushed until +* it is full. In that case it may appear that your I/O is not working. You +* should be aware of how the library buffers data, and you should identify +* a buffering strategy and buffer size for a specified stream. If you +* supply a buffer, it must exist until the stream is closed. The following +* line of code disables the buffer for the standard library that +* accompanies the GCC compiler: +* \code setvbuf( stdin, NULL, _IONBF, 0 ); \endcode +* +* +*

MISRA-C Compliance

+* The Retarget IO utility has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
5.6ANo identifier in one name space should have the same spelling +* as an identifier in another name space, with the exception of +* structure member and union member names.Violated since the utility redefines the function declared in standard +* library.
6.3Atypedefs that indicate size and signedness should be used in +* place of the basic numerical type.Basic numerical types are used to match the definition of the +* function with the prototype defined in the standard library.
8.8RAn external object or function shall be declared in one and only one file.The _write is declared in the standard i/o library with +* weak attribute and is redefined in the utility.
14.2RAll non-null statements shall either:
(a) have at least one +* side-effect however executed, or
(b) cause control flow to change.		The unused function parameters are cast to void. This statement +* has no side-effect and is used to suppress a compiler warning.
20.9RThe input/output library shall not be used in +* production code.stdio.h file is included to connect the standard function +* definition with their declaration in the standard library.
+* +*

Changelog

+* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.20Changed include path for cy_scb_uart.h to reflect the PDL source code structure
1.10Added STDIN support
1.0Initial version
+* \} +*/ +#include +#include "cy_device_headers.h" + +/* Must remain uncommented to use this utility */ +#define IO_STDOUT_ENABLE +#define IO_STDIN_ENABLE +#define IO_STDOUT_UART UART_Console_HW +#define IO_STDIN_UART UART_Console_HW + +#if defined(IO_STDOUT_ENABLE) || defined(IO_STDIN_ENABLE) +#if defined(IO_STDOUT_UART) || defined(IO_STDIN_UART) +#include "cy_scb_uart.h" +#endif /* IO_STDOUT_UART || IO_STDIN_UART */ +#endif /* IO_STDOUT_ENABLE || IO_STDIN_ENABLE */ + +/* Controls whether CR is added for LF */ +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif /* STDOUT_CR_LF */ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined (IO_STDOUT_ENABLE) && defined (IO_STDOUT_UART) +void STDIO_PutChar(uint32_t ch); +#endif /* IO_STDOUT_ENABLE && IO_STDOUT_UART */ + +#if defined (IO_STDIN_ENABLE) && defined (IO_STDIN_UART) +uint32_t STDIO_GetChar(void); +#endif /* IO_STDIN_ENABLE && IO_STDIN_UART */ + +#if defined(__cplusplus) +} +#endif + +#endif /* STDIO_USER_H */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/system_psoc6.h b/2020TPCApp1.cydsn/system_psoc6.h new file mode 100644 index 0000000..73d1263 --- /dev/null +++ b/2020TPCApp1.cydsn/system_psoc6.h @@ -0,0 +1,648 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.20 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is _IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#define CY_CORTEX_M4_APPL_ADDR ( CY_FLASH_BASE + CY_FLASH_SIZE / 2U) /* <<< Half of flash is reserved for the Cortex-M0+ application */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +#if defined(__ARMCC_VERSION) + extern void SystemInit(void) __attribute__((constructor)); +#else + extern void SystemInit(void); +#endif /* (__ARMCC_VERSION) */ + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/system_psoc6_cm0plus.c b/2020TPCApp1.cydsn/system_psoc6_cm0plus.c new file mode 100644 index 0000000..038e7b4 --- /dev/null +++ b/2020TPCApp1.cydsn/system_psoc6_cm0plus.c @@ -0,0 +1,699 @@ +/***************************************************************************//** +* \file system_psoc6_cm0plus.c +* \version 2.20 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) +#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) + if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) + { + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + IPC_STRUCT7->DATA = 0UL; + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + IPC_STRUCT7->RELEASE = 0UL; + } +#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t slowClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Slow Clock Divider */ + slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + pathFreqHz = pathFreqHz / periClkDiv; + cy_PeriClkFreqHz = pathFreqHz; + pathFreqHz = pathFreqHz / slowClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Returns the Cortex-M4 core power mode. +* +* \return \ref group_system_config_cm4_status_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t regValue; + + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; + + return (regValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; + + CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); + + interruptState = Cy_SysLib_EnterCriticalSection(); + + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) + { + Cy_SysResetCM4(); + } + + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core and waits for the mode to take the effect. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm0 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm0(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/2020TPCApp1.cydsn/system_psoc6_cm4.c b/2020TPCApp1.cydsn/system_psoc6_cm4.c new file mode 100644 index 0000000..c4d8c11 --- /dev/null +++ b/2020TPCApp1.cydsn/system_psoc6_cm4.c @@ -0,0 +1,542 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.20 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} + +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU.cydwr b/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU.cydwr new file mode 100644 index 0000000..ddaa64c --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/2020TPCAppNoDFU.cydwr @@ -0,0 +1,1295 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/Audio.c b/2020TPCAppNoDFU.cydsn/Audio.c new file mode 100644 index 0000000..d8db7ef --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Audio.c @@ -0,0 +1,288 @@ +/* Include Files */ +#include "KTag.h" + +QueueHandle_t xQueueAudio; +TaskHandle_t Audio_Task_Handle; + +static const uint8_t START_BYTE = 0x7E; +static const uint8_t VERSION_BYTE = 0xFF; +static const uint8_t END_BYTE = 0xEF; + +// Valid volumes are 0 - 30. +static const uint8_t COMMAND_SPECIFY_VOLUME = 0x06; +static const uint8_t COMMAND_PAUSE = 0x0E; +static const uint8_t COMMAND_PLAY_TRACK_IN_FOLDER = 0x0F; + +__attribute__((always_inline)) inline uint16_t CalculateChecksum(uint8_t * buffer, uint8_t length) +{ + uint16_t checksum = 0; + + for (uint_fast8_t i = 0; i < length; i++) + { + checksum += buffer[i]; + } + + return (0 - checksum); +} + +static void Send_Command(uint8_t command, bool requireFeedback, uint16_t parameter) +{ + uint8_t buffer[10]; + uint16_t checksum; + + buffer[0] = START_BYTE; + buffer[1] = VERSION_BYTE; + buffer[2] = 6; // count + buffer[3] = command; + buffer[4] = requireFeedback; + buffer[5] = (uint8_t)(parameter >> 8); + buffer[6] = (uint8_t)(parameter); + + checksum = CalculateChecksum(&buffer[1], 6); + + buffer[7] = (uint8_t)(checksum >> 8); + buffer[8] = (uint8_t)(checksum); + buffer[9] = END_BYTE; + + for (uint_fast8_t i = 0; i < 10; i++) + { + UART_Audio_Put(buffer[i]); + } +} + +SystemKResult_T Perform_Audio_Action(AudioAction_T * action) +{ + if (xQueueSend(xQueueAudio, action, 0) == pdTRUE) + { + return SYSTEMK_RESULT_SUCCESS; + } + else + { + return SYSTEMK_RESULT_QUEUE_IS_FULL; + } +} + +void Init_Audio(void) +{ + UART_Audio_Start(); + + xQueueAudio = xQueueCreate(5, sizeof(AudioAction_T)); +} + +void Audio_Task(void * pvParameters) +{ + portBASE_TYPE xStatus; + + while (IsNVMInitialized() == false) + { + vTaskDelay(100 / portTICK_PERIOD_MS); + } + Send_Command(COMMAND_SPECIFY_VOLUME, false, NVM_VOLUME); + + while (true) + { + AudioAction_T action; + + xStatus = xQueueReceive(xQueueAudio, &action, 0); + + if (xStatus == pdPASS) + { + switch (action.ID) + { + case AUDIO_SET_VOLUME: + { + uint8_t volume = *((uint8_t *)action.Data); + if (volume <= 30) + { + Send_Command(COMMAND_SPECIFY_VOLUME, false, volume); + } + } + break; + + case AUDIO_SILENCE: + Send_Command(COMMAND_PAUSE, false, 0x0000); + break; + + case AUDIO_PLAY_STARTUP_SOUND: + // Play track "001" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0101); + break; + + case AUDIO_PLAY_SHOT_FIRED: + // Play track "002" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0102); + break; + + case AUDIO_PLAY_TAG_RECEIVED: + // Play track "003" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0103); + break; + + case AUDIO_PLAY_TAGGED_OUT: + // Play track "004" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0104); + break; + + case AUDIO_PLAY_MISFIRE: + // Play track "005" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0105); + break; + + case AUDIO_PRONOUNCE_NUMBER_0_TO_100: + { + uint8_t file_index = *((uint8_t *)action.Data); + if (file_index > 100) + { + file_index = 100; + } + else if (file_index == 0) + { + file_index = 101; + } + // The numbers are stored in folder "10". + // 001.mp3 is "one", 100.mp3 is "one hundred", and 101.mp3 is "zero". + uint16_t filenumber = 0x0A00 + file_index; + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, filenumber); + } + break; + + case AUDIO_PLAY_MENU_PROMPT: + // Play track "006" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0106); + break; + + case AUDIO_PLAY_SELECTION_INDICATOR: + // Play track "007" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0107); + break; + + case AUDIO_PLAY_HEALTH_REMAINING: + // Play track "008" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0108); + break; + + case AUDIO_PLAY_ELECTRONIC_DANCE_MUSIC: + // Play track "009" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0109); + break; + + default: + case AUDIO_PLAY_GENERIC_ERROR: + // Play track "010" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010A); + break; + + case AUDIO_PLAY_VOLUME_PROMPT: + // Play track "011" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010B); + break; + + case AUDIO_PLAY_RIGHT_HANDED: + // Play track "012" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010C); + break; + + case AUDIO_PLAY_LEFT_HANDED: + // Play track "013" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010D); + break; + + case AUDIO_PLAY_GAME_ON: + // Play track "014" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010E); + break; + + case AUDIO_PLAY_HARDWARE_SETTINGS_PROMPT: + // Play track "015" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x010F); + break; + + case AUDIO_PLAY_GAME_SETTINGS_PROMPT: + // Play track "016" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0110); + break; + + case AUDIO_PLAY_BONK: + // Play track "017" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0111); + break; + + case AUDIO_PLAY_NEAR_MISS: + // Play track "018" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0112); + break; + + case AUDIO_PLAY_PLAYER_ID_PROMPT: + // Play track "019" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0113); + break; + + case AUDIO_PLAY_TEAM_ID_PROMPT: + // Play track "020" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0114); + break; + + case AUDIO_PLAY_FRIENDLY_FIRE: + // Play track "021" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0115); + break; + + case AUDIO_PLAY_STARTING_THEME: + // Play track "022" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0116); + break; + + case AUDIO_PLAY_BOOP: + // Play track "023" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0117); + break; + + case AUDIO_PLAY_BEEP: + // Play track "024" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0118); + break; + + case AUDIO_PLAY_REPROGRAMMING: + // Play track "025" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x0119); + break; + + case AUDIO_PLAY_BOMB: + // Play track "026" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x011A); + break; + + case AUDIO_PLAY_GAME_OVER: + // Play track "027" in folder "01". + Send_Command(COMMAND_PLAY_TRACK_IN_FOLDER, false, 0x011B); + break; + } + + if (action.Play_To_Completion == true) + { + do + { + vTaskDelay(100 / portTICK_PERIOD_MS); + } while (Is_Audio_Playing() == true); + + KEvent_T command_received_event = {.ID = KEVENT_AUDIO_COMPLETED, .Data = (void *)action.ID}; + Post_KEvent(&command_received_event); + } + } + + vTaskDelay(100 / portTICK_PERIOD_MS); + } +} + +bool Is_Audio_Playing() +{ + bool result = false; + + // The signal is active low. + if (Cy_GPIO_Read(Pin_Audio_Busy_PORT, Pin_Audio_Busy_NUM) == 0) + { + result = true; + } + + return result; +} diff --git a/2020TPCAppNoDFU.cydsn/Audio.h b/2020TPCAppNoDFU.cydsn/Audio.h new file mode 100644 index 0000000..d2dda0c --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Audio.h @@ -0,0 +1,7 @@ + +extern QueueHandle_t xQueueAudio; +extern TaskHandle_t Audio_Task_Handle; + +void Init_Audio(void); +void Audio_Task(void * pvParameters); +bool Is_Audio_Playing(); diff --git a/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE.c b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE.c new file mode 100644 index 0000000..0636c1d --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE.c @@ -0,0 +1,1013 @@ +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +#define BLE_TASK_PERIOD_IN_ms 10 + +#ifdef TRACE_BLE + #define TRACE_BLE_STATE_ENTRY(state_name) do {if (State_Changed == true) { COMM_Console_Print_String("[BLE] Entering the ");COMM_Console_Print_String(state_name);COMM_Console_Print_String(" state.\n");}} while (false) +#else // TRACE_BLE + #define TRACE_BLE_STATE_ENTRY(state_name) +#endif // TRACE_BLE + +/* Public Variables */ + +/* Variable used to maintain connection information */ +cy_stc_ble_conn_handle_t appConnHandle[CY_BLE_CONN_COUNT]; + +QueueHandle_t COMM_BLE_CommandQueue; + +TaskHandle_t COMM_BLE_Task_Handle; + +/* Private Variables */ + +static const TickType_t BLE_Task_Delay = BLE_TASK_PERIOD_IN_ms / portTICK_PERIOD_MS; +static COMM_BLE_StateID_T Current_State = COMM_BLE_DEFAULT; +static COMM_BLE_StateID_T Next_State = COMM_BLE_INITIALIZING; +static bool State_Changed = false; +static TickType_t Time_At_State_Entry_In_Ticks; + +//! Immediate Alert Service alert level value. +volatile uint8_t COMM_BLE_IASAlertLevel = 0; + +static cy_stc_ble_gapp_disc_data_t Advertising_Data; +static cy_stc_ble_gapp_scan_rsp_data_t Scan_Response_Data; +static cy_stc_ble_gapp_disc_mode_info_t Advertising_Info = {.advData = &Advertising_Data, .scanRspData = &Scan_Response_Data}; + +/* Private Function Prototypes */ +static void BLE_EventHandler(uint32_t event, void * eventParam); +static void IASEventHandler(uint32 event, void * eventParam); +static cy_en_ble_api_result_t StartNextAdvertisement(); + +/* Inline Functions */ +static inline uint32_t COMM_BLE_GetTimeInState_in_ms() +{ + uint32_t result = (xTaskGetTickCount() - Time_At_State_Entry_In_Ticks) * portTICK_PERIOD_MS; + return result; +} + +/* Public Functions */ + +//! Initializes the Bluetooth Low Energy communications. +void COMM_BLE_Init(void) +{ + COMM_BLE_CommandQueue = xQueueCreate(10, sizeof(COMM_BLE_Command_T)); + + BLE_InitPacketBuffers(); + + COMM_BLE_UART_Init(); + + if (Cy_BLE_Start(BLE_EventHandler) == CY_BLE_SUCCESS) + { + Cy_BLE_IAS_RegisterAttrCallback(IASEventHandler); + } +#ifdef TRACE_BLE + else + { + COMM_Console_Print_String("[BLE] Cy_BLE_Start API Error!\n"); + } +#endif // TRACE_BLE +} + +//! Bluetooth Low Energy communications task: Manages BLE communications, using the PSoC API functions. +/*! + * + */ +void COMM_BLE_Task(void * pvParameters) +{ + COMM_BLE_Command_T command; + + while(true) + { + Cy_BLE_ProcessEvents(); + + if (xQueueReceive(COMM_BLE_CommandQueue, &command, BLE_Task_Delay) == pdPASS) + { + if (Next_State != Current_State) + { + Current_State = Next_State; + Time_At_State_Entry_In_Ticks = xTaskGetTickCount(); + State_Changed = true; + } + else + { + State_Changed = false; + } + + switch (Current_State) + { + default: + case COMM_BLE_DEFAULT: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_DEFAULT"); + COMM_BLE_RequestState(COMM_BLE_INITIALIZING); + } + break; + + case COMM_BLE_INITIALIZING: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_INITIALIZING"); + // Wait for the CY_BLE_EVT_STACK_ON event in BLE_EventHandler() to transition to COMM_BLE_IDLE. + } + break; + + case COMM_BLE_IDLE: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_IDLE"); + + switch (command.ID) + { + case COMM_BLE_SCAN_FOR_KTAG_PACKETS: + COMM_BLE_RequestState(COMM_BLE_SCANNING_FOR_KTAG_PACKETS); + break; + + case COMM_BLE_SCAN_AND_ADVERTISE: + COMM_BLE_RequestState(COMM_BLE_SCANNING_AND_ADVERTISING); + break; + + default: + // All other commands are ignored in this state. + break; + } + } + break; + + case COMM_BLE_SCANNING_FOR_KTAG_PACKETS: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_SCANNING_FOR_KTAG_PACKETS"); + + if (State_Changed == true) + { + // Handle state entry events. + cy_en_ble_api_result_t apiResult = + Cy_BLE_GAPC_StartScan(CY_BLE_SCANNING_FAST, CY_BLE_OBSERVER_CONFIGURATION_0_INDEX); + + if(apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPC_StartScan API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + + switch (command.ID) + { + case COMM_BLE_ADVERTISE_AS_BROADCASTER: + COMM_BLE_RequestState(COMM_BLE_ADVERTISING_AS_BROADCASTER); + break; + + case COMM_BLE_SCAN_AND_ADVERTISE: + COMM_BLE_RequestState(COMM_BLE_SCANNING_AND_ADVERTISING); + break; + + default: + // All other commands are ignored in this state. + break; + } + } + break; + + case COMM_BLE_ADVERTISING_AS_BROADCASTER: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_ADVERTISING_AS_BROADCASTER"); + + if (State_Changed == true) + { + // Handle state entry events. + cy_en_ble_api_result_t apiResult = + Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_BROADCASTER_CONFIGURATION_0_INDEX); + + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + + switch (command.ID) + { + case COMM_BLE_STOP_ADVERTISING: + { + cy_en_ble_api_result_t apiResult = Cy_BLE_GAPP_StopAdvertisement(); + + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StopAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + COMM_BLE_RequestState(COMM_BLE_SCANNING_FOR_KTAG_PACKETS); + } + break; + + case COMM_BLE_SCAN_AND_ADVERTISE: + COMM_BLE_RequestState(COMM_BLE_SCANNING_AND_ADVERTISING); + break; + + default: + // All other commands are ignored in this state. + break; + } + } + break; + + case COMM_BLE_ADVERTISING_AS_PERIPHERAL: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_ADVERTISING_AS_PERIPHERAL"); + + if (State_Changed == true) + { + // Handle state entry events. + cy_en_ble_api_result_t apiResult = + Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX); + + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + } + break; + + case COMM_BLE_SCANNING_AND_ADVERTISING: + { + TRACE_BLE_STATE_ENTRY("COMM_BLE_SCANNING_AND_ADVERTISING"); + + if (State_Changed == true) + { + // Handle state entry events. + cy_en_ble_api_result_t apiResult = + Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_BROADCASTER_CONFIGURATION_0_INDEX); + + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + + apiResult = + Cy_BLE_GAPC_StartScan(CY_BLE_SCANNING_FAST, CY_BLE_OBSERVER_CONFIGURATION_0_INDEX); + + if(apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPC_StartScan API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + } + break; + } + COMM_BLE_UART_MaybeSendData(); + +#ifdef CY_DFU_SDK_VERSION_MAJOR + if (COMM_BLE_IASAlertLevel != 0u) + { + // Disconnect from all the connected devices. + for (uint_fast8_t i = 0; i < CY_BLE_CONN_COUNT; i++) + { + if (Cy_BLE_GetConnectionState(appConnHandle[i]) == CY_BLE_CONN_STATE_CONNECTED) + { + cy_stc_ble_gap_disconnect_info_t disconnectInfoParam = + { + .bdHandle = appConnHandle[i].bdHandle, + .reason = CY_BLE_HCI_ERROR_OTHER_END_TERMINATED_USER + }; + + /* Initiate disconnection from the peer device*/ + if (Cy_BLE_GAP_Disconnect(&disconnectInfoParam) == CY_BLE_SUCCESS) + { + /* Wait for disconnection event */ + while (Cy_BLE_GetConnectionState(appConnHandle[i]) == CY_BLE_CONN_STATE_CONNECTED) + { + /* Process BLE events */ + Cy_BLE_ProcessEvents(); + } + } + } + } + + /* Stop BLE component. */ + Cy_BLE_Disable(); + Cy_DFU_ExecuteApp(0u); + } +#endif // CY_DFU_SDK_VERSION_MAJOR + } + } +} + +SystemKResult_T BLE_GetMyAddress(uint8_t * BD_ADDR) +{ + BD_ADDR[0] = cy_ble_deviceAddress.bdAddr[0]; + BD_ADDR[1] = cy_ble_deviceAddress.bdAddr[1]; + BD_ADDR[2] = cy_ble_deviceAddress.bdAddr[2]; + BD_ADDR[3] = cy_ble_deviceAddress.bdAddr[3]; + BD_ADDR[4] = cy_ble_deviceAddress.bdAddr[4]; + BD_ADDR[5] = cy_ble_deviceAddress.bdAddr[5]; + return SYSTEMK_RESULT_SUCCESS; +} + +SystemKResult_T BLE_ScanAndAdvertise(void) +{ + COMM_BLE_Command_T command = { .ID = COMM_BLE_SCAN_AND_ADVERTISE, .Data = (void *)0x00 }; + xQueueSend(COMM_BLE_CommandQueue, &command, 0); + + return SYSTEMK_RESULT_SUCCESS; +} + +void COMM_BLE_RequestState(COMM_BLE_StateID_T state) +{ + Next_State = state; + COMM_BLE_Command_T command = {.ID = COMM_BLE_REQUEST_STATE_CHANGE, .Data = (void *)0x00}; + xQueueSend(COMM_BLE_CommandQueue, &command, 0); +} + +SystemKResult_T BLE_SetAdvertisingData(BLE_AdvertisingData_T * data) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + if (data->length > BLE_MAX_ADVERTISING_BYTES) + { + result = SYSTEMK_RESULT_TOO_MANY_DATA; + } + else if (data->length < BLE_KTAG_PACKET_TOTAL_SIZE) + { + result = SYSTEMK_RESULT_TOO_FEW_DATA; + } + else + { + Advertising_Data.advDataLen = BLE_KTAG_PACKET_TOTAL_SIZE; + memcpy(Advertising_Data.advData, data, BLE_KTAG_PACKET_TOTAL_SIZE); + + cy_en_ble_api_result_t result = Cy_BLE_GAPP_UpdateAdvScanData(&Advertising_Info); + + if (result != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_UpdateAdvScanData Error: 0x"); + COMM_Console_Print_UInt32AsHex(result); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + + return result; +} + +/* Private Functions */ + +static void BLE_EventHandler(uint32_t event, void * eventParam) +{ + cy_en_ble_api_result_t apiResult; + + static cy_stc_ble_gap_sec_key_info_t keyInfo = + { + .localKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST | + CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST | + CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST, + .exchangeKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST | + CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST | + CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST | + CY_BLE_GAP_SMP_RESP_ENC_KEY_DIST | + CY_BLE_GAP_SMP_RESP_IRK_KEY_DIST | + CY_BLE_GAP_SMP_RESP_CSRK_KEY_DIST, + }; + + if (COMM_BLE_UART_HandleEvent(event, eventParam) == false) + { + // For more information, refer to the comments in cy_ble_stack.h, where all + // these events are described in more detail. + switch (event) + { + case CY_BLE_EVT_INVALID: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_INVALID\n"); +#endif // TRACE_BLE + break; + + + // G E N E R I C E V E N T S (0x1000 to 0x1FFF) + case CY_BLE_EVT_STACK_ON: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_STACK_ON\n"); +#endif // TRACE_BLE + COMM_BLE_RequestState(COMM_BLE_IDLE); + break; + + case CY_BLE_EVT_TIMEOUT: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_TIMEOUT: 0x"); + COMM_Console_Print_UInt8AsHex(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_STACK_BUSY_STATUS: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_STACK_BUSY_STATUS: 0x"); + COMM_Console_Print_UInt8AsHex(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_MEMORY_REQUEST: + case CY_BLE_EVT_PENDING_FLASH_WRITE: + case CY_BLE_EVT_FLASH_CORRUPT: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); + break; +#endif // TRACE_BLE + break; + + + // H O S T C O N T R O L I N T E R F A C E E V E N T S (0x2000 to 0x2FFF) + case CY_BLE_EVT_HARDWARE_ERROR: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_HARDWARE_ERROR: 0x"); + COMM_Console_Print_UInt8AsHex(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_WRITE_AUTH_PAYLOAD_TO_COMPLETE: + case CY_BLE_EVT_READ_AUTH_PAYLOAD_TO_COMPLETE: + case CY_BLE_EVT_GET_CHANNEL_MAP_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_LE_SET_EVENT_MASK_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_SET_DEVICE_ADDR_COMPLETE\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_LE_PING_AUTH_TIMEOUT: + case CY_BLE_EVT_SET_DATA_LENGTH_COMPLETE: + case CY_BLE_EVT_SET_SUGGESTED_DATA_LENGTH_COMPLETE: + case CY_BLE_EVT_GET_DATA_LENGTH_COMPLETE: + case CY_BLE_EVT_DATA_LENGTH_CHANGE: + case CY_BLE_EVT_GET_PEER_RPA_COMPLETE: + case CY_BLE_EVT_GET_LOCAL_RPA_COMPLETE: + case CY_BLE_EVT_SET_RPA_TO_COMPLETE: + case CY_BLE_EVT_SET_RPA_ENABLE_COMPLETE: + case CY_BLE_EVT_SET_HOST_CHANNEL_COMPLETE: + case CY_BLE_EVT_ADD_DEVICE_TO_RPA_LIST_COMPLETE: + case CY_BLE_EVT_REMOVE_DEVICE_FROM_RPA_LIST_COMPLETE: + case CY_BLE_EVT_ADD_DEVICE_TO_WHITE_LIST_COMPLETE: + case CY_BLE_EVT_REMOVE_DEVICE_FROM_WHITE_LIST_COMPLETE: + case CY_BLE_EVT_GET_PHY_COMPLETE: + case CY_BLE_EVT_SET_DEFAULT_PHY_COMPLETE: + case CY_BLE_EVT_SET_PHY_COMPLETE: + case CY_BLE_EVT_PHY_UPDATE_COMPLETE: + case CY_BLE_EVT_SET_PRIVACY_MODE_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + + // V E N D O R E V E N T S (0x3000 to 0x3FFF) + case CY_BLE_EVT_LL_CNTRL_PROC_PENDING_COMPLETE: + case CY_BLE_EVT_SOFT_RESET_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_SET_DEVICE_ADDR_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_SET_DEVICE_ADDR_COMPLETE\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GET_DEVICE_ADDR_COMPLETE: + case CY_BLE_EVT_GET_RSSI_COMPLETE: + case CY_BLE_EVT_GET_TX_PWR_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_SET_TX_PWR_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_SET_TX_PWR_COMPLETE\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GET_CLK_CONFIG_COMPLETE: + case CY_BLE_EVT_SET_CLK_CONFIG_COMPLETE: + case CY_BLE_EVT_RANDOM_NUM_GEN_COMPLETE: + case CY_BLE_EVT_AES_ENCRYPT_COMPLETE: + case CY_BLE_EVT_AES_CCM_ENCRYPT_COMPLETE: + case CY_BLE_EVT_AES_CCM_DECRYPT_COMPLETE: + case CY_BLE_EVT_SET_SLAVE_LATENCY_MODE_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_STACK_SHUTDOWN_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_STACK_SHUTDOWN_COMPLETE\n"); +#endif // TRACE_BLE + // If desired, wait until console transmit is complete, then call Cy_SysPm_Hibernate(); + break; + + case CY_BLE_EVT_RADIO_TEMPERATURE: + case CY_BLE_EVT_RADIO_VOLTAGE_LEVEL: + case CY_BLE_EVT_AES_CMAC_GEN_COMPLETE: + case CY_BLE_EVT_SET_EVENT_MASK_COMPLETE: + case CY_BLE_EVT_SET_CE_LENGTH_COMPLETE: + case CY_BLE_EVT_SET_CONN_PRIORITY_COMPLETE: + case CY_BLE_EVT_HCI_PKT_RCVD: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + + // G E N E R I C A C C E S S P R O F I L E E V E N T S (0x4000 to 0x4FFF) + case CY_BLE_EVT_GAPC_SCAN_PROGRESS_RESULT: + { +#if (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + COMM_Console_Print_String("[BLE] ..SCAN_PROGRESS_RESULT "); +#endif // (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + + BLE_Packet_T * packet = BLE_DecodeKTagPacket((*(cy_stc_ble_gapc_adv_report_param_t *)eventParam).data, + (*(cy_stc_ble_gapc_adv_report_param_t *)eventParam).dataLen, + (*(cy_stc_ble_gapc_adv_report_param_t *)eventParam).peerBdAddr, + (*(cy_stc_ble_gapc_adv_report_param_t *)eventParam).rssi); + + if (packet != NULL) + { +#ifdef TRACE_BLE + switch (packet->Generic.type) + { + case BLE_PACKET_TYPE_INSTIGATE_GAME: + COMM_Console_Print_String(" KTag 'Instigate Game' packet found!"); + break; + + case BLE_PACKET_TYPE_JOIN_NOW: + COMM_Console_Print_String(" KTag 'Join Now' packet found!"); + break; + + case BLE_PACKET_TYPE_TAG: + COMM_Console_Print_String(" KTag 'Tag' packet found!"); + break; + + case BLE_PACKET_TYPE_CONSOLE: + COMM_Console_Print_String(" KTag 'Console' packet found!"); + break; + + case BLE_PACKET_TYPE_STATUS: + COMM_Console_Print_String(" KTag 'Status' packet found!"); + break; + + default: + COMM_Console_Print_String(" Unknown KTag packet found!"); + break; + } + + COMM_Console_Print_String(" RSSI: "); + COMM_Console_Print_Int8(packet->Generic.RSSI); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + if (packet->Generic.type == BLE_PACKET_TYPE_CONSOLE) + { + packet->Console.console_data[BLE_KTAG_PACKET_DATA_SIZE - 1] = COMM_CONSOLE_STRING_TERMINATOR; + COMM_Console_Execute_Internal_Command(packet->Console.console_data); + } + else + { + KEvent_T packet_received_event = {.ID = KEVENT_BLE_PACKET_RECEIVED, .Data = packet}; + Post_KEvent(&packet_received_event); + } + } +#if (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + else + { + COMM_Console_Print_String(" Not a KTag packet!\n"); + } +#endif // (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + } + break; + + case CY_BLE_EVT_GAP_AUTH_REQ: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_AUTH_REQ: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle); + COMM_Console_Print_String(" security=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).security); + COMM_Console_Print_String(" bonding=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding); + COMM_Console_Print_String(" ekeySize=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).ekeySize); + COMM_Console_Print_String(" authErr=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + + if(cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].security == + (CY_BLE_GAP_SEC_MODE_1 | CY_BLE_GAP_SEC_LEVEL_1)) + { + cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].authErr = + CY_BLE_GAP_AUTH_ERROR_PAIRING_NOT_SUPPORTED; + } + + cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].bdHandle = + ((cy_stc_ble_gap_auth_info_t *)eventParam)->bdHandle; + + /* Pass security information for authentication in reply to an authentication request + * from the master device */ + apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]); + if(apiResult != CY_BLE_SUCCESS) + { + Cy_BLE_GAP_RemoveOldestDeviceFromBondedList(); + apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]); + if(apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_AuthReqReply API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + break; + + case CY_BLE_EVT_GAP_PASSKEY_ENTRY_REQUEST: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_PASSKEY_ENTRY_REQUEST:\n"); + COMM_Console_Print_String(" Please enter the passkey displayed on the peer device.\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_PASSKEY_DISPLAY_REQUEST: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_PASSKEY_DISPLAY_REQUEST: "); + COMM_Console_Print_UInt32(*(uint32_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_AUTH_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_AUTH_COMPLETE: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle); + COMM_Console_Print_String(" security=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).security); + COMM_Console_Print_String(" bonding=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding); + COMM_Console_Print_String(" ekeySize=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).ekeySize); + COMM_Console_Print_String(" authErr=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_AUTH_FAILED: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_AUTH_FAILED: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).bdHandle); + COMM_Console_Print_String(" authErr=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAPP_ADVERTISEMENT_START_STOP: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAPP_ADVERTISEMENT_START_STOP: state="); + COMM_Console_Print_UInt8(Cy_BLE_GetAdvertisementState()); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + +#if 0 + if (Cy_BLE_GetAdvertisementState() == CY_BLE_ADV_STATE_STOPPED) + { + apiResult = StartNextAdvertisement(); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } +#endif // 0 + break; + + case CY_BLE_EVT_GAP_DEVICE_CONNECTED: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_DEVICE_CONNECTED: connIntv="); + COMM_Console_Print_UInt16(((cy_stc_ble_gap_connected_param_t *)eventParam)->connIntv * 5u /4u); + COMM_Console_Print_String(" ms\n"); +#endif // TRACE_BLE + + /* Set security keys for new device which is not already bonded */ + if(App_IsDeviceInBondList((*(cy_stc_ble_gap_connected_param_t *)eventParam).bdHandle) == 0u) + { + keyInfo.SecKeyParam.bdHandle = (*(cy_stc_ble_gap_connected_param_t *)eventParam).bdHandle; + apiResult = Cy_BLE_GAP_SetSecurityKeys(&keyInfo); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_SetSecurityKeys API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + } + break; + + case CY_BLE_EVT_GAP_DEVICE_DISCONNECTED: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_DEVICE_DISCONNECTED: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_disconnect_param_t *)eventParam).bdHandle); + COMM_Console_Print_String(" reason=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_disconnect_param_t *)eventParam).reason); + COMM_Console_Print_String(" status=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_gap_disconnect_param_t *)eventParam).status); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + + apiResult = StartNextAdvertisement(); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAPP_StartAdvertisement API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + break; + + case CY_BLE_EVT_GAP_ENCRYPT_CHANGE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_ENCRYPT_CHANGE: 0x"); + COMM_Console_Print_UInt8AsHex(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_CONNECTION_UPDATE_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAPC_SCAN_START_STOP: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAPC_SCAN_START_STOP\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_KEYINFO_EXCHNGE_CMPLT: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_NUMERIC_COMPARISON_REQUEST: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_NUMERIC_COMPARISON_REQUEST:\n"); + COMM_Console_Print_String(" Compare this passkey with the one displayed in your peer device and press 'y' or 'n':\n"); + COMM_Console_Print_String(" "); + COMM_Console_Print_UInt32(*(uint32_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_KEYPRESS_NOTIFICATION: + case CY_BLE_EVT_GAP_OOB_GENERATED_NOTIFICATION: + case CY_BLE_EVT_GAP_ENHANCE_CONN_COMPLETE: + case CY_BLE_EVT_GAPC_DIRECT_ADV_REPORT: + case CY_BLE_EVT_GAP_SMP_NEGOTIATED_AUTH_INFO: + case CY_BLE_EVT_GAP_DEVICE_ADDR_GEN_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAP_KEYS_GEN_COMPLETE: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_KEYS_GEN_COMPLETE\n"); +#endif // TRACE_BLE + keyInfo.SecKeyParam = (*(cy_stc_ble_gap_sec_key_param_t *)eventParam); + Cy_BLE_GAP_SetIdAddress(&cy_ble_deviceAddress); + break; + + case CY_BLE_EVT_GAP_RESOLVE_DEVICE_COMPLETE: + case CY_BLE_EVT_GAP_GEN_SET_LOCAL_P256_KEYS_COMPLETE: + case CY_BLE_EVT_GAP_CREATE_CONN_CANCEL_COMPLETE: + case CY_BLE_EVT_GAP_CONN_ESTB: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GAPP_UPDATE_ADV_SCAN_DATA_COMPLETE: +#if (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAPP_UPDATE_ADV_SCAN_DATA_COMPLETE: "); + COMM_Console_Print_UInt8(*(uint8_t *)eventParam); + COMM_Console_Print_String("\n"); +#endif // (defined TRACE_BLE) && (defined VERBOSE_BLE_TRACE) + break; + + case CY_BLE_EVT_GAP_ADV_TX: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GAP_ADV_TX\n"); +#endif // TRACE_BLE + break; + + // G E N E R I C A T T R I B U T E P R O F I L E E V E N T S (0x5000 to 0x5FFF) + case CY_BLE_EVT_GATTC_ERROR_RSP: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GATTC_ERROR_RSP: opCode=0x"); + COMM_Console_Print_UInt8AsHex(((cy_stc_ble_gatt_err_param_t*)eventParam)->errInfo.opCode); + COMM_Console_Print_String(" errorCode=0x"); + COMM_Console_Print_UInt8AsHex(((cy_stc_ble_gatt_err_param_t*)eventParam)->errInfo.errorCode); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + case CY_BLE_EVT_GATT_CONNECT_IND: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GATT_CONNECT_IND: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_conn_handle_t *)eventParam).bdHandle); + COMM_Console_Print_String(" attId=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_conn_handle_t *)eventParam).attId); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + { + cy_stc_ble_conn_handle_t connHandle = *(cy_stc_ble_conn_handle_t*)eventParam; + appConnHandle[connHandle.attId] = *(cy_stc_ble_conn_handle_t *)eventParam; + } + break; + + case CY_BLE_EVT_GATT_DISCONNECT_IND: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GATT_DISCONNECT_IND: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_conn_handle_t *)eventParam).bdHandle); + COMM_Console_Print_String(" attId=0x"); + COMM_Console_Print_UInt8AsHex((*(cy_stc_ble_conn_handle_t *)eventParam).attId); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + { + cy_stc_ble_conn_handle_t connHandle = *(cy_stc_ble_conn_handle_t*)eventParam; + appConnHandle[connHandle.attId].attId = connHandle.attId; + appConnHandle[connHandle.attId].bdHandle = CY_BLE_INVALID_CONN_HANDLE_VALUE; + } + break; + + case CY_BLE_EVT_GATTS_XCNHG_MTU_REQ: + { + cy_stc_ble_gatt_xchg_mtu_param_t mtu = + { + .connHandle = ((cy_stc_ble_gatt_xchg_mtu_param_t *)eventParam)->connHandle + }; + Cy_BLE_GATT_GetMtuSize(&mtu); +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] CY_BLE_EVT_GATTS_XCNHG_MTU_REQ: bdHandle=0x"); + COMM_Console_Print_UInt8AsHex(mtu.connHandle.bdHandle); + COMM_Console_Print_String(" attId=0x"); + COMM_Console_Print_UInt8AsHex(mtu.connHandle.bdHandle); + COMM_Console_Print_String(" mtu="); + COMM_Console_Print_UInt16(mtu.mtu); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + break; + + case CY_BLE_EVT_GATTC_XCHNG_MTU_RSP: + case CY_BLE_EVT_GATTC_READ_BY_GROUP_TYPE_RSP: + case CY_BLE_EVT_GATTC_READ_BY_TYPE_RSP: + case CY_BLE_EVT_GATTC_FIND_INFO_RSP: + case CY_BLE_EVT_GATTC_FIND_BY_TYPE_VALUE_RSP: + case CY_BLE_EVT_GATTC_READ_RSP: + case CY_BLE_EVT_GATTC_READ_BLOB_RSP: + case CY_BLE_EVT_GATTC_READ_MULTI_RSP: + case CY_BLE_EVT_GATTS_WRITE_REQ: + case CY_BLE_EVT_GATTC_WRITE_RSP: + case CY_BLE_EVT_GATTS_WRITE_CMD_REQ: + case CY_BLE_EVT_GATTS_PREP_WRITE_REQ: + case CY_BLE_EVT_GATTS_EXEC_WRITE_REQ: + case CY_BLE_EVT_GATTC_EXEC_WRITE_RSP: + case CY_BLE_EVT_GATTC_HANDLE_VALUE_NTF: + case CY_BLE_EVT_GATTC_HANDLE_VALUE_IND: + case CY_BLE_EVT_GATTS_HANDLE_VALUE_CNF: + case CY_BLE_EVT_GATTS_DATA_SIGNED_CMD_REQ: + case CY_BLE_EVT_GATTC_STOP_CMD_COMPLETE: + case CY_BLE_EVT_GATTS_READ_CHAR_VAL_ACCESS_REQ: + case CY_BLE_EVT_GATTC_LONG_PROCEDURE_END: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt16AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + + default: +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Unhandled event: "); + COMM_Console_Print_UInt32AsHex(event); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + break; + } + } +} + +/******************************************************************************* +* Function Name: IasEventHandler +******************************************************************************** +* +* Summary: +* This is an event callback function to receive events from the BLE Component, +* which are specific to Immediate Alert Service. +* +* Parameters: +* event: Write Command event from the BLE component. +* eventParams: A structure instance of CY_BLE_GATT_HANDLE_VALUE_PAIR_T type. +* +*******************************************************************************/ +static void IASEventHandler(uint32 event, void * eventParam) +{ + (void) eventParam; + uint8_t alert; + + /* Alert Level Characteristic write event */ + if (event == CY_BLE_EVT_IASS_WRITE_CHAR_CMD) + { + /* Read the updated Alert Level value from the GATT database */ + Cy_BLE_IASS_GetCharacteristicValue(CY_BLE_IAS_ALERT_LEVEL, sizeof(alert), &alert); + COMM_BLE_IASAlertLevel = alert; + } +} + +static cy_en_ble_api_result_t StartNextAdvertisement() +{ + static uint8_t Current_Advertising_Index = CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX; + cy_en_ble_api_result_t apiResult; + + apiResult = Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, Current_Advertising_Index); + + if(apiResult == CY_BLE_SUCCESS) + { + if (Current_Advertising_Index == CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX) + { + Current_Advertising_Index = CY_BLE_BROADCASTER_CONFIGURATION_0_INDEX; + COMM_Console_Print_String("CY_BLE_BROADCASTER_CONFIGURATION_0_INDEX\n"); + } + else + { + Current_Advertising_Index = CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX; + COMM_Console_Print_String("CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX\n"); + } + } + + return apiResult; +} diff --git a/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE.h b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE.h new file mode 100644 index 0000000..83701e6 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE.h @@ -0,0 +1,79 @@ +/** \dir "BLE" + * + * \brief This directory contains source code for managing Bluetooth Low Energy communications. + * + */ + +/** \file + * \brief This file defines the interface to the Bluetooth Low Energy communications used by this software. + * + */ + +#ifndef COMM_BLE_H +#define COMM_BLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +// Define this to print out BLE trace statements to the console. +//#define TRACE_BLE +//#define VERBOSE_BLE_TRACE + +#define COMM_BLE_TASK_STACK_SIZE_in_bytes 4096 + +typedef enum +{ + COMM_BLE_DEFAULT, + COMM_BLE_INITIALIZING, + COMM_BLE_IDLE, + COMM_BLE_SCANNING_FOR_KTAG_PACKETS, + COMM_BLE_ADVERTISING_AS_PERIPHERAL, + COMM_BLE_ADVERTISING_AS_BROADCASTER, + COMM_BLE_SCANNING_AND_ADVERTISING +} COMM_BLE_StateID_T; + +typedef enum +{ + COMM_BLE_COMMAND_NO_OP, + COMM_BLE_REQUEST_STATE_CHANGE, + COMM_BLE_PROCESS_BLE_EVENTS, + COMM_BLE_SCAN_FOR_KTAG_PACKETS, + COMM_BLE_ADVERTISE_AS_BROADCASTER, + COMM_BLE_ADVERTISE_AS_PERIPHERAL, + COMM_BLE_STOP_ADVERTISING, + COMM_BLE_SCAN_AND_ADVERTISE, + // COMM_BLE_COMMAND_IS_OUT_OF_RANGE is one more than the last valid command. + COMM_BLE_COMMAND_IS_OUT_OF_RANGE +} COMM_BLE_Command_ID_T; + +typedef struct +{ + COMM_BLE_Command_ID_T ID; + void * Data; +} COMM_BLE_Command_T; + +/* Include Files */ + +/* Public Variables */ + +extern cy_stc_ble_conn_handle_t appConnHandle[CY_BLE_CONN_COUNT]; +extern volatile uint8_t COMM_BLE_IASAlertLevel; + +extern QueueHandle_t COMM_BLE_CommandQueue; + +//! Handle of the COMM_BLE_Task() given when the task was created. +extern TaskHandle_t COMM_BLE_Task_Handle; + +/* Public Functions */ +void COMM_BLE_Init(void); +void COMM_BLE_Task(void * pvParameters); +void COMM_BLE_RequestState(COMM_BLE_StateID_T state); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_BLE_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_Bond.c b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_Bond.c new file mode 100644 index 0000000..ece43a5 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_Bond.c @@ -0,0 +1,252 @@ +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/* Public Variables */ + +/* Private Variables */ + +static bool removeBondListFlag = false; + +/* Private Function Prototypes */ + +/* Public Functions */ + +/******************************************************************************* +* Function Name: App_DisplayBondList() +******************************************************************************** +* +* Summary: +* This function displays the bond list. +* +*******************************************************************************/ +void App_DisplayBondList(void) +{ +#ifdef TRACE_BLE + cy_en_ble_api_result_t apiResult; + cy_stc_ble_gap_peer_addr_info_t bondedDeviceInfo[CY_BLE_MAX_BONDED_DEVICES]; + cy_stc_ble_gap_bonded_device_list_info_t bondedDeviceList = + { + .bdHandleAddrList = bondedDeviceInfo + }; + uint8_t deviceCount; + + /* Find out whether the device has bonded information stored already or not */ + apiResult = Cy_BLE_GAP_GetBondList(&bondedDeviceList); + if (apiResult != CY_BLE_SUCCESS) + { + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_GetBondList API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); + } + else + { + deviceCount = bondedDeviceList.noOfDevices; + + if(deviceCount != 0u) + { + uint8_t counter; + + COMM_Console_Print_String("[BLE] Bond list:\n"); + + do + { + COMM_Console_Print_String(" "); + COMM_Console_Print_UInt8(deviceCount); + COMM_Console_Print_String(". "); + + deviceCount--; + + if(bondedDeviceList.bdHandleAddrList[deviceCount].bdAddr.type == CY_BLE_GAP_ADDR_TYPE_RANDOM) + { + COMM_Console_Print_String("Peer Random Address:"); + } + else + { + COMM_Console_Print_String("Peer Public Address:"); + } + + for (counter = CY_BLE_GAP_BD_ADDR_SIZE; counter > 0u; counter--) + { + COMM_Console_Print_String(" "); + COMM_Console_Print_UInt8AsHex(bondedDeviceList.bdHandleAddrList[deviceCount].bdAddr.bdAddr[counter - 1u]); + } + COMM_Console_Print_String(", bdHandle: 0x"); + COMM_Console_Print_UInt8AsHex(bondedDeviceList.bdHandleAddrList[deviceCount].bdHandle); + COMM_Console_Print_String("\n"); + } while (deviceCount != 0u); + COMM_Console_Print_String("\n"); + } + } +#endif // TRACE_BLE +} + + +/******************************************************************************* +* Function Name: App_RemoveDevidesFromBondList +******************************************************************************** +* +* Summary: +* Remove devices from the bond list. +* +*******************************************************************************/ +void App_RemoveDevicesFromBondList(void) +{ +#if(CY_BLE_BONDING_REQUIREMENT == CY_BLE_BONDING_YES) + cy_en_ble_api_result_t apiResult; + cy_stc_ble_gap_bd_addr_t peerBdAddr = { .type = 0u }; +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cleaning Bond List...\n\n"); +#endif // TRACE_BLE + + /* Remove all bonded devices in the list */ + apiResult = Cy_BLE_GAP_RemoveBondedDevice(&peerBdAddr); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_RemoveBondedDevice API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + else + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_RemoveBondedDevice complete.\n\n"); +#endif // TRACE_BLE + } +#else +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Bonding is disabled...no need to remove bonded devices.\n\n"); +#endif // TRACE_BLE +#endif /* (CY_BLE_BONDING_REQUIREMENT == CY_BLE_BONDING_YES) */ + + /* Clean flag */ + removeBondListFlag = false; +} + + +/******************************************************************************* +* Function Name: App_GetCountOfBondedDevices() +******************************************************************************** +* +* Summary: +* This function returns the count of bonded devices +* +* Return: +* uint32_t The count of bonded devices +* +*******************************************************************************/ +uint32_t App_GetCountOfBondedDevices(void) +{ + cy_en_ble_api_result_t apiResult; + cy_stc_ble_gap_peer_addr_info_t bondedDeviceInfo[CY_BLE_MAX_BONDED_DEVICES]; + cy_stc_ble_gap_bonded_device_list_info_t bondedDeviceList = + { + .bdHandleAddrList = bondedDeviceInfo + }; + uint32_t deviceCount = 0u; + + /* Find out whether the device has bonded information stored already or not */ + apiResult = Cy_BLE_GAP_GetBondList(&bondedDeviceList); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_GetBondList API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + else + { + deviceCount = bondedDeviceList.noOfDevices; + } + + return (deviceCount); +} + + +/******************************************************************************* +* Function Name: App_IsDeviceInBondList() +******************************************************************************** +* +* Summary: +* This function check if device with bdHandle is in the bond list +* +* Parameters: +* bdHandle - bond device handler +* +* Return: +* bool - true value when bdHandle exists in bond list +* +*******************************************************************************/ +bool App_IsDeviceInBondList(uint32_t bdHandle) +{ + cy_en_ble_api_result_t apiResult; + cy_stc_ble_gap_peer_addr_info_t bondedDeviceInfo[CY_BLE_MAX_BONDED_DEVICES]; + cy_stc_ble_gap_bonded_device_list_info_t bondedDeviceList = + { + .bdHandleAddrList = bondedDeviceInfo + }; + bool deviceIsDetected = false; + uint32_t deviceCount; + + /* Find out whether the device has bonding information stored already or not */ + apiResult = Cy_BLE_GAP_GetBondList(&bondedDeviceList); + if (apiResult != CY_BLE_SUCCESS) + { +#ifdef TRACE_BLE + COMM_Console_Print_String("[BLE] Cy_BLE_GAP_GetBondList API Error: 0x"); + COMM_Console_Print_UInt32AsHex(apiResult); + COMM_Console_Print_String("\n"); +#endif // TRACE_BLE + } + else + { + deviceCount = bondedDeviceList.noOfDevices; + + if(deviceCount != 0u) + { + do + { + deviceCount--; + if(bdHandle == bondedDeviceList.bdHandleAddrList[deviceCount].bdHandle) + { + deviceIsDetected = 1u; + } + } while(deviceCount != 0u); + } + } + return(deviceIsDetected); +} + +/******************************************************************************* +* Function Name: App_SetRemoveBondListFlag() +******************************************************************************** +* Summary: +* Set flag for removing bond list +* +*******************************************************************************/ +void App_SetRemoveBondListFlag(void) +{ + removeBondListFlag = true; +} + +/******************************************************************************* +* Function Name: App_IsRemoveBondListFlag() +******************************************************************************** +* Summary: +* Get value of remove bond list flag +* +* Return: +* true - remove bond list flag is set +* false - remove bond list flag is clear +* +*******************************************************************************/ +bool App_IsRemoveBondListFlag(void) +{ + return ((removeBondListFlag == true) ? true : false); +} + +/* Private Functions */ diff --git a/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_Bond.h b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_Bond.h new file mode 100644 index 0000000..ef5f43b --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_Bond.h @@ -0,0 +1,32 @@ +/** \file + * \brief This file declares Bluetooth Low Energy bond list helper functions. + * + */ + +#ifndef COMM_BLE_BOND_H +#define COMM_BLE_BOND_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +/* Include Files */ + +/* Public Variables */ + +/* Public Functions */ +void App_DisplayBondList(void); +void App_RemoveDevicesFromBondListBySW2Press(uint32_t seconds); +void App_RemoveDevicesFromBondList(void); +void App_SetRemoveBondListFlag(void); +bool App_IsRemoveBondListFlag(void); +bool App_IsDeviceInBondList(uint32_t bdHandle); +uint32_t App_GetCountOfBondedDevices(void); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_BLE_BOND_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_UART.c b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_UART.c new file mode 100644 index 0000000..a50ed0f --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_UART.c @@ -0,0 +1,177 @@ +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +#define UART_CIRCULAR_BUFFER_SIZE 1024 +#define BLE_UART_BUFFER_CHARACTERISTIC_SIZE 20 + +/* Public Variables */ + +/* Private Variables */ + +static uint_fast16_t UART_Tx_Notifications_Enabled = 0; + +static uint8_t UART_Tx_Buffer_Storage[UART_CIRCULAR_BUFFER_SIZE]; +static UTIL_CircularBuffer_T UART_Tx_Buffer; +static uint8_t BLE_UART_Tx_Buffer[BLE_UART_BUFFER_CHARACTERISTIC_SIZE]; +static uint8_t Rx_Buffer[BLE_UART_BUFFER_CHARACTERISTIC_SIZE + 1]; + +/* Private Function Prototypes */ + +/* Public Functions */ + +void COMM_BLE_UART_Init(void) +{ + UTIL_InitCircularBuffer(&UART_Tx_Buffer, UART_Tx_Buffer_Storage, UART_CIRCULAR_BUFFER_SIZE); +} + +//! Sends a message over the BLE UART. +void COMM_BLE_UART_PutString(const char8 * string, uint16_t length) +{ + for (uint8_t i = 0; i < length; i++) + { + (void) UTIL_PushToCircularBuffer(&UART_Tx_Buffer, *string++); + } +} + +//! Sends a single character over the BLE UART. +void COMM_BLE_UART_PutChar(char8 character) +{ + (void) UTIL_PushToCircularBuffer(&UART_Tx_Buffer, character); +} + +void COMM_BLE_UART_MaybeSendData(void) +{ + int8_t length = 0; + + if (UTIL_IsCircularBufferEmpty(&UART_Tx_Buffer) == false) + { + while ((length < BLE_UART_BUFFER_CHARACTERISTIC_SIZE) && (UTIL_IsCircularBufferEmpty(&UART_Tx_Buffer) == false)) + { + uint8_t value; + if (UTIL_PopFromCircularBuffer(&UART_Tx_Buffer, &value) == UTIL_CIRCULARBUFFERRESULT_SUCCESS) + { + BLE_UART_Tx_Buffer[length] = value; + length++; + } + } + } + + if (length > 0) + { + for (uint_fast8_t i = 0; i < CY_BLE_CONN_COUNT; i++) + { + if (Cy_BLE_GetConnectionState(appConnHandle[i]) >= CY_BLE_CONN_STATE_CONNECTED) + { + cy_stc_ble_gatt_handle_value_pair_t tempHandle; + + tempHandle.attrHandle = CY_BLE_NORDIC_UART_SERVICE_TX_CHAR_HANDLE; + tempHandle.value.val = (uint8 *) BLE_UART_Tx_Buffer; + tempHandle.value.actualLen = length; + tempHandle.value.len = length; + + Cy_BLE_GATTS_WriteAttributeValueLocal(&tempHandle); + } + } + + // Send notification to each client that has TX notifications enabled. + for (uint_fast8_t i = 0; i < CY_BLE_CONN_COUNT; i++) + { + if ((Cy_BLE_GetConnectionState(appConnHandle[i]) >= CY_BLE_CONN_STATE_CONNECTED) && + Cy_BLE_GATTS_IsNotificationEnabled(&appConnHandle[i], + CY_BLE_NORDIC_UART_SERVICE_TX_TXCCCD_DESC_HANDLE)) + { + cy_stc_ble_gatt_handle_value_pair_t tempHandle; + + tempHandle.attrHandle = CY_BLE_NORDIC_UART_SERVICE_TX_CHAR_HANDLE; + tempHandle.value.val = (uint8 *) BLE_UART_Tx_Buffer; + tempHandle.value.actualLen = length; + tempHandle.value.len = length; + + Cy_BLE_GATTS_SendNotification(&appConnHandle[i], &tempHandle); + } + } + } +} + +//! BLE event handler for the BLE UART feature. +/*! + * This function should be called *before* events are handled in the event handler passed to + * Cy_BLE_Start(). If it returns `false`, then the rest of the event handler should proceed. + * + * \param event BLE stack event code received from the BLE middleware (one of cy_en_ble_event_t). + * \param eventParam pointer to an event-specific data structure containing the relevant event information. + * \return true if this handler has completely handled the event, and no further + * handling is necessary; false otherwise. + */ +bool COMM_BLE_UART_HandleEvent(uint32 event, void * eventParam) +{ + static cy_stc_ble_gatts_write_cmd_req_param_t * writeReqParameter; + bool handled = false; + + /* Take an action based on the current event */ + switch ((cy_en_ble_event_t)event) + { + // Handle a write request. + case CY_BLE_EVT_GATTS_WRITE_REQ: + + writeReqParameter = (cy_stc_ble_gatts_write_cmd_req_param_t*)eventParam; + + // Request to write the UART. + // https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk5.v15.2.0%2Fble_sdk_app_nus_eval.html&cp=5_5_0_4_1_2_24 + if (writeReqParameter->handleValPair.attrHandle == CY_BLE_NORDIC_UART_SERVICE_RX_CHAR_HANDLE) + { + // Only update the value and write the response if the requested write is allowed. + if (CY_BLE_GATT_ERR_NONE == Cy_BLE_GATTS_WriteAttributeValuePeer(&writeReqParameter->connHandle, &writeReqParameter->handleValPair)) + { + uint16_t i; + + for (i = 0; (i < BLE_UART_BUFFER_CHARACTERISTIC_SIZE) && (i < writeReqParameter->handleValPair.value.len); i++) + { + Rx_Buffer[i] = writeReqParameter->handleValPair.value.val[i]; + } + + // NULL-terminate the buffer. + Rx_Buffer[i] = 0x00; + + Cy_BLE_GATTS_WriteRsp(writeReqParameter->connHandle); + + COMM_Console_Execute_Internal_Command(Rx_Buffer); + } + + handled = true; + } + + // Request for UART Tx notifications. + if (writeReqParameter->handleValPair.attrHandle == CY_BLE_NORDIC_UART_SERVICE_TX_TXCCCD_DESC_HANDLE) + { + if (CY_BLE_GATT_ERR_NONE == Cy_BLE_GATTS_WriteAttributeValuePeer(&writeReqParameter->connHandle, &writeReqParameter->handleValPair)) + { + UART_Tx_Notifications_Enabled = writeReqParameter->handleValPair.value.val[0] & 0x01; + + if (UART_Tx_Notifications_Enabled) + { + COMM_Console_Print_String("[BLE] UART Tx notifications enabled.\n"); + } + else + { + COMM_Console_Print_String("[BLE] UART Tx notifications disabled.\n"); + } + + Cy_BLE_GATTS_WriteRsp(writeReqParameter->connHandle); + } + + handled = true; + } + break; + + default: + // (`handled` is already set to false.) + break; + } + + return handled; +} + +/* Private Functions */ diff --git a/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_UART.h b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_UART.h new file mode 100644 index 0000000..b0f924e --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/BLE/COMM_BLE_UART.h @@ -0,0 +1,30 @@ +/** \file + * \brief This file declares interface functions to a BLE UART implementation. + * + */ + +#ifndef COMM_BLE_UART_H +#define COMM_BLE_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +/* Include Files */ + +/* Public Variables */ + +/* Public Functions */ +void COMM_BLE_UART_Init(void); +void COMM_BLE_UART_PutString(const char8 * string, uint16_t length); +void COMM_BLE_UART_PutChar(char8 character); +void COMM_BLE_UART_MaybeSendData(void); +bool COMM_BLE_UART_HandleEvent(uint32 event, void * eventParam); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_BLE_UART_H \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM.h b/2020TPCAppNoDFU.cydsn/COMM/COMM.h new file mode 100644 index 0000000..269a3bf --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM.h @@ -0,0 +1,50 @@ +/** \dir "COMM" + * + * \brief This directory contains source code for the communication interfaces used by this software. + * + */ + +/** \file + * \brief This file defines the interface to the communications used by this software. + * + * This file should be included by any file outside the COMM package wishing to make use + * of any of the configuration information provided by the COMM package. + * + */ + +#ifndef COMM_H +#define COMM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ +#include "COMM_IPC_Messages.h" +#include "BLE/COMM_BLE.h" +#include "BLE/COMM_BLE_Bond.h" +#include "BLE/COMM_BLE_UART.h" +#include "COMM_Console.h" +#include "COMM_Console_Util.h" +#include "COMM_I2C_Bus.h" +#include "COMM_Util.h" +#include "ConsoleCommands/COMM_ConsoleCommands.h" +#include "ConsoleCommands/COMM_BLE_ConsoleCommands.h" +#include "ConsoleCommands/COMM_NVM_ConsoleCommands.h" +#include "ConsoleCommands/COMM_RTOS_ConsoleCommands.h" +#include "ConsoleCommands/COMM_STATE_ConsoleCommands.h" + +/* Preprocessor and Type Definitions */ + +#define DebugPrintf(...) +#define Task_DebugPrintf(...) + +/* Public Variables */ + +/* Public Functions */ + +#ifdef __cplusplus +} +#endif + +#endif // COMM_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_Console.c b/2020TPCAppNoDFU.cydsn/COMM/COMM_Console.c new file mode 100644 index 0000000..1d612b3 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_Console.c @@ -0,0 +1,639 @@ +/** \file + * \brief This file implements a simple serial debug console and command interpreter. + */ + +/** \defgroup CONSOLE Console + * + * \brief Serial debug console command interpreter. + * + * \todo Describe the command interpreter. + * + * @{ + * @} + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +//! Text representations of numeric digits, used by COMM_Console_Print_UInt32(). +static const char8 DIGITS[] = "0123456789ABCDEF"; + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +//! Maximum number of characters (save one) able to be printed by COMM_Console_Print_String(). +#define MAX_CONSOLE_STRING_LENGTH 81 + +//! States in the COMM_Console_Task() state machine. +typedef enum +{ + COMM_STATE_INITIALIZING = 0, + COMM_STATE_DISPLAY_POWERUP_INFO, + COMM_STATE_IDLE, + COMM_STATE_COMMAND_TOO_LONG, + COMM_STATE_IDENTIFY_COMMAND, + COMM_STATE_EXECUTE_COMMAND, + COMM_STATE_UNKNOWN_COMMAND +} COMM_Console_State_T; + +/* Public Variables */ +char8 Command_Buffer[COMM_CONSOLE_COMMAND_MAX_LENGTH]; +uint_fast16_t Command_Buffer_Index = 0; +TaskHandle_t COMM_Console_Task_Handle; + +/* Private Variables */ + +//! Current state of the COMM_Console_Task() state machine. +static COMM_Console_State_T Current_State = COMM_STATE_INITIALIZING; + +//! Next state of the COMM_Console_Task() state machine. +static COMM_Console_State_T Next_State = COMM_STATE_INITIALIZING; + +//! Index into the #COMM_Console_Command_Table for the command currently being handled. +/*! + * If #Current_Command is set to UINT_FAST16_MAX, the command being handled is unknown, or no command is being handled. + */ +static uint_fast16_t Current_Command = 0; + +/* Private Function Prototypes */ + +static void ConsoleISR(void); +static bool ConsoleCommandMatches(const char8 * const command_name); +static void ReverseString(char8 * value, uint32_t length); + +/* Inline Functions */ + +//! Swaps the characters in x and y. +static inline void Swap_Char8(char8 * x, char8 * y) +{ + uint8_t temp = *x; + *x = *y; + *y = temp; + } + +static inline void Reset_Command_Buffer() +{ + taskENTER_CRITICAL(); + for (uint_fast16_t i = 0; i < COMM_CONSOLE_COMMAND_MAX_LENGTH; i++) + { + Command_Buffer[i] = COMM_CONSOLE_STRING_TERMINATOR; + } + Command_Buffer_Index = 0; + taskEXIT_CRITICAL(); +} + +/* Public Functions */ + +//! Initializes the console. +/*! + * \ingroup CONSOLE + */ +void COMM_Console_Init(void) +{ + // Enable the pullup on the Rx pin to keep the noise down. + Cy_GPIO_SetDrivemode(UART_Console_rx_PORT, UART_Console_rx_NUM, CY_GPIO_DM_PULLUP); + UART_Console_Start(); + + /// Unmask only the RX FIFO not empty interrupt bit. + UART_Console_HW->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk; + Cy_SysInt_Init(&Int_UART_Console_cfg, ConsoleISR); + NVIC_ClearPendingIRQ(Int_UART_Console_cfg.intrSrc); + NVIC_EnableIRQ(Int_UART_Console_cfg.intrSrc); +} + +//! Parses and handle console commands in the background. +/*! + * \ingroup CONSOLE + * + * The [UML State Machine Diagram](http://www.uml-diagrams.org/state-machine-diagrams.html) below + * shows how the console messages processed by this code. Note that all of the *Character Rx'd* + * transitions occur in the #UART_Console_SPI_UART_ISR_EntryCallback() itself on the PSoC4, in + * #ConsoleRxISR() on the PSoC5, and in #ConsoleISR() on the PSoC6, to improve overall performance. + * + * \startuml{COMM_Console_Task.png} "Console Task" + * + * skinparam headerFontSize 18 + * skinparam state { + * BackgroundColor #eeeeee + * BackgroundColor<> #ffaaaa + * FontName Impact + * FontSize 18 + * } + * skinparam note { + * FontName "Comic Sans MS" + * FontStyle italic + * } + * + * state "Initializing" as STATE_INITIALIZING + * [*] --> STATE_INITIALIZING + * note left of STATE_INITIALIZING : Wait for the rest of the system to come online. + * state "Display Powerup Info" as STATE_DISPLAY_POWERUP_INFO + * STATE_DISPLAY_POWERUP_INFO : do/ print OS version + * STATE_DISPLAY_POWERUP_INFO : do/ print configuration (debug or release) + * STATE_INITIALIZING --> STATE_DISPLAY_POWERUP_INFO : after(100ms) + * state "Idle" as STATE_IDLE + * STATE_IDLE : do/ RTOS_Sleep() + * STATE_DISPLAY_POWERUP_INFO --> STATE_IDLE + * state STATE_IS_EOM <> + * note top of STATE_IS_EOM : This happens in\nUART_Console_SPI_UART_ISR_ExitCallback() on PSoC4,\nConsoleRxISR() on PSoC5,\nand ConsoleISR() on PSoC6. + * STATE_IDLE --> STATE_IS_EOM : character rx'd + * state STATE_IS_COMMAND_BUFFER_FULL <> + * note top of STATE_IS_COMMAND_BUFFER_FULL : This happens in\nUART_Console_SPI_UART_ISR_ExitCallback() on PSoC4,\nConsoleRxISR() on PSoC5,\nand ConsoleISR() on PSoC6. + * STATE_IS_EOM --> STATE_IS_COMMAND_BUFFER_FULL : [else] + * state "Identify Command" as STATE_IDENTIFY_COMMAND + * STATE_IDENTIFY_COMMAND : do/ look for command in the COMM_Console_Command_Table[] + * STATE_IS_EOM --> STATE_IDENTIFY_COMMAND : [rx'd character is EOM] + * STATE_IDLE --> STATE_IDENTIFY_COMMAND : COMM_Console_Execute_Internal_Command() + * state "Command Too Long" as STATE_COMMAND_TOO_LONG + * STATE_COMMAND_TOO_LONG : do/ print error message + * STATE_COMMAND_TOO_LONG : do/ reset command buffer + * STATE_IS_COMMAND_BUFFER_FULL --> STATE_COMMAND_TOO_LONG : [command buffer is full] + * STATE_IS_COMMAND_BUFFER_FULL --> STATE_IDLE : [else]/\nAppend received character to command buffer + * STATE_COMMAND_TOO_LONG --> STATE_IDLE + * state "Execute Command" as STATE_EXECUTE_COMMAND + * STATE_EXECUTE_COMMAND : do/ execute console command + * STATE_EXECUTE_COMMAND : exit/ reset command buffer + * STATE_EXECUTE_COMMAND --> STATE_IDLE + * STATE_IDENTIFY_COMMAND --> STATE_EXECUTE_COMMAND : [command matched] + * state "Unknown Command" as STATE_UNKNOWN_COMMAND + * STATE_UNKNOWN_COMMAND : do/ print error message + * STATE_UNKNOWN_COMMAND : do/ reset command buffer + * STATE_IDENTIFY_COMMAND --> STATE_UNKNOWN_COMMAND : [else] + * STATE_UNKNOWN_COMMAND --> STATE_IDLE + * + * left footer Key: UML 2.5\nLast modified 2020-12-14 + * \enduml + * + * \return None (infinite loop) + */ +void COMM_Console_Task(void * pvParameters) +{ + static TickType_t xTicksToWait = pdMS_TO_TICKS(10); + static uint32_t * NotificationValue; + + while(true) + { + (void) xTaskNotifyWait(0, 0, (uint32_t *)&NotificationValue, xTicksToWait); + + // Change to the next state atomically. + taskENTER_CRITICAL(); + Current_State = Next_State; + taskEXIT_CRITICAL(); + + switch (Current_State) + { + default: + case COMM_STATE_INITIALIZING: + Next_State = COMM_STATE_DISPLAY_POWERUP_INFO; + vTaskDelay(pdMS_TO_TICKS(10)); + xTicksToWait = 1; + break; + + case COMM_STATE_DISPLAY_POWERUP_INFO: + COMM_Console_Print_String("[COMM] "); + COMM_RTOS_HandleConsoleVersion(NULL, 0); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("[COMM] Console ready (awaiting commands).\n"); + Next_State = COMM_STATE_IDLE; + xTicksToWait = 1; + break; + + case COMM_STATE_IDLE: + xTicksToWait = pdMS_TO_TICKS(100); + break; + + case COMM_STATE_COMMAND_TOO_LONG: + COMM_Console_Print_String("[COMM] ERROR: Command \""); + COMM_Console_Print_String(Command_Buffer); + COMM_Console_Print_String("\" too long!\n"); + Reset_Command_Buffer(); + Next_State = COMM_STATE_IDLE; + xTicksToWait = 1; + break; + + case COMM_STATE_IDENTIFY_COMMAND: + Current_Command = UINT_FAST16_MAX; + + for (uint_fast16_t i = 0; i < COMM_N_CONSOLE_COMMANDS; i++) + { + if (ConsoleCommandMatches(COMM_Console_Command_Table[i].Command_Name) == true) + { + Current_Command = i; + Next_State = COMM_STATE_EXECUTE_COMMAND; + xTicksToWait = 1; + break; + } + } + + if (Current_Command == UINT_FAST16_MAX) + { + // No matching command was found. + Next_State = COMM_STATE_UNKNOWN_COMMAND; + xTicksToWait = 1; + } + break; + + case COMM_STATE_EXECUTE_COMMAND: + if (COMM_Console_Command_Table[Current_Command].Execute_Command != NULL) + { + COMM_Console_Command_Result_T result = COMM_Console_Command_Table[Current_Command].Execute_Command(Command_Buffer, Command_Buffer_Index); + + if (result == COMM_CONSOLE_CMD_RESULT_PARAMETER_ERROR) + { + COMM_Console_Print_String("ERROR: Parameter error!\n"); + } + } + Reset_Command_Buffer(); + Next_State = COMM_STATE_IDLE; + xTicksToWait = 1; + break; + + case COMM_STATE_UNKNOWN_COMMAND: + COMM_Console_Print_String("ERROR: Command \""); + COMM_Console_Print_String(Command_Buffer); + COMM_Console_Print_String("\" not recognized! Try '?' for help.\n"); + Reset_Command_Buffer(); + Next_State = COMM_STATE_IDLE; + xTicksToWait = 1; + break; + } + } +} + +SystemKResult_T HW_Execute_Console_Command(const uint8_t * const command) +{ + COMM_Console_Execute_Internal_Command(command); + + return SYSTEMK_RESULT_SUCCESS; +} + +//! Executes a (potentially cross-task) console command. +/*! + * This function is used to initiate a console command from a software source internal to this + * CPU. This provides a way to use preexisting console commands on TX-only consoles. + * + * \note If two calls to this function are made back-to-back (before the COMM_Console_Task() has an + * opportunity to run), only the second command will be executed, as it will have overwritten the + * first. Allow time for the console commands to execute between calls to this function. + * + * \param command String containing the command to be executed. + */ +void COMM_Console_Execute_Internal_Command(const uint8_t * const command) +{ + bool finished = false; + uint_fast16_t i = 0; + + taskENTER_CRITICAL(); + while ( (finished == false) && + (i < COMM_CONSOLE_COMMAND_MAX_LENGTH) && + (command[i] != COMM_CONSOLE_END_OF_MESSAGE ) && + (command[i] != COMM_CONSOLE_STRING_TERMINATOR ) + ) + { + Command_Buffer[i] = command[i]; + i++; + } + Command_Buffer_Index = i; + + // If there is still room, terminate the command. + if (i < COMM_CONSOLE_COMMAND_MAX_LENGTH) + { + Command_Buffer[i] = COMM_CONSOLE_END_OF_MESSAGE; + } + taskEXIT_CRITICAL(); + + Next_State = COMM_STATE_IDENTIFY_COMMAND; + xTaskNotifyGive(COMM_Console_Task_Handle); +} + +//! Prints a NULL-terminated string to the serial console. +void COMM_Console_Print_String(const char8 * const text) +{ + for (size_t i = 0; i < MAX_CONSOLE_STRING_LENGTH; i++) + { + // Check for the end of the string. If there is no NULL terminator, up to + // MAX_CONSOLE_STRING_LENGTH characters of randomness will be printed. + if (text[i] == COMM_CONSOLE_STRING_TERMINATOR) + { + break; + } + + // Send out the string, one character at a time. + COMM_Console_PutChar(text[i]); + } +} + +//! Prints a 32-bit unsigned integer to the serial console. +void COMM_Console_Print_UInt32(uint32_t value) +{ + // The largest string for a unit32_t is 10 characters (4294967296). + char8 buffer[10+1]; + uint_fast8_t buffer_index = 0; + + while (value > 9) + { + uint8_t digit_index = value % 10; + buffer[buffer_index] = DIGITS[digit_index]; + value = value / 10; + buffer_index++; + } + buffer[buffer_index] = DIGITS[value]; + buffer_index++; + ReverseString(buffer, buffer_index); + + // NULL-terminate the string. + buffer[buffer_index] = 0; + + COMM_Console_Print_String(buffer); +} + +//! Prints a 32-bit signed integer to the serial console. +void COMM_Console_Print_SInt32(int32_t value) +{ + if (value < 0) + { + value *= -1; + COMM_Console_PutChar('-'); + } + + COMM_Console_Print_UInt32(value); +} + +//! Prints a 32-bit unsigned integer to the serial console using a hexadecimal representation. +void COMM_Console_Print_UInt32AsHex(uint32_t value) +{ + // The largest hexadecimal string for a unit32_t is 8 characters (FFFFFFFF). + char8 buffer[8+1]; + uint_fast8_t buffer_index = 0; + + while (value > 15) + { + uint8_t digit_index = value % 16; + buffer[buffer_index] = DIGITS[digit_index]; + value = value / 16; + buffer_index++; + } + buffer[buffer_index] = DIGITS[value]; + buffer_index++; + ReverseString(buffer, buffer_index); + + // NULL-terminate the string. + buffer[buffer_index] = 0; + + COMM_Console_PutChar('0'); + COMM_Console_PutChar('x'); + COMM_Console_Print_String(buffer); +} + +//! Prints a 64-bit unsigned integer to the serial console. +void COMM_Console_Print_UInt64(uint64_t value) +{ + // The largest string for a unit64_t is 20 characters (18446744073709551615). + char8 buffer[20+1]; + uint_fast8_t buffer_index = 0; + + while (value > 9) + { + uint8_t digit_index = value % 10; + buffer[buffer_index] = DIGITS[digit_index]; + value = value / 10; + buffer_index++; + } + buffer[buffer_index] = DIGITS[value]; + buffer_index++; + ReverseString(buffer, buffer_index); + + // NULL-terminate the string. + buffer[buffer_index] = 0; + + COMM_Console_Print_String(buffer); +} + +//! Prints a 64-bit unsigned integer to the serial console using a hexadecimal representation. +void COMM_Console_Print_UInt64AsHex(uint64_t value) +{ + // The largest hexadecimal string for a unit64_t is 16 characters (FFFFFFFFFFFFFFFF). + char8 buffer[16+1]; + uint_fast8_t buffer_index = 0; + + while (value > 15) + { + uint8_t digit_index = value % 16; + buffer[buffer_index] = DIGITS[digit_index]; + value = value / 16; + buffer_index++; + } + buffer[buffer_index] = DIGITS[value]; + buffer_index++; + ReverseString(buffer, buffer_index); + + // NULL-terminate the string. + buffer[buffer_index] = 0; + + COMM_Console_PutChar('0'); + COMM_Console_PutChar('x'); + COMM_Console_Print_String(buffer); +} + +//! Prints a floating-point number to the serial console. +/*! + * With thanks to Rick Regan and his [Quick and Dirty Floating-Point to Decimal Conversion](https://www.exploringbinary.com/quick-and-dirty-floating-point-to-decimal-conversion/). + */ +void COMM_Console_Print_Float(float value) +{ + #define MAX_INTEGRAL_DIGITS 12 + #define MAX_FRACTIONAL_DIGITS 6 + #define BUFFER_SIZE (MAX_INTEGRAL_DIGITS + MAX_FRACTIONAL_DIGITS + 2) + + char8 buffer[BUFFER_SIZE]; + char8 integral_buffer_reversed[MAX_INTEGRAL_DIGITS]; + uint16_t buffer_index = 0; + double integral_value; + double fractional_value; + bool overflow = false; + + if (value < 0.0) + { + COMM_Console_Print_String("-"); + value *= -1.0; + } + + // Break the given value into fractional and integral parts. + fractional_value = modf(value, &integral_value); + + if (integral_value > 0) + { + // Convert the integral part. + while ((integral_value > 0) && (buffer_index < MAX_INTEGRAL_DIGITS)) + { + integral_buffer_reversed[buffer_index++] = '0' + (int)fmod(integral_value, 10); + integral_value = floor(integral_value / 10); + } + + // If there is still an integral part remaining, and overflow has occurred. + if (integral_value > 0) + { + overflow = true; + } + + // Reverse and append the integral part. + for (uint16_t i = 0; i < buffer_index; i++) + { + buffer[i] = integral_buffer_reversed[buffer_index-i-1]; + } + } + else + { + // Append a leading zero. + buffer[buffer_index++] = '0'; + } + + // Append the decimal point. + buffer[buffer_index++] = '.'; + + // Convert the fractional part, even if it is zero, and leave room for the NULL terminator. + while (buffer_index < (BUFFER_SIZE - 1)) + { + fractional_value *= 10; + buffer[buffer_index++] = '0' + (int)fractional_value; + fractional_value = modf(fractional_value, &integral_value); + } + + // Append the NULL terminator. + buffer[buffer_index] = 0; + + if (overflow == true) + { + COMM_Console_Print_String("OVERFLOW"); + } + else + { + COMM_Console_Print_String(buffer); + } +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +//! Converts a byte to a two-character hexadecimal representation. +/*! + * \param buffer Buffer into which to place the resulting sting. It needs to be at least three + * characters wide. + * \param byte The byte to be converted. + */ +void COMM_Console_ByteToHex(char8 * buffer, uint8_t byte) +{ + if (byte < 16) + { + buffer[0] = '0'; + buffer[1] = DIGITS[byte]; + buffer[2] = 0; + } + else + { + buffer[0] = DIGITS[byte / 16]; + buffer[1] = DIGITS[byte % 16]; + buffer[2] = 0; + } +} + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Private Functions */ + +static void ConsoleISR(void) +{ + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + // Check for the "Rx FIFO not empty" interrput. + if ((UART_Console_HW->INTR_RX_MASKED & SCB_INTR_RX_MASKED_NOT_EMPTY_Msk ) != 0) + { + // Clear the "Rx FIFO not empty" interrput. + UART_Console_HW->INTR_RX = UART_Console_HW->INTR_RX & SCB_INTR_RX_NOT_EMPTY_Msk; + + // Get the character. + uint32_t value = UART_Console_Get(); + + // Check if there is actually data. Sometimes the flag is set when there is no data (why?). + if (value != CY_SCB_UART_RX_NO_DATA) + { + char8 rx_data = (char8) value; + + // Determine what to do with it. + if (Command_Buffer_Index < COMM_CONSOLE_COMMAND_MAX_LENGTH) + { + if (rx_data == COMM_CONSOLE_END_OF_MESSAGE) + { + Command_Buffer[Command_Buffer_Index] = COMM_CONSOLE_STRING_TERMINATOR; + Next_State = COMM_STATE_IDENTIFY_COMMAND; + vTaskNotifyGiveFromISR(COMM_Console_Task_Handle, &xHigherPriorityTaskWoken); + } + else + { + Command_Buffer[Command_Buffer_Index] = rx_data; + Command_Buffer_Index++; + } + } + else + { + Next_State = COMM_STATE_COMMAND_TOO_LONG; + vTaskNotifyGiveFromISR(COMM_Console_Task_Handle, &xHigherPriorityTaskWoken); + } + } + } + + NVIC_ClearPendingIRQ(Int_UART_Console_cfg.intrSrc); + + // If the state needs to change, a context switch might be required. + portEND_SWITCHING_ISR(xHigherPriorityTaskWoken); +} + +static bool ConsoleCommandMatches(const char8 * const command_name) +{ + uint32_t i = 0; + bool is_match = false; + + if (Command_Buffer[i] == command_name[i]) + { + is_match = true; + i++; + } + + while ( (is_match == true) && + (i < COMM_CONSOLE_COMMAND_MAX_LENGTH) && + (Command_Buffer[i] != COMM_CONSOLE_PARAMETER_DELIMITER) && + (Command_Buffer[i] != COMM_CONSOLE_END_OF_MESSAGE ) && + (Command_Buffer[i] != COMM_CONSOLE_STRING_TERMINATOR ) + ) + { + if ( Command_Buffer[i] != command_name[i] ) + { + is_match = false; + } + i++; + } + + return is_match; +} + +//! Reverses a string in place. +/*! + * \param value Pointer to the string to be reversed. + * \param length Length of the string, including the NULL terminator. + */ +static void ReverseString(char8 * value, uint32_t length) +{ + if (length > 1) + { + uint_fast32_t start = 0; + uint_fast32_t end = length - 1; + while (start < end) + { + Swap_Char8(value + start, value + end); + start++; + end--; + } + } +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_Console.h b/2020TPCAppNoDFU.cydsn/COMM/COMM_Console.h new file mode 100644 index 0000000..916cb6c --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_Console.h @@ -0,0 +1,144 @@ +/** \file + * \brief This file defines the interface to a simple serial debug console and command interpreter. + * + * \note As always, and should be included before this file. + */ + +#ifndef COMM_CONSOLE_H +#define COMM_CONSOLE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +#define COMM_CONSOLE_TASK_STACK_SIZE_in_bytes 512 + +#define COMM_Console_PutChar UART_and_BLE_PutChar +#define COMM_Console_PutString UART_and_BLE_PutString + +#define COMM_CONSOLE_COMMAND_MAX_LENGTH 50 + +//! Character signifying the end of a console message. +#define COMM_CONSOLE_END_OF_MESSAGE ('\n') + +//! Character used between parameters in a console message. +#define COMM_CONSOLE_PARAMETER_DELIMITER (' ') + +//! Character signifying the end of a string. +#define COMM_CONSOLE_STRING_TERMINATOR ('\0') + +//! Result of executing a console command callback. +typedef enum +{ + COMM_CONSOLE_CMD_RESULT_UNKNOWN = 0, + COMM_CONSOLE_CMD_RESULT_SUCCESS = 1, + COMM_CONSOLE_CMD_RESULT_PARAMETER_ERROR = 2 +} COMM_Console_Command_Result_T; + +//! Result of parsing a console command parameter. +typedef enum +{ + COMM_CONSOLE_PARAMETER_RESULT_UNKNOWN = 0, + COMM_CONSOLE_PARAMETER_RESULT_SUCCESS = 1, + COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR = 2, + COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END = 3 +} COMM_Console_Parameter_Result_T; + +//! Prototype of a console command callback. +/*! + * \ingroup CONSOLE + * All console commands must use this signature. + * + * \param[in] data Pointer to the string containg the console command (and any arguments). + * \param[in] size Size (in char8) of the data string. + * \return #COMM_CONSOLE_CMD_RESULT_SUCCESS on success + * \return #COMM_Console_Command_Result_T otherwise + */ +typedef COMM_Console_Command_Result_T (* const COMM_Console_Command_Handler_T)(char8 * data, uint32_t size); + +typedef struct +{ + const char8 * const Command_Name; + const char8 * const Help; + COMM_Console_Command_Handler_T Execute_Command; +} COMM_Console_Command_Table_Entry_T; + +/* Public Variables */ + +//! Handle of the COMM_Console_Task() given when the task was created. +extern TaskHandle_t COMM_Console_Task_Handle; + +/* Public Functions */ + +void COMM_Console_Init(void); +void COMM_Console_Task(void * pvParameters); +void COMM_Console_Execute_Internal_Command(const uint8_t * const command); +void COMM_Console_Print_String(const char8 * const text); +void COMM_Console_Print_UInt32(uint32_t value); +void COMM_Console_Print_SInt32(int32_t value); +void COMM_Console_Print_UInt32AsHex(uint32_t value); +void COMM_Console_Print_UInt64(uint64_t value); +void COMM_Console_Print_UInt64AsHex(uint64_t value); +void COMM_Console_Print_Float(float value); + +void COMM_Console_ByteToHex(char8 * buffer, uint8_t byte); + +/* Inline Functions */ + +//! Prints an 8-bit unsigned integer to the serial console. +inline void COMM_Console_Print_UInt8(uint8_t value) +{ + COMM_Console_Print_UInt32((uint32_t) value); +} + +//! Prints an 8-bit unsigned integer to the serial console using a hexadecimal representation. +inline void COMM_Console_Print_UInt8AsHex(uint8_t value) +{ + COMM_Console_Print_UInt32AsHex((uint32_t) value); +} + +//! Prints an 8-bit signed integer to the serial console. +inline void COMM_Console_Print_Int8(int8_t value) +{ + COMM_Console_Print_SInt32((int32_t) value); +} + +//! Prints a 16-bit unsigned integer to the serial console. +inline void COMM_Console_Print_UInt16(uint16_t value) +{ + COMM_Console_Print_UInt32((uint32_t) value); +} + +//! Prints a 16-bit unsigned integer to the serial console using a hexadecimal representation. +inline void COMM_Console_Print_UInt16AsHex(uint16_t value) +{ + COMM_Console_Print_UInt32AsHex((uint32_t) value); +} + +//! Prints a 16-bit signed integer to the serial console. +inline void COMM_Console_Print_Int16(int16_t value) +{ + COMM_Console_Print_SInt32((int32_t) value); +} + +static inline void UART_and_BLE_PutChar(uint8 txDataByte) +{ + UART_Console_Put(txDataByte); + COMM_BLE_UART_PutChar(txDataByte); +} + +static inline void UART_and_BLE_PutString(const char8 string[]) +{ + UART_Console_PutString(string); + COMM_BLE_UART_PutString(string, strlen(string)); +} + +#ifdef __cplusplus +} +#endif + +#endif // COMM_CONSOLE_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_Console_Util.c b/2020TPCAppNoDFU.cydsn/COMM/COMM_Console_Util.c new file mode 100644 index 0000000..0a68b17 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_Console_Util.c @@ -0,0 +1,254 @@ +/** \file + * \brief This file implements utility functions used by the command interpreter. + */ + +/** + * \ingroup CONSOLE + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Public Variables */ + +/* Private Variables */ + +/* Private Function Prototypes */ + +/* Public Functions */ + +//! Find the start location of the nth parameter in the buffer. +/*! + * \note The command itself is parameter 0. + */ +COMM_Console_Parameter_Result_T COMM_Console_FindNthParameter(const char * const buffer, const uint8_t parameterNumber, const char ** parameterLocation) +{ + uint32_t buffer_index = 0; + uint32_t parameter_index = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + + while (parameterNumber != parameter_index) + { + if (buffer[buffer_index] == COMM_CONSOLE_PARAMETER_DELIMITER) + { + parameter_index++; + } + else if (buffer[buffer_index] == COMM_CONSOLE_END_OF_MESSAGE) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + else if (buffer[buffer_index] == COMM_CONSOLE_STRING_TERMINATOR) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + buffer_index++; + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + *parameterLocation = &buffer[buffer_index]; + } + + return result; +} + + +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt8(const char * const buffer, uint8_t * const parameterUInt8) +{ + uint8_t value = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + + // Strings containing uint8s range from "0" to "255". The large number has three characters. + uint_fast16_t MAX_CHARACTERS = 3; + uint_fast16_t index = 0; + + while (index < (MAX_CHARACTERS + 1)) + { + if ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + value *= 10; + value += buffer[index] - '0'; + index++; + } + else if ( (buffer[index] == COMM_CONSOLE_PARAMETER_DELIMITER) || + (buffer[index] == COMM_CONSOLE_STRING_TERMINATOR) || + (buffer[index] == COMM_CONSOLE_END_OF_MESSAGE) ) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END; + break; + } + else + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END) + { + result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + *parameterUInt8 = value; + } + + return result; +} + + +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt16(const char * const buffer, uint16_t * const parameterUInt16) +{ + uint16_t value = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + + // Strings containing uint16s range from "0" to "65535". The large number has five characters. + uint_fast16_t MAX_CHARACTERS = 5; + uint_fast16_t index = 0; + + while (index < (MAX_CHARACTERS + 1)) + { + if ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + value *= 10; + value += buffer[index] - '0'; + index++; + } + else if ( (buffer[index] == COMM_CONSOLE_PARAMETER_DELIMITER) || + (buffer[index] == COMM_CONSOLE_STRING_TERMINATOR) || + (buffer[index] == COMM_CONSOLE_END_OF_MESSAGE) ) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END; + break; + } + else + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END) + { + result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + *parameterUInt16 = value; + } + + return result; +} + +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterInt32(const char * const buffer, int32_t * const parameterInt32) +{ + int32_t value = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + bool is_negative = false; + + // Strings containing int32s range from "-2147483648" to "2147483647". The negative number has eleven characters. + uint_fast16_t MAX_CHARACTERS = 11; + uint_fast16_t index = 0; + + if (buffer[index] == '-') + { + is_negative = true; + index++; + } + + while (index < (MAX_CHARACTERS + 1)) + { + if ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + value *= 10; + value += buffer[index] - '0'; + index++; + } + else if ( (buffer[index] == COMM_CONSOLE_PARAMETER_DELIMITER) || + (buffer[index] == COMM_CONSOLE_STRING_TERMINATOR) || + (buffer[index] == COMM_CONSOLE_END_OF_MESSAGE) ) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END; + break; + } + else + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + } + + if (is_negative == true) + { + value *= -1; + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END) + { + result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + *parameterInt32 = value; + } + + return result; +} + +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt32(const char * const buffer, uint32_t * const parameterUInt32) +{ + uint32_t value = 0; + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + + // Strings containing uint32s range from "0" to "4294967296". The large number has ten characters. + uint_fast16_t MAX_CHARACTERS = 10; + uint_fast16_t index = 0; + + while (index < (MAX_CHARACTERS + 1)) + { + if ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + value *= 10; + value += buffer[index] - '0'; + index++; + } + else if ( (buffer[index] == COMM_CONSOLE_PARAMETER_DELIMITER) || + (buffer[index] == COMM_CONSOLE_STRING_TERMINATOR) || + (buffer[index] == COMM_CONSOLE_END_OF_MESSAGE) ) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END; + break; + } + else + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + break; + } + } + + if (result == COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_END) + { + result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + *parameterUInt32 = value; + } + + return result; +} + +COMM_Console_Parameter_Result_T COMM_Console_DecodeHexParameterUInt64(const char * const buffer, uint64_t * const parameterUInt64) +{ + COMM_Console_Parameter_Result_T result = COMM_CONSOLE_PARAMETER_RESULT_SUCCESS; + struct _reent context; + + context._errno = 0; + + *parameterUInt64 = _strtoull_r(&context, buffer, NULL, 16); + + if (context._errno != 0) + { + result = COMM_CONSOLE_PARAMETER_RESULT_PARAMETER_ERROR; + } + + return result; +} + +/* Private Functions */ + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_Console_Util.h b/2020TPCAppNoDFU.cydsn/COMM/COMM_Console_Util.h new file mode 100644 index 0000000..7fccbaf --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_Console_Util.h @@ -0,0 +1,50 @@ +/** \file + * \brief Utility functions used by the command interpreter. + * + * \note As always, and should be included before this file. + */ + +#ifndef COMM_CONSOLE_UTIL_H +#define COMM_CONSOLE_UTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Parameter_Result_T COMM_Console_FindNthParameter(const char * const buffer, const uint8_t parameterNumber, const char ** parameterLocation); +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt8(const char * const buffer, uint8_t * const parameterUInt8); +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt16(const char * const buffer, uint16_t * const parameterUInt16); +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterInt32(const char * const buffer, int32_t * const parameterInt32); +COMM_Console_Parameter_Result_T COMM_Console_DecodeParameterUInt32(const char * const buffer, uint32_t * const parameterUInt32); +COMM_Console_Parameter_Result_T COMM_Console_DecodeHexParameterUInt64(const char * const buffer, uint64_t * const parameterUInt64); + +//! Returns `true` if this character marks the end of a console message; `false` otherwise. +inline bool COMM_Console_IsEndOfMessage(char8 character) +{ + bool result = false; + + if ( (character == COMM_CONSOLE_END_OF_MESSAGE) || + (character == COMM_CONSOLE_STRING_TERMINATOR) ) + { + result = true; + } + + return result; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_CONSOLE_UTIL_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_I2C_Bus.c b/2020TPCAppNoDFU.cydsn/COMM/COMM_I2C_Bus.c new file mode 100644 index 0000000..7fe82f6 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_I2C_Bus.c @@ -0,0 +1,33 @@ +/** \file + * \brief This file implements the I²C bus. + * + * See COMM_I2C_Bus.h for a detailed description of the functionality implemented by this code. + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/* Public Variables */ + +SemaphoreHandle_t COMM_I2C_Bus_Mutex = NULL; + +/* Private Variables */ + +/* Private Function Prototypes */ + +/* Public Functions */ + +//! Initializes the I²C bus. +/*! + * + */ +void COMM_I2C_Init(void) +{ + COMM_I2C_Bus_Mutex = xSemaphoreCreateMutex(); + I2C_Start(); +} + + +/* Private Functions */ diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_I2C_Bus.h b/2020TPCAppNoDFU.cydsn/COMM/COMM_I2C_Bus.h new file mode 100644 index 0000000..414e7f2 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_I2C_Bus.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file defines the interface to the I²C bus. + * + */ + +#ifndef COMM_I2C_BUS_H +#define COMM_I2C_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + + +/* Include Files */ + + +/* Public Variables */ +extern SemaphoreHandle_t COMM_I2C_Bus_Mutex; + +/* Public Functions */ +void COMM_I2C_Init(void); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_I2C_BUS_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_IPC_Messages.c b/2020TPCAppNoDFU.cydsn/COMM/COMM_IPC_Messages.c new file mode 100644 index 0000000..605d8df --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_IPC_Messages.c @@ -0,0 +1,285 @@ +/** \file + * \brief This file implements messaging using inter-processor communication (IPC). + * +* \see https://community.cypress.com/thread/36182. + */ + +/** + * \ingroup CONSOLE + */ + +/* Include Files */ +#include +#include +#include +#include +#include +#include + +#include "COMM_IPC_Messages.h" + +/* Private Function Prototypes */ + +#if (__CORTEX_M == 0) +static void Message_Received_for_CM0(uint32_t * msg); +static void Message_Received_by_CM4(void); +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) +static void Message_Received_for_CM4(uint32_t * msg); +static void Message_Received_by_CM0(void); +#endif // (__CORTEX_M == 4) + +static void IPC_UserPipeInit(void); +static void IPC_UserPipeISR(void); + + +/* Local Definitions and Constants */ + +//! Number of clients supported on the user pipe. +#define CY_IPC_USRPIPE_CLIENT_CNT (uint32_t)(8u) + +#define CY_IPC_CHAN_USRPIPE_CM0 (uint32_t)(8u) +#define CY_IPC_CHAN_USRPIPE_CM4 (uint32_t)(9u) + +#define CY_IPC_INTR_USRPIPE_CM0 (uint32_t)(8u) +#define CY_IPC_INTR_USRPIPE_CM4 (uint32_t)(9u) + +#define CY_IPC_EP_USRPIPE_ADDR_CM0_EP (uint32_t)(2u) +#define CY_IPC_EP_USRPIPE_ADDR_CM4_EP (uint32_t)(3u) + +#if (CY_CPU_CORTEX_M0P) + #define IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_ADDR_CM0_EP +#else + #define IPC_EP_USRPIPE_ADDR CY_IPC_EP_USRPIPE_ADDR_CM4_EP +#endif /* (CY_CPU_CORTEX_M0P) */ + +/* User Pipe Configuration */ + +#define IPC_USRPIPE_CHAN_MASK_CM0 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM0) +#define IPC_USRPIPE_CHAN_MASK_CM4 (uint32_t)(0x0001ul << CY_IPC_CHAN_USRPIPE_CM4) +#define IPC_USRPIPE_INTR_MASK (uint32_t)( IPC_USRPIPE_CHAN_MASK_CM0 | IPC_USRPIPE_CHAN_MASK_CM4 ) +#define IPC_INTR_USRPIPE_PRIOR_CM0 (uint32_t)(1u) /* Notifier Priority */ +#define IPC_INTR_USRPIPE_PRIOR_CM4 (uint32_t)(1u) /* Notifier Priority */ +#define IPC_INTR_USRPIPE_MUX_CM0 (uint32_t)(7u) /* IPC CYPRESS PIPE */ +#define IPC_USRPIPE_CONFIG_CM0 (uint32_t)(IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos)\ + |(CY_IPC_INTR_USRPIPE_CM0 << CY_IPC_PIPE_CFG_INTR_Pos )\ + |(CY_IPC_CHAN_USRPIPE_CM0) +#define IPC_USRPIPE_CONFIG_CM4 (uint32_t)(IPC_USRPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos)\ + |(CY_IPC_INTR_USRPIPE_CM4 << CY_IPC_PIPE_CFG_INTR_Pos )\ + |(CY_IPC_CHAN_USRPIPE_CM4) + +#define USRPIPE_CONFIG \ +{\ + /* .ep0ConfigData */ {\ + /* .ipcNotifierNumber */ CY_IPC_INTR_USRPIPE_CM0,\ + /* .ipcNotifierPriority */ IPC_INTR_USRPIPE_PRIOR_CM0,\ + /* .ipcNotifierMuxNumber */ IPC_INTR_USRPIPE_MUX_CM0,\ + /* .epAddress */ CY_IPC_EP_USRPIPE_ADDR_CM0_EP,\ + /* .epConfig */ IPC_USRPIPE_CONFIG_CM0\ + },\ + /* .ep1ConfigData */ {\ + /* .ipcNotifierNumber */ CY_IPC_INTR_USRPIPE_CM4,\ + /* .ipcNotifierPriority */ IPC_INTR_USRPIPE_PRIOR_CM4,\ + /* .ipcNotifierMuxNumber */ 0u,\ + /* .epAddress */ CY_IPC_EP_USRPIPE_ADDR_CM4_EP,\ + /* .epConfig */ IPC_USRPIPE_CONFIG_CM4\ + },\ + /* .endpointClientsCount */ CY_IPC_USRPIPE_CLIENT_CNT,\ + /* .endpointsCallbacksArray */ ipc_pipe_CbArray,\ + /* .userPipeIsrHandler */ &IPC_UserPipeISR\ +} + +//! Client ID for messages from the CM0 to the CM4 +#define COMM_IPC_CM0_TO_CM4_CLIENT_ID 0 +//! Client ID for messages from the CM4 to the CM0 +#define COMM_IPC_CM4_TO_CM0_CLIENT_ID 1 + + +/* Public Variables */ + +/* Private Variables */ + +#if (__CORTEX_M == 0) +static COMM_IPCMessage_T MessageBuffer = +{ + .ClientID = _VAL2FLD(CY_IPC_PIPE_MSG_CLIENT, COMM_IPC_CM0_TO_CM4_CLIENT_ID) | _VAL2FLD(CY_IPC_PIPE_MSG_USR, 0) | _VAL2FLD(CY_IPC_PIPE_MSG_RELEASE, IPC_USRPIPE_INTR_MASK), + .MessageID = COMM_SMM_DefaultNoMessage, + .Data = NULL +}; + +static volatile bool OK_to_send_from_CM0_to_CM4 = true; +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) +static COMM_IPCMessage_T MessageBuffer = +{ + .ClientID = _VAL2FLD(CY_IPC_PIPE_MSG_CLIENT, COMM_IPC_CM4_TO_CM0_CLIENT_ID) | _VAL2FLD(CY_IPC_PIPE_MSG_USR, 0) | _VAL2FLD(CY_IPC_PIPE_MSG_RELEASE, IPC_USRPIPE_INTR_MASK), + .MessageID = COMM_SMM_DefaultNoMessage, + .Data = NULL +}; + +static volatile bool OK_to_send_from_CM4_to_CM0 = true; +#endif // (__CORTEX_M == 4) + + +/* Public Functions */ + +#if (__CORTEX_M == 0) +//! Initializes the inter-processor communications on the Cortex-M0 core. +/*! + * This should be called *before* calling Cy_SysEnableCM4(). + */ +void COMM_InitIPCMessages(void) +{ + IPC_UserPipeInit(); + + // Register a callback to handle messages from CM4. + Cy_IPC_Pipe_RegisterCallback(IPC_EP_USRPIPE_ADDR, + Message_Received_for_CM0, + CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) +//! Initializes the inter-processor communications on the Cortex-M4 core. +void COMM_InitIPCMessages(void) +{ + IPC_UserPipeInit(); + + // Register a callback to handle messages from CM0. + Cy_IPC_Pipe_RegisterCallback(IPC_EP_USRPIPE_ADDR, + Message_Received_for_CM4, + CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif // (__CORTEX_M == 4) + + +//! Sends an inter-processor communication message to the other core. +bool COMM_SendMessageToOtherCore(COMM_IPCMessageID_T message_ID, void * message_data) +{ + bool message_sent = false; + + MessageBuffer.MessageID = message_ID; + MessageBuffer.Data = message_data; + +#if (__CORTEX_M == 0) + if (OK_to_send_from_CM0_to_CM4 == true) + { + OK_to_send_from_CM0_to_CM4 = false; + uint32_t timeout_in_us = 2000; + cy_en_ipc_pipe_status_t ipcStatus; + + do + { + ipcStatus = Cy_IPC_Pipe_SendMessage(CY_IPC_EP_USRPIPE_ADDR_CM4_EP, + CY_IPC_EP_USRPIPE_ADDR_CM0_EP, + (uint32_t *) &MessageBuffer, + Message_Received_by_CM4); + Cy_SysLib_DelayUs(1u); + timeout_in_us--; + } while((ipcStatus != CY_IPC_PIPE_SUCCESS) && (timeout_in_us != 0)); + + message_sent = true; + } +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) + if (OK_to_send_from_CM4_to_CM0 == true) + { + OK_to_send_from_CM4_to_CM0 = false; + uint32_t timeout_in_us = 2000; + cy_en_ipc_pipe_status_t ipcStatus; + + do + { + ipcStatus = Cy_IPC_Pipe_SendMessage(CY_IPC_EP_USRPIPE_ADDR_CM0_EP, + CY_IPC_EP_USRPIPE_ADDR_CM4_EP, + (uint32_t *) &MessageBuffer, + Message_Received_by_CM0); + Cy_SysLib_DelayUs(1u); + timeout_in_us--; + } while((ipcStatus != CY_IPC_PIPE_SUCCESS) && (timeout_in_us != 0)); + + message_sent = true; + } +#endif // (__CORTEX_M == 4) + + return message_sent; +} + + +/* Private Functions */ + +#if (__CORTEX_M == 0) +//! Callback for messages received by the CM0 core from the CM4 core. +/*! + * \note This code is executed inside an interrupt handler. + */ +static void Message_Received_for_CM0(uint32_t * msg) +{ + switch (((COMM_IPCMessage_T *)msg)->MessageID) + { + default: + case COMM_SMM_DefaultNoMessage: + case COMM_SMM_NoMessage: + break; + + case COMM_SMM_RebootImmediately: + // Perform a software reset of both cores. + NVIC_SystemReset(); + break; + } +} + +static void Message_Received_by_CM4(void) +{ + OK_to_send_from_CM0_to_CM4 = true; +} +#endif // (__CORTEX_M == 0) + +#if (__CORTEX_M == 4) +//! Callback for messages received by the CM4 core from the CM0 core. +/*! + * \note This code is executed inside an interrupt handler. + */ +static void Message_Received_for_CM4(uint32_t * msg) +{ + switch (((COMM_IPCMessage_T *)msg)->MessageID) + { + default: + case COMM_SMM_DefaultNoMessage: + case COMM_SMM_NoMessage: + break; + + case COMM_SMM_RebootImmediately: + // This message does nothing on CM4 + break; + } +} + +static void Message_Received_by_CM0(void) +{ + OK_to_send_from_CM4_to_CM0 = true; +} +#endif // (__CORTEX_M == 4) + +//! Initializes the IPC user pipe. +static void IPC_UserPipeInit(void) +{ + static cy_ipc_pipe_callback_ptr_t ipc_pipe_CbArray[CY_IPC_USRPIPE_CLIENT_CNT]; + static const cy_stc_ipc_pipe_config_t userPipeConfig = USRPIPE_CONFIG; + + uint32_t savedIntrStatus = Cy_SysLib_EnterCriticalSection(); + + Cy_IPC_Pipe_Init(&userPipeConfig); + + Cy_SysLib_ExitCriticalSection(savedIntrStatus); +} + +//! Interrupt service routine for the user pipe. +void IPC_UserPipeISR(void) +{ + Cy_IPC_Pipe_ExecuteCallback(IPC_EP_USRPIPE_ADDR); +} + diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_IPC_Messages.h b/2020TPCAppNoDFU.cydsn/COMM/COMM_IPC_Messages.h new file mode 100644 index 0000000..c6efdc3 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_IPC_Messages.h @@ -0,0 +1,49 @@ + +/** \file + * \brief This file contains definitions and prototypes for messaging using inter-processor + * communication (IPC). + */ + +#ifndef COMM_IPC_MESSAGES_H +#define COMM_IPC_MESSAGES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +typedef enum +{ + //! This is not an actual message. Upon receipt, do nothing. + COMM_SMM_DefaultNoMessage = 0, + //! Reboot the system immediately upon receipt of this message (Data is "don't care"). + COMM_SMM_RebootImmediately, + //! This is not an actual message. Upon receipt, do nothing. + COMM_SMM_NoMessage = 0xFFFFFFFF, +} COMM_IPCMessageID_T; + +typedef struct +{ + //! The client ID number is the index into the callback array. + uint32_t ClientID; + //! The message ID represents the meaning of the message being sent. + COMM_IPCMessageID_T MessageID; + //! The contents of Data are different for each message ID. See #COMM_IPCMessageID_T for more details. + void * Data; +} COMM_IPCMessage_T; + +/* Public Variables */ + +/* Public Functions */ + +void COMM_InitIPCMessages(void); +bool COMM_SendMessageToOtherCore(COMM_IPCMessageID_T message_ID, void * message_data); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_IPC_MESSAGES_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_Util.c b/2020TPCAppNoDFU.cydsn/COMM/COMM_Util.c new file mode 100644 index 0000000..311d8a5 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_Util.c @@ -0,0 +1,48 @@ +/** \file + * \brief This file implements utility functions used by the communications package. + */ + +/** + * \ingroup CONSOLE + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/* Public Variables */ + +/* Private Variables */ +static char8 uint64_buffer[20+1]; + +/* Private Function Prototypes */ + +/* Public Functions */ + +//! Converts a UInt64 to a NULL-terminated string. +/*! + * This function is necessary because newlib-nano does not support "%llu" / #PRIu64. + * \see https://answers.launchpad.net/gcc-arm-embedded/+question/257014 + * + * \note This function is not reentrant! + * + * \param value pointer to the digital input object. + * \return pointer to a NULL-terminated string containing the base-10 textual representation of #value. + */ +char8 * COMM_UInt64ToDecimal(uint64_t value) +{ + char8 * p = uint64_buffer + sizeof(uint64_buffer); + *(--p) = 0x00; + + for (bool first_time = true; value || first_time; first_time = false) + { + const uint32_t digit = value % 10; + const char c = '0' + digit; + *(--p) = c; + value = value / 10; + } + return p; +} + +/* Private Functions */ diff --git a/2020TPCAppNoDFU.cydsn/COMM/COMM_Util.h b/2020TPCAppNoDFU.cydsn/COMM/COMM_Util.h new file mode 100644 index 0000000..0dc199a --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/COMM_Util.h @@ -0,0 +1,27 @@ +/** \file + * \brief Utility functions used by the communications package. + * + * \note As always, and should be included before this file. + */ + +#ifndef COMM_UTIL_H +#define COMM_UTIL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +char8 * COMM_UInt64ToDecimal(uint64_t value); + +#ifdef __cplusplus +} +#endif + +#endif // COMM_UTIL_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.c b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.c new file mode 100644 index 0000000..183e994 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.c @@ -0,0 +1,78 @@ +/** \file + * \brief This file defines the serial console commands for the Bluetooth Low Energy subsystem. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) && (CONFIG__FEATURE_BLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ + +/* Public Variables */ + +/* Private Variables */ + +/* Public Functions */ + +/* Private Functions */ + +//! Console command handler for subcommands of the 'ble' command. +COMM_Console_Command_Result_T COMM_HandleBLECommand(char8 * data, uint32_t size) +{ + // data[0] through data[3] is 'ble '. + + if (data[4] == '?') + { + COMM_Console_Print_String("ble ? Display this help.\n"); + COMM_Console_Print_String("ble cmd Inject the BLE command with ID .\n"); + } + else if ( (data[4] == 'c') && + (data[5] == 'm') && + (data[6] == 'd') ) + + { + if (COMM_Console_IsEndOfMessage(data[7])) + { + COMM_Console_Print_String("ERROR: missing BLE command ID!\n"); + } + else if (data[7] == ' ') + { + uint16_t id = 0; + + if (COMM_Console_DecodeParameterUInt16(&(data[8]), &id) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + if ((id > COMM_BLE_COMMAND_NO_OP) && (id < COMM_BLE_COMMAND_IS_OUT_OF_RANGE)) + { + COMM_BLE_Command_T command = {.ID = id, .Data = (void *)0x00}; + xQueueSend(COMM_BLE_CommandQueue, &command, 0); + } + else + { + COMM_Console_Print_String("ERROR: specified BLE command ID ("); + COMM_Console_Print_UInt16(id); + COMM_Console_Print_String(") is invalid!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: could not comprehend BLE command ID!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: unrecognized or mangled command!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: Unknown BLE command!\n"); + } + + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) && (CONFIG__FEATURE_BLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.h b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.h new file mode 100644 index 0000000..014c11e --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_BLE_ConsoleCommands.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file declares the serial console commands for the Bluetooth Low Energy subsystem. + */ + +#ifndef COMM_BLE_CONSOLECOMMANDS_H +#define COMM_BLE_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Command_Result_T COMM_HandleBLECommand(char8 * data, uint32_t size); + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_BLE_CONSOLECOMMANDS_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.c b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.c new file mode 100644 index 0000000..95802c5 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.c @@ -0,0 +1,72 @@ +/** \file + * \brief This file defines the serial console commands for this CPU. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ +static COMM_Console_Command_Result_T HandleConsoleHelp(char8 * data, uint32_t size); +static COMM_Console_Command_Result_T HandleConsoleComment(char8 * data, uint32_t size); +static COMM_Console_Command_Result_T HandleConsoleUptime(char8 * data, uint32_t size); + +/* Public Variables */ + +const COMM_Console_Command_Table_Entry_T COMM_Console_Command_Table[] = +{ + {"?", " Show this help.", HandleConsoleHelp}, + {"#", " Comment (Do not omit the space after the #.)", HandleConsoleComment}, + {"event", " Generate an event in the high-level state machine (\'event ?\' for help).", COMM_HandleEventCommand}, + {"ble", " Interact with the Bluetooth Low Energy subsystem (try \'ble ?\').", COMM_HandleBLECommand}, + {"up", " Display uptime.", HandleConsoleUptime}, + {"cpu (r)", " Display CPU usage ('r' to reset maximum).", COMM_RTOS_HandleConsoleCPU}, + {"stack", " Display stack usage.", COMM_RTOS_HandleConsoleStack}, + {"version", " Display RTOS version.", COMM_RTOS_HandleConsoleVersion}, + {"reboot", " Performs a software reset on both cores.", COMM_RTOS_HandleConsoleReboot}, + {"nvm", " Interact with the Nonvolatile Memory (try \'nvm ?\').", COMM_NVM_HandleConsoleNVMCommand}, +}; + +//! Size of the #COMM_Console_Command_Table array (i.e. the number of console commands). +const uint_fast16_t COMM_N_CONSOLE_COMMANDS = (uint_fast16_t) (sizeof(COMM_Console_Command_Table) / sizeof(COMM_Console_Command_Table_Entry_T)); + +/* Private Variables */ + +/* Public Functions */ + +/* Private Functions */ + +static COMM_Console_Command_Result_T HandleConsoleHelp(char8 * data, uint32_t size) +{ + for (uint_fast16_t i = 0; i < COMM_N_CONSOLE_COMMANDS; i++) + { + COMM_Console_Print_String(COMM_Console_Command_Table[i].Command_Name); + COMM_Console_Print_String(" "); + COMM_Console_Print_String(COMM_Console_Command_Table[i].Help); + COMM_Console_Print_String("\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + } + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +static COMM_Console_Command_Result_T HandleConsoleComment(char8 * data, uint32_t size) +{ + COMM_Console_Print_String("Comment.\n"); + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +static COMM_Console_Command_Result_T HandleConsoleUptime(char8 * data, uint32_t size) +{ +#if (configTICK_RATE_HZ != 1000) +#error This code assumes configTICK_RATE_HZ is set to 1000 (== 1ms ticks)! +#endif // (configTICK_RATE_HZ != 1000) + COMM_Console_Print_String("Up "); + COMM_Console_Print_UInt32(xTaskGetTickCount()); + COMM_Console_Print_String(" milliseconds.\n"); + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.h b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.h new file mode 100644 index 0000000..c332d4d --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_ConsoleCommands.h @@ -0,0 +1,30 @@ +/** \file + * \brief This file configures the serial console commands on this CPU. + */ + +#ifndef COMM_CONSOLECOMMANDS_H +#define COMM_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ +extern const COMM_Console_Command_Table_Entry_T COMM_Console_Command_Table[]; +extern const uint_fast16_t COMM_N_CONSOLE_COMMANDS; + +/* Public Functions */ + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_CONSOLECOMMANDS_H \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.c b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.c new file mode 100644 index 0000000..ced911a --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.c @@ -0,0 +1,207 @@ +/** \file + * \brief This file defines the serial console commands for the Nonvolatile Memory. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ + +/* Public Variables */ + +/* Private Variables */ + +/* Public Functions */ + +/* Private Functions */ + +//! Console command handler for subcommands of the 'nvm' command. +COMM_Console_Command_Result_T COMM_NVM_HandleConsoleNVMCommand(char8 * data, uint32_t size) +{ + // data[0] through data[3] is 'nvm '. + if (data[4] == '?') + { + COMM_Console_Print_String("nvm ? Display this help.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("nvm dump Display the entire Nonvolatile Memory.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("nvm names Display the NVM parameter names.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("nvm get Display an individual parameter from NVM.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("nvm set Assign a value to an individual parameter in NVM (be careful!).\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + } + else if ((data[4] == 'd') && (data[5] == 'u') && (data[6] == 'm') && (data[7] == 'p')) + { + for (uint8_t i = 0; i < NVM_N_ONCHIP_EEPROM_ENTRIES; i++) + { + COMM_Console_Print_String("NVM["); + COMM_Console_Print_UInt16(i); + COMM_Console_Print_String("]: "); + + for (uint8_t j = 0; j < NVM_OnChipEEPROMEntries[i]->Size; j++) + { + char8 buffer[3]; + + COMM_Console_ByteToHex(buffer, *(NVM_OnChipEEPROMEntries[i]->Value + j)); + COMM_Console_Print_String("0x"); + COMM_Console_Print_String(buffer); + COMM_Console_Print_String(" "); + } + COMM_Console_Print_String("\n"); + } + } + else if ((data[4] == 'n') && (data[5] == 'a') && (data[6] == 'm') && (data[7] == 'e') && (data[8] == 's')) + { + COMM_Console_Print_String("Valid NVM parameters:\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String(" test_1\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String(" test_2\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String(" volume\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + } + else if ((data[4] == 'g') && (data[5] == 'e') && (data[6] == 't') && (data[7] == ' ')) + { + if (strncmp(&data[8], "volume", 6) == 0) + { + COMM_Console_Print_String("Volume: "); + COMM_Console_Print_UInt8(NVM_VOLUME); + COMM_Console_Print_String("\n"); + } + else if (strncmp(&data[8], "test_1", 6) == 0) + { + COMM_Console_Print_String("Test 1: "); + COMM_Console_Print_UInt16(NVM_ONCHIP_TEST_1); + COMM_Console_Print_String("\n"); + } + else if (strncmp(&data[8], "test_2", 6) == 0) + { + COMM_Console_Print_String("Test 2: "); + COMM_Console_Print_UInt32(NVM_ONCHIP_TEST_2); + COMM_Console_Print_String("\n"); + } + else if (strncmp(&data[8], "test_3", 6) == 0) + { + COMM_Console_Print_String("Test 3: "); + COMM_Console_Print_UInt16(NVM_EXTERNAL_TEST_3); + COMM_Console_Print_String("\n"); + } + else if (strncmp(&data[8], "test_4", 6) == 0) + { + COMM_Console_Print_String("Test 4: "); + COMM_Console_Print_UInt32(NVM_EXTERNAL_TEST_4); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Unknown NVM parameter!\n"); + } + } + else if ((data[4] == 's') && (data[5] == 'e') && (data[6] == 't') && (data[7] == ' ')) + { + if (strncmp(&data[8], "volume", 6) == 0) + { + uint8_t volume = 0; + if (COMM_Console_DecodeParameterUInt8(&(data[15]), &volume) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_VOLUME = volume; + NVM_SaveExternalEEPROMEntry(NVM_VOLUME_ENTRY_PTR); + + COMM_Console_Print_String("Volume changed to "); + COMM_Console_Print_UInt8(NVM_VOLUME); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else if (strncmp(&data[8], "test_1", 6) == 0) + { + uint16_t test_value = 0; + if (COMM_Console_DecodeParameterUInt16(&(data[15]), &test_value) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_ONCHIP_TEST_1 = test_value; + NVM_SaveOnChipEEPROMEntry(NVM_ONCHIP_TEST_1_ENTRY_PTR); + + COMM_Console_Print_String("Test 1 value changed to "); + COMM_Console_Print_UInt16(NVM_ONCHIP_TEST_1); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else if (strncmp(&data[8], "test_2", 6) == 0) + { + uint32_t test_value = 0; + if (COMM_Console_DecodeParameterUInt32(&(data[15]), &test_value) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_ONCHIP_TEST_2 = test_value; + NVM_SaveOnChipEEPROMEntry(NVM_ONCHIP_TEST_2_ENTRY_PTR); + + COMM_Console_Print_String("Test 2 value changed to "); + COMM_Console_Print_UInt32(NVM_ONCHIP_TEST_2); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else if (strncmp(&data[8], "test_3", 6) == 0) + { + uint16_t test_value = 0; + if (COMM_Console_DecodeParameterUInt16(&(data[15]), &test_value) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_EXTERNAL_TEST_3 = test_value; + NVM_SaveExternalEEPROMEntry(NVM_EXTERNAL_TEST_3_ENTRY_PTR); + + COMM_Console_Print_String("Test 3 value changed to "); + COMM_Console_Print_UInt16(NVM_EXTERNAL_TEST_3); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else if (strncmp(&data[8], "test_4", 6) == 0) + { + uint32_t test_value = 0; + if (COMM_Console_DecodeParameterUInt32(&(data[15]), &test_value) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + NVM_EXTERNAL_TEST_4 = test_value; + NVM_SaveExternalEEPROMEntry(NVM_EXTERNAL_TEST_4_ENTRY_PTR); + + COMM_Console_Print_String("Test 4 value changed to "); + COMM_Console_Print_UInt32(NVM_EXTERNAL_TEST_4); + COMM_Console_Print_String("\n"); + } + else + { + COMM_Console_Print_String("ERROR: Parameter value unrecognized or missing!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: Unknown NVM parameter!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: Unknown NVM command!\n"); + } + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.h b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.h new file mode 100644 index 0000000..d71ee1a --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_NVM_ConsoleCommands.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file declares the serial console commands for the Nonvolatile Memory. + */ + +#ifndef COMM_NVM_CONSOLECOMMANDS_H +#define COMM_NVM_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Command_Result_T COMM_NVM_HandleConsoleNVMCommand(char8 * data, uint32_t size); + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_NVM_CONSOLECOMMANDS_H diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.c b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.c new file mode 100644 index 0000000..109755e --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.c @@ -0,0 +1,109 @@ +/** \file + * \brief This file defines the serial console commands for the RTOS package. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ + +/* Public Variables */ + +/* Private Variables */ + +/* Public Functions */ + +/* Private Functions */ + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleVersion(char8 * data, uint32_t size) +{ + COMM_Console_Print_String("PSoC 6 running FreeRTOS "); + + COMM_Console_Print_String(tskKERNEL_VERSION_NUMBER); + +#ifdef NDEBUG + COMM_Console_Print_String(" (Release, compiled "); +#else + COMM_Console_Print_String(" (Debug, compiled "); +#endif // NDEBUG + + COMM_Console_Print_String(__DATE__); + COMM_Console_Print_String(" "); + COMM_Console_Print_String(__TIME__); + COMM_Console_Print_String(").\n"); + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleStack(char8 * data, uint32_t size) +{ + for (uint_fast8_t i = 0; i < CONFIG_N_TASK_HANDLES; i++) + { + TaskStatus_t status; + vTaskGetInfo(*CONFIG_TaskHandles[i], &status, pdTRUE, eInvalid); + COMM_Console_Print_String(status.pcTaskName); + COMM_Console_Print_String(": "); + COMM_Console_Print_UInt16(status.usStackHighWaterMark); + COMM_Console_Print_String("\n"); + } + + // Repeat for the Idle Task. + { + TaskStatus_t status; + vTaskGetInfo(xTaskGetIdleTaskHandle(), &status, pdTRUE, eInvalid); + COMM_Console_Print_String(status.pcTaskName); + COMM_Console_Print_String(": "); + COMM_Console_Print_UInt16(status.usStackHighWaterMark); + COMM_Console_Print_String("\n"); + } + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleCPU(char8 * data, uint32_t size) +{ + // data[0] through data[3] is 'cpu '. + if (data[4] == 'r') + { + //COMM_Console_Print_String("Max CPU reset.\n"); + COMM_Console_Print_String("(Not yet implemented.)\n"); + } + else + { + for (uint_fast8_t i = 0; i < CONFIG_N_TASK_HANDLES; i++) + { + TaskStatus_t status; + vTaskGetInfo(*CONFIG_TaskHandles[i], &status, pdTRUE, eInvalid); + COMM_Console_Print_String(status.pcTaskName); + COMM_Console_Print_String(": "); + COMM_Console_Print_UInt32(status.ulRunTimeCounter); + COMM_Console_Print_String("\n"); + } + + // Repeat for the Idle Task. + { + TaskStatus_t status; + vTaskGetInfo(xTaskGetIdleTaskHandle(), &status, pdTRUE, eInvalid); + COMM_Console_Print_String(status.pcTaskName); + COMM_Console_Print_String(": "); + COMM_Console_Print_UInt16(status.ulRunTimeCounter); + COMM_Console_Print_String("\n"); + } + } + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleReboot(char8 * data, uint32_t size) +{ + (void) COMM_SendMessageToOtherCore(COMM_SMM_RebootImmediately, NULL); + + // Not that it matters... + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.h b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.h new file mode 100644 index 0000000..6478c06 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_RTOS_ConsoleCommands.h @@ -0,0 +1,32 @@ +/** \file + * \brief This file declares the serial console commands for the RTOS package. + */ + +#ifndef COMM_RTOS_CONSOLECOMMANDS_H +#define COMM_RTOS_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleVersion(char8 * data, uint32_t size); +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleStack(char8 * data, uint32_t size); +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleCPU(char8 * data, uint32_t size); +COMM_Console_Command_Result_T COMM_RTOS_HandleConsoleReboot(char8 * data, uint32_t size); + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_RTOS_CONSOLECOMMANDS_H \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.c b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.c new file mode 100644 index 0000000..83d8bcf --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.c @@ -0,0 +1,189 @@ +/** \file + * \brief This file defines the serial console commands for the high-level state machine. + */ + +/* Include Files */ +#include "KTag.h" + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Local Definitions and Constants */ + +/* Private Function Prototypes */ +static void Simulate_Hit(uint8_t team_ID, uint16_t damage); + +/* Public Variables */ + +/* Private Variables */ + +/* Public Functions */ + +//! Console command handler for the 'event' command. +COMM_Console_Command_Result_T COMM_HandleEventCommand(char8 * data, uint32_t size) +{ + // data[0] through data[5] is 'event '. + + if (data[6] == '?') + { + COMM_Console_Print_String("event ? Display this help.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("event raw Inject the event with ID .\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("event tag Send tag(s).\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + COMM_Console_Print_String("event hit Simulate a hit from team for damage.\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + } + else if ( (data[6] == 'r') && + (data[7] == 'a') && + (data[8] == 'w') ) + + { + if (COMM_Console_IsEndOfMessage(data[9])) + { + COMM_Console_Print_String("ERROR: missing event ID!\n"); + } + else if (data[9] == ' ') + { + uint16_t id = 0; + + if (COMM_Console_DecodeParameterUInt16(&(data[10]), &id) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + if ((id > KEVENT_NO_EVENT) && (id < KEVENT_IS_OUT_OF_RANGE)) + { + KEvent_T raw_event = { .ID = id, .Data = (void *)0x00 }; + Post_KEvent(&raw_event); + } + else + { + COMM_Console_Print_String("ERROR: specified event ID ("); + COMM_Console_Print_UInt16(id); + COMM_Console_Print_String(") is invalid!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: could not comprehend event ID!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: unrecognized or mangled command!\n"); + } + } + else if ( (data[6] == 't') && + (data[7] == 'a') && + (data[8] == 'g') ) + + { + if (COMM_Console_IsEndOfMessage(data[9])) + { + if (Send_Tag() == SYSTEMK_RESULT_SUCCESS) + { + COMM_Console_Print_String("Tag sent.\n"); + } + else + { + COMM_Console_Print_String("Error: Couldn't send tag!\n"); + } + } + else if (data[9] == ' ') + { + uint16_t times = 0; + + if (COMM_Console_DecodeParameterUInt16(&(data[10]), ×) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + while (times > 0) + { + if (Send_Tag() == SYSTEMK_RESULT_SUCCESS) + { + COMM_Console_Print_String("Tag sent.\n"); + } + else + { + COMM_Console_Print_String("Error: Couldn't send tag!\n"); + } + //! \todo Why can't the console command 'event tag ' send tags faster than once per second? + vTaskDelay(1000 / portTICK_PERIOD_MS); + times--; + } + } + else + { + COMM_Console_Print_String("ERROR: could not comprehend tag repetitions!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: unrecognized or mangled command!\n"); + } + } + else if ( (data[6] == 'h') && + (data[7] == 'i') && + (data[8] == 't') ) + + { + if (COMM_Console_IsEndOfMessage(data[9])) + { + Simulate_Hit(1, 10); + COMM_Console_Print_String("Hit!\n"); + } + else if (data[9] == ' ') + { + uint8_t team_ID = 0; + uint16_t damage = 10; + + if (COMM_Console_DecodeParameterUInt8(&(data[10]), &team_ID) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + const char * damage_location; + + // Damage is the first parameter after team ID. + if (COMM_Console_FindNthParameter(&(data[10]), 1, &damage_location) == COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + if (COMM_Console_DecodeParameterUInt16(damage_location, &damage) != COMM_CONSOLE_PARAMETER_RESULT_SUCCESS) + { + COMM_Console_Print_String("ERROR: could not comprehend damage--using default.\n"); + damage = 10; + } + } + Simulate_Hit(team_ID, damage); + COMM_Console_Print_String("Hit!\n"); + } + else + { + COMM_Console_Print_String("ERROR: could not comprehend team ID!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: unrecognized or mangled command!\n"); + } + } + else + { + COMM_Console_Print_String("ERROR: Unknown event command!\n"); + } + + + return COMM_CONSOLE_CMD_RESULT_SUCCESS; +} + +/* Private Functions */ + +static void Simulate_Hit(uint8_t team_ID, uint16_t damage) +{ + static DecodedPacket_T Simulated_Tag_Rx_Buffer; + static KEvent_T tag_received_event; + + Simulated_Tag_Rx_Buffer.Tag.type = DECODED_PACKET_TYPE_TAG_RECEIVED; + Simulated_Tag_Rx_Buffer.Tag.protocol = LASER_X_PROTOCOL; + Simulated_Tag_Rx_Buffer.Tag.player_ID = 0x00; + Simulated_Tag_Rx_Buffer.Tag.team_ID = team_ID; + Simulated_Tag_Rx_Buffer.Tag.damage = damage; + Simulated_Tag_Rx_Buffer.Tag.color = GetColorFromTeamID(team_ID); + tag_received_event.ID = KEVENT_TAG_RECEIVED; + tag_received_event.Data = &Simulated_Tag_Rx_Buffer; + Post_KEvent(&tag_received_event); +} + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) diff --git a/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.h b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.h new file mode 100644 index 0000000..0c29268 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/COMM/ConsoleCommands/COMM_STATE_ConsoleCommands.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file declares the serial console commands for the high-level state machine. + */ + +#ifndef COMM_STATE_CONSOLECOMMANDS_H +#define COMM_STATE_CONSOLECOMMANDS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +/* Public Functions */ +COMM_Console_Command_Result_T COMM_HandleEventCommand(char8 * data, uint32_t size); + +#endif // (CONFIG__FEATURE_COMM_CONSOLE == CONFIG__FEATURE_ENABLED) + +#ifdef __cplusplus +} +#endif + +#endif // COMM_STATE_CONSOLECOMMANDS_H diff --git a/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG.h b/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG.h new file mode 100644 index 0000000..0270516 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG.h @@ -0,0 +1,84 @@ +/** \dir "CONFIG" + * + * \brief This directory contains configuration files for this software. + * + */ + +/** \file + * \brief This file includes project-wide for this software. + * + * This file should be included by every file outside the CONFIG package! + * + * \note As always, should be included before this file. + */ + +#ifndef CONFIG_H +#define CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "CONFIG_RTOS.h" + +//! Value of audio volume represeting the maximum volume possible for this device. +#define CONFIG_KTAG_MAX_AUDIO_VOLUME 30 + +//! Value of audio volume represeting the minimum volume possible for this device. +#define CONFIG_KTAG_MIN_AUDIO_VOLUME 5 + +//! Time (in milliseconds) after starting a game before the countdown begins. +//#define CONFIG_KTAG_T_DEFAULT_START_GAME_in_ms (30 * 1000) +#define CONFIG_KTAG_T_DEFAULT_START_GAME_in_ms (3 * 1000) + +//! true if the hardware includes internal (on-chip) NVM. +#define CONFIG__HAS_INTERNAL_NVM true + +//! true if the hardware includes an external (I2C) NVM chip. +#define CONFIG__HAS_EXTERNAL_NVM true + +// '||' || '|| '||''|. TM +// || ... || || || ... .. ... ... .... ... +// || || || ||'''|. ||' '' || || '|. | +// || || || || || || || || '|.| +// .||.....| .||. .||. .||...|' .||. '|..'|. '| + +#if (defined LIL_BRUV) || (defined LITTLE_BOY_BLUE) + +//! Number of NeoPixel channels supported. +#define CONFIG_KTAG_N_NEOPIXEL_CHANNELS 1 + +//! Maximum number of NeoPixels on a single channel. +#define CONFIG_KTAG_MAX_NEOPIXELS_PER_CHANNEL 5 + + + +// /\ /\\ /\ /\\ TM +// ( ) || || ( ) || || |''||''| '||''|. ..|'''.| +// // || || // || || || || || .|' ' +// // || || // || || || ||...|' || +// /( || || /( || || || || '|. . +// {___ \\/ {___ \\/ .||. .||. ''|....' + +#elif (defined TWENTY20TPC) + +//! Number of NeoPixel channels supported. +#define CONFIG_KTAG_N_NEOPIXEL_CHANNELS 4 + +//! Maximum number of NeoPixels on a single channel. +#define CONFIG_KTAG_MAX_NEOPIXELS_PER_CHANNEL 8 + + + +#else + #error "No recognized KTag models defined. Supported models are: LIL_BRUV, LITTLE_BOY_BLUE, and TWENTY20TPC." +#endif + +//! Time between NeoPixel animation frames, in milliseconds. +#define CONFIG_KTAG_ANIMATION_STEP_TIME_IN_ms 10 + +#ifdef __cplusplus +} +#endif + +#endif // CONFIG_H \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG_RTOS.c b/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG_RTOS.c new file mode 100644 index 0000000..9c97c6c --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG_RTOS.c @@ -0,0 +1,113 @@ +/** \file + * \brief This file defines and registers the tasks used by the Real-Time Operating System. + * + * See CONFIG_RTOS.h for a detailed description of the functionality implemented by this code. + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/*---------------------------------------------------------------------------*/ +/* Task priorities: Low priority numbers denote low priority tasks. + * + * Low == 0 == tskIDLE_PRIORITY + * ... + * High == (configMAX_PRIORITIES - 1) + * + * See http://www.freertos.org/RTOS-task-priority.html for more information. + */ +#define CAPSENSE_TASK_PRIORITY (tskIDLE_PRIORITY + 3) +#define SAMPLE_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define FIRE_CONTROL_TASK_PRIORITY (tskIDLE_PRIORITY + 1) +#define AUDIO_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define NEOPIXELS_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define TAG_SENSORS_TASK_PRIORITY (tskIDLE_PRIORITY + 5) +#define SWITCHES_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define NVM_EXTERNAL_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define NVM_ON_CHIP_EEPROM_TASK_PRIORITY (tskIDLE_PRIORITY + 1) +#define COMM_CONSOLE_TASK_PRIORITY (tskIDLE_PRIORITY + 2) +#define COMM_BLE_TASK_PRIORITY (tskIDLE_PRIORITY + 4) + + +/* External Variables [Only if necessary!] */ + +/* External Function Prototypes [Only if necessary!] */ + +/* Public Variables */ + +//! Array of all the handles for the configured RTOS tasks. +TaskHandle_t * const CONFIG_TaskHandles[] = {&HW_CapSense_Task_Handle, + &Fire_Control_Task_Handle, + &Sample_Task_Handle, + &Audio_Task_Handle, + &NeoPixels_Task_Handle, + &Tag_Sensors_Task_Handle, + &Switches_Task_Handle, + &State_Machine_Task_Handle, + &NVM_ExternalEEPROM_Task_Handle, + &NVM_OnChipEEPROM_Task_Handle, + &COMM_Console_Task_Handle, + &COMM_BLE_Task_Handle}; + +//! Size of the #CONFIG_TaskHandles array (i.e. the number of configured tasks). +const uint8_t CONFIG_N_TASK_HANDLES = (uint8_t) (sizeof(CONFIG_TaskHandles) / sizeof(TaskHandle_t *)); + +/* Private Variables */ + +/* Private Function Prototypes */ + +/* Public Functions */ + +void CONFIG_InitTasks(void) +{ + HW_CapSense_Init(); + COMM_I2C_Init(); + NVM_InitExternalEEPROM(); + NVM_InitOnChipEEPROM(); + Sample_Task_Init(); + Init_Fire_Control(); + Tag_Sensors_Init(); + Init_Audio(); + Switches_Init(); + COMM_Console_Init(); + COMM_BLE_Init(); +} + +//! Registers tasks with the kernel, and then runs them. +/*! + * This function should not return. +*/ +void CONFIG_RunTasks(void) +{ + (void) xTaskCreate(HW_CapSense_Task, "CapSense Task", HW_CAPSENSE_TASK_STACK_SIZE_in_bytes, NULL, CAPSENSE_TASK_PRIORITY, &HW_CapSense_Task_Handle); + (void) xTaskCreate(Fire_Control_Task, "Fire Control Task", configMINIMAL_STACK_SIZE, NULL, FIRE_CONTROL_TASK_PRIORITY, &Fire_Control_Task_Handle); + (void) xTaskCreate(Sample_Task, "Sample Task", configMINIMAL_STACK_SIZE, NULL, SAMPLE_TASK_PRIORITY, &Sample_Task_Handle); + (void) xTaskCreate(Audio_Task, "Audio Task", configMINIMAL_STACK_SIZE, NULL, AUDIO_TASK_PRIORITY, &Audio_Task_Handle); + (void) xTaskCreate(NeoPixels_Task, "NeoPixels Task", configMINIMAL_STACK_SIZE, NULL, NEOPIXELS_TASK_PRIORITY, &NeoPixels_Task_Handle); + (void) xTaskCreate(Tag_Sensors_Task, "Tag Sensors Task", configMINIMAL_STACK_SIZE, NULL, TAG_SENSORS_TASK_PRIORITY, &Tag_Sensors_Task_Handle); + (void) xTaskCreate(Switches_Task, "Switches Task", configMINIMAL_STACK_SIZE, NULL, SWITCHES_TASK_PRIORITY, &Switches_Task_Handle); + (void) xTaskCreate(NVM_OnChipEEPROMTask, "NVMOn", NVM_ON_CHIP_EEPROM_TASK_STACK_SIZE_in_bytes, NULL, NVM_ON_CHIP_EEPROM_TASK_PRIORITY, &NVM_OnChipEEPROM_Task_Handle); + (void) xTaskCreate(NVM_ExternalEEPROMTask, "NVMEx", NVM_EXTERNAL_EEPROM_TASK_STACK_SIZE_in_bytes, NULL, NVM_EXTERNAL_TASK_PRIORITY, &NVM_ExternalEEPROM_Task_Handle); + (void) xTaskCreate(COMM_Console_Task, "Console Task", COMM_CONSOLE_TASK_STACK_SIZE_in_bytes, NULL, COMM_CONSOLE_TASK_PRIORITY, &COMM_Console_Task_Handle); + (void) xTaskCreate(COMM_BLE_Task, "BLE Task", COMM_BLE_TASK_STACK_SIZE_in_bytes, NULL, COMM_BLE_TASK_PRIORITY, &COMM_BLE_Task_Handle); + + if (Initialize_SystemK() != SYSTEMK_RESULT_SUCCESS) + { + KLOG_ERROR("CONFIG", "Failed to initilaize SystemK!"); + } + + /* This should not return. */ + vTaskStartScheduler(); + + // Something went wrong. +#ifdef DEBUG + // Break into the debugger. + __BKPT(0); +#else // DEBUG + __NVIC_SystemReset(); +#endif // DEBUG +} + +/* Private Functions */ diff --git a/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG_RTOS.h b/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG_RTOS.h new file mode 100644 index 0000000..26709c3 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/CONFIG/CONFIG_RTOS.h @@ -0,0 +1,29 @@ +/** \file + * \brief This file configures the Real-Time Operating System (RTOS). + */ + +#ifndef CONFIG_RTOS_H +#define CONFIG_RTOS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Include Files */ + +/* Preprocessor and Type Definitions */ + +/* Public Variables */ + +extern TaskHandle_t * const CONFIG_TaskHandles[]; +extern const uint8_t CONFIG_N_TASK_HANDLES; + +/* Public Functions */ +void CONFIG_InitTasks(void); +void CONFIG_RunTasks(void); + +#ifdef __cplusplus +} +#endif + +#endif // CONFIG_RTOS_H diff --git a/2020TPCAppNoDFU.cydsn/Fire_Control.c b/2020TPCAppNoDFU.cydsn/Fire_Control.c new file mode 100644 index 0000000..6033112 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Fire_Control.c @@ -0,0 +1,223 @@ +/* Include Files */ +#include "KTag.h" + +#define FIRE_CONTROL_REGISTER__IR_OFF 0b00000 +#define FIRE_CONTROL_REGISTER__IR_ON_MODULATED_LOW_POWER 0b00011 +#define FIRE_CONTROL_REGISTER__IR_ON_MODULATED_HIGH_POWER 0b00101 +#define FIRE_CONTROL_REGISTER__IR_ON_MODULATED_MAX_POWER 0b11111 +#define FIRE_CONTROL_REGISTER__IR_ON_UNMODULATED_LOW_POWER 0b00010 +#define FIRE_CONTROL_REGISTER__IR_ON_UNMODULATED_HIGH_POWER 0b00100 +#define FIRE_CONTROL_REGISTER__IR_ON_UNMODULATED_MAX_POWER 0b00110 + +#define TRIGGER_STATUS_REGISTER__NO_ACTION 0x00 +#define TRIGGER_STATUS_REGISTER__TRIGGER_PULLED 0x01 +#define TRIGGER_STATUS_REGISTER__TRIGGER_RELEASED 0x02 + + +void Trigger_Interrupt_ISR(); +void Bit_Stream_Timer_ISR(); + +TimedPulseTrain_T * Shot_Buffer; +TagPacket_T Shot_Packet; + +TaskHandle_t Fire_Control_Task_Handle; + +static TimedPulseTrain_T * Active_Pulse_Train = NULL; +static uint8_t Active_Bitstream_Index = 0; + +static TickType_t TicksAtTriggerPress; + +static inline void Initiate_Pulse_Train(TimedPulseTrain_T * pulsetrain) +{ + Bit_Stream_Timer_Disable(); + Active_Pulse_Train = pulsetrain; + Active_Bitstream_Index = 0; + + if (Active_Pulse_Train->bitstream[Active_Bitstream_Index].symbol == MARK) + { + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_ON_MODULATED_MAX_POWER); + } + else + { + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); + } + Bit_Stream_Timer_SetPeriod(Active_Pulse_Train->bitstream[0].duration); + Bit_Stream_Timer_SetCounter(0); + Active_Bitstream_Index++; + Bit_Stream_Timer_Enable(); + Bit_Stream_Timer_TriggerStart(); +} + +static inline void Next_Bit(void) +{ + static BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + Bit_Stream_Timer_Disable(); + + if (Active_Pulse_Train->bitstream[Active_Bitstream_Index].duration != LAST_PULSE) + { + if (Active_Pulse_Train->bitstream[Active_Bitstream_Index].symbol == MARK) + { + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_ON_MODULATED_MAX_POWER); + } + else + { + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); + } + + if (Active_Bitstream_Index < ((2*MAX_PULSES) - 2)) + { + Bit_Stream_Timer_SetPeriod(Active_Pulse_Train->bitstream[Active_Bitstream_Index].duration); + Bit_Stream_Timer_SetCounter(0); + Active_Bitstream_Index++; + Bit_Stream_Timer_Enable(); + Bit_Stream_Timer_TriggerStart(); + } + else + { + // The bitstream is too long! + + // Turn the IR Emitter off, and wait a long time. + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); + xSemaphoreGiveFromISR(NeoPixels_Semaphore, &xHigherPriorityTaskWoken); + Bit_Stream_Timer_SetPeriod(UINT16_MAX); + Bit_Stream_Timer_SetCounter(0); + Active_Pulse_Train = NULL; + Bit_Stream_Timer_Enable(); + Bit_Stream_Timer_TriggerStart(); + } + } + else + { + // Turn the IR Emitter off, and wait a long time. + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); + xSemaphoreGiveFromISR(NeoPixels_Semaphore, &xHigherPriorityTaskWoken); + Bit_Stream_Timer_SetPeriod(UINT16_MAX); + Bit_Stream_Timer_SetCounter(0); + Active_Pulse_Train = NULL; + Bit_Stream_Timer_Enable(); + Bit_Stream_Timer_TriggerStart(); + } + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + +void Init_Fire_Control(void) +{ + // Register and enable the ISRs. + Cy_SysInt_Init(&Trigger_Interrupt_cfg, Trigger_Interrupt_ISR); + Cy_SysInt_Init(&Bit_Stream_Timer_Interrupt_cfg, Bit_Stream_Timer_ISR); + NVIC_EnableIRQ(Trigger_Interrupt_cfg.intrSrc); + NVIC_EnableIRQ(Bit_Stream_Timer_Interrupt_cfg.intrSrc); + + // Initialize the hardware. + Bit_Stream_Timer_Clock_Enable(); + Bit_Stream_Timer_Init(&Bit_Stream_Timer_config); + Bit_Stream_Timer_SetPeriod(2); + Bit_Stream_Timer_Start(); + SW_CLK_Enable(); + PWM_IR_Modulation_Start(); + + + Fire_Control_Register_Write(FIRE_CONTROL_REGISTER__IR_OFF); +} + +void Fire_Control_Task(void * pvParameters) +{ + while (true) + { + vTaskDelay(1000 / portTICK_PERIOD_MS); + } +} + +SystemKResult_T Prepare_Tag() +{ + Shot_Packet.player_ID = NVM_PLAYER_ID; + Shot_Packet.team_ID = NVM_TEAM_ID; + Weapon_t weapon = GetWeaponFromID(NVM_WEAPON_ID); + Shot_Packet.color = (uint32_t)PROTOCOLS_GetColor(weapon.Protocol, Shot_Packet.team_ID, Shot_Packet.player_ID); + Shot_Packet.protocol = weapon.Protocol; + Shot_Packet.damage = weapon.Damage_Per_Shot; + Shot_Buffer = PROTOCOLS_EncodePacket(&Shot_Packet); + Fire_Control_Set_Modulation_Frequency(PROTOCOLS_GetModulationFrequency(weapon.Protocol)); + return SYSTEMK_RESULT_SUCCESS; +} + +SystemKResult_T Send_Tag() +{ + xSemaphoreTake(NeoPixels_Semaphore, portMAX_DELAY); + Initiate_Pulse_Train(Shot_Buffer); + + KEvent_T tag_sent_event = { .ID = KEVENT_TAG_SENT, .Data = (void *)0x00 }; + Post_KEvent(&tag_sent_event); + + return SYSTEMK_RESULT_SUCCESS; +} + +void Fire_Control_Set_Modulation_Frequency(ModulationFrequency_T freq) +{ + PWM_IR_Modulation_TriggerKill(); + if (freq == FREQUENCY_38kHz) + { + PWM_IR_Modulation_SetPeriod0(314); + //PWM_IR_Modulation_SetCompare0(314/2); // 50% Duty Cycle + PWM_IR_Modulation_SetCompare0((314 * 3)/10); // 30% Duty Cycle + } + else // (freq == FREQUENCY_56kHz) + { + PWM_IR_Modulation_SetPeriod0(213); + //PWM_IR_Modulation_SetCompare0(213/2); // 50% Duty Cycle + PWM_IR_Modulation_SetCompare0((213 * 3)/10); // 30% Duty Cycle + } + PWM_IR_Modulation_TriggerStart(); +} + +//! ISR for the trigger input. +void Trigger_Interrupt_ISR() +{ + portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; + + // Clear the interrupt. + NVIC_ClearPendingIRQ(Trigger_Interrupt_cfg.intrSrc); + + // Read the trigger register to know if this was a pull or a release. + uint8_t trigger_status = Trigger_Status_Reg_Read(); + + if ((trigger_status & TRIGGER_STATUS_REGISTER__TRIGGER_PULLED) == TRIGGER_STATUS_REGISTER__TRIGGER_PULLED) + { + TicksAtTriggerPress = xTaskGetTickCountFromISR(); + KEvent_T switch_event = {.ID = KEVENT_CENTER_SWITCH_PRESSED, .Data = NULL}; + Post_KEvent_From_ISR(&switch_event, &xHigherPriorityTaskWoken); + } + else if ((trigger_status & TRIGGER_STATUS_REGISTER__TRIGGER_RELEASED) == TRIGGER_STATUS_REGISTER__TRIGGER_RELEASED) + { + uint32_t triggerPressDurationInms = pdTICKS_TO_MS(xTaskGetTickCountFromISR() - TicksAtTriggerPress); + KEvent_T switch_event = {.ID = KEVENT_CENTER_SWITCH_RELEASED, .Data = (void *) triggerPressDurationInms}; + Post_KEvent_From_ISR(&switch_event, &xHigherPriorityTaskWoken); + } + else + { + // What happened!!? + } + + // If an event was enqueued above, a context switch might be required. + // xHigherPriorityTaskWoken was initialized to pdFALSE on interrupt entry. If calling + // xSemaphoreGiveFromISR() caused a task to unblock, and the unblocked task has a + // priority equal to or higher than the currently running task (the task that was + // interrupted by this ISR), then xHigherPriorityTaskWoken will have been set to pdTRUE + // and portEND_SWITCHING_ISR() will request a context switch to the newly unblocked task. + portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); +} + +void Bit_Stream_Timer_ISR() +{ + // Get all the enabled pending interrupts... + uint32_t source = Bit_Stream_Timer_GetInterruptStatusMasked(); + // ...and clear them. + Bit_Stream_Timer_ClearInterrupt(source); + + if (Active_Pulse_Train != NULL) + { + Next_Bit(); + } +} diff --git a/2020TPCAppNoDFU.cydsn/Fire_Control.h b/2020TPCAppNoDFU.cydsn/Fire_Control.h new file mode 100644 index 0000000..bcf8e72 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Fire_Control.h @@ -0,0 +1,13 @@ +#ifndef FIRE_CONTROL_H +#define FIRE_CONTROL_H + +#include +#include + +extern TaskHandle_t Fire_Control_Task_Handle; + +void Init_Fire_Control(void); +void Fire_Control_Task(void * pvParameters); +void Fire_Control_Set_Modulation_Frequency(ModulationFrequency_T freq); + +#endif // FIRE_CONTROL_H diff --git a/2020TPCAppNoDFU.cydsn/FreeRTOSConfig.h b/2020TPCAppNoDFU.cydsn/FreeRTOSConfig.h new file mode 100644 index 0000000..ff41915 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/FreeRTOSConfig.h @@ -0,0 +1,228 @@ +/* + * FreeRTOS Kernel V10.0.1 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#include "syslib/cy_syslib.h" + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configUSE_TICKLESS_IDLE 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ 1000u +#define configMAX_PRIORITIES 15 +#define configMINIMAL_STACK_SIZE 512 +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 10 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 0 +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 5 + +/* Memory allocation related definitions. */ +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configTOTAL_HEAP_SIZE (64*1024) +#define configAPPLICATION_ALLOCATED_HEAP 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 1 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + + +//! Debug Exception and Monitor Control register +#define CORE_DBG_EXC_MON_CTL (*(uint32_t *)0xE000EDFC) + +//! DWT Control Register +#define DWT_CTRL (*(uint32_t *)0xE0001000) + +//! DWT Current PC Sampler Cycle Count Register +/*! + * Use the DWT Current PC Sampler Cycle Count Register to count the number of core cycles. This + * count can measure elapsed execution time. + */ +#define DWT_CYCCNT (*(uint32_t *)0xE0001004) + +//! Initializes the Data Watchpoint and Trace Unit and starts the CYCCNT counter. +static inline void vCONFIGURE_TIMER_FOR_RUN_TIME_STATS(void) +{ + // If the Data Watchpoint and Trace Unit is present, #DWT_CTRL will be non-zero. + if (DWT_CTRL != 0) + { + // Set bit 24 (TRCENA) on the CORE_DBG_EXC_MON_CTL register to enable use of the DWT. + CORE_DBG_EXC_MON_CTL |= (1 << 24); + // Initialize the count register. + DWT_CYCCNT = 0; + // Set bit 0 (CYCCNTENA) on the DWT_CTRL register to enable the CYCCNT counter. + DWT_CTRL |= (1 << 0); + } +} + +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS vCONFIGURE_TIMER_FOR_RUN_TIME_STATS + +//! Returns the current value of the DWT Current PC Sampler Cycle Count Register +/*! + * Use the DWT Current PC Sampler Cycle Count Register to count the number of core cycles. This + * count can measure elapsed execution time. + */ +static inline uint32_t ulGET_RUN_TIME_COUNTER_VALUE(void) +{ + return DWT_CYCCNT; +} + +#define portGET_RUN_TIME_COUNTER_VALUE ulGET_RUN_TIME_COUNTER_VALUE + +/* Co-routine related definitions. */ +#define configUSE_CO_ROUTINES 1 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY 3 +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* FreeRTOS MPU specific definitions. */ +#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 + +/* +Interrupt nesting behavior configuration. +This is explained here: http://www.freertos.org/a00110.html + +Priorities are controlled by two macros: +- configKERNEL_INTERRUPT_PRIORITY determines the priority of the RTOS daemon task +- configMAX_API_CALL_INTERRUPT_PRIORITY dictates the priority of ISRs that make API calls + +Notes: +1. Interrupts that do not call API functions should be >= configKERNEL_INTERRUPT_PRIORITY + and will nest. +2. Interrupts that call API functions must have priority between KERNEL_INTERRUPT_PRIORITY + and MAX_API_CALL_INTERRUPT_PRIORITY (inclusive). +3. Interrupts running above MAX_API_CALL_INTERRUPT_PRIORITY are never delayed by the OS. +*/ +/* +PSoC 6 __NVIC_PRIO_BITS = 3 + +0 (high) +1 MAX_API_CALL_INTERRUPT_PRIORITY 001xxxxx (0x3F) +2 +3 +4 +5 +6 +7 (low) KERNEL_INTERRUPT_PRIORITY 111xxxxx (0xFF) + +!!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + +If you call a FreeRTOS API function from an interrupt with priority higher than +MAX_API_CALL_INTERRUPT_PRIORITY FreeRTOS will generate an exception. If you need +to call a FreeRTOS API function from your system’s highest priority interrupt +you must reduce all interrupt priorities to MAX_API_CALL_INTERRUPT_PRIORITY or +lower. + +If your system pipe (IPC) interrupt priority is less than or equal to +MAX_API_CALL_INTERRUPT_PRIORITY then care must be taken with code that writes to +flash (including the Flash/BLE/Emulated EEPROM/Bootloader drivers from Cypress +PDL). The duration of critical sections must be kept short - see the +Configuration Considerations section of the flash driver in the PDL API +Reference. + +*/ + +/* Put KERNEL_INTERRUPT_PRIORITY in top __NVIC_PRIO_BITS bits of CM4 register */ +#define configKERNEL_INTERRUPT_PRIORITY 0xFF +/* +Put MAX_SYSCALL_INTERRUPT_PRIORITY in top __NVIC_PRIO_BITS bits of CM4 register +NOTE For IAR compiler make sure that changes of this macro is reflected in +file portable\IAR\CM4F\portasm.s in PendSV_Handler: routine +*/ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 0x3F +/* configMAX_API_CALL_INTERRUPT_PRIORITY is a new name for configMAX_SYSCALL_INTERRUPT_PRIORITY + that is used by newer ports only. The two are equivalent. */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY configMAX_SYSCALL_INTERRUPT_PRIORITY + + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xEventGroupSetBitFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 0 +#define INCLUDE_xTaskAbortDelay 0 +#define INCLUDE_xTaskGetHandle 0 +#define INCLUDE_xTaskResumeFromISR 1 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names - or at least those used in the unmodified vector table. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ diff --git a/2020TPCAppNoDFU.cydsn/HW/HW.h b/2020TPCAppNoDFU.cydsn/HW/HW.h new file mode 100644 index 0000000..0a27ecd --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/HW/HW.h @@ -0,0 +1,50 @@ +/** \dir "HW" + * + * \brief This directory contains source code interfacing to the lowest level of the hardware on this CPU. + * + */ + +/** \file + * \brief This file defines the interface to the low-level hardware used by this software. + * + * This file should be included by any file outside the HW package wishing to make use + * of any of the HW functionality. + * + * \note As always, and should be included before this file. + */ + +#ifndef HW_H +#define HW_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +//! Represents the states of a Digital Input or Digital Output. +typedef enum +{ + //! Represents low voltage (logic '0') on a digital input or output. + HW_DIGITAL_STATE_LOW = 0, + + //! Represents high voltage (logic '1') on a digital input or output. + HW_DIGITAL_STATE_HIGH = 1, + + //! Used when the state of a digital input or output cannot be determined. + HW_DIGITAL_STATE_UNKNOWN = 2 +} HW_DigitalState_T; + +/* Include Files */ + +#include "HW_CapSense.h" + +/* Public Variables */ + +/* Public Functions */ + +#ifdef __cplusplus +} +#endif + +#endif // HW_H diff --git a/2020TPCAppNoDFU.cydsn/HW/HW_CapSense.c b/2020TPCAppNoDFU.cydsn/HW/HW_CapSense.c new file mode 100644 index 0000000..14db4b5 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/HW/HW_CapSense.c @@ -0,0 +1,125 @@ +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +#define CAPSENSE_TASK_PERIOD_IN_ms 50 + +/* Public Variables */ + +TaskHandle_t HW_CapSense_Task_Handle; + +/* Private Variables */ + +static const TickType_t CapSense_Task_Delay = CAPSENSE_TASK_PERIOD_IN_ms / portTICK_PERIOD_MS; + +static bool CapSense_One_Pressed = false; +static bool CapSense_Two_Pressed = false; + +/* Private Function Prototypes */ + + +/* Public Functions */ + +//! Initializes the capacitive touch sensing. +void HW_CapSense_Init(void) +{ +} + +//! Capacitive touch sensing task: Manages the capsense, using the PSoC API functions. +/*! + * + */ +void HW_CapSense_Task(void * pvParameters) +{ + TickType_t xLastWakeTime; + + // Initialize the xLastWakeTime variable with the current time. + xLastWakeTime = xTaskGetTickCount(); + + // Start up the capsense component, and initiate the first scan. + // Note that this can't be done in HW_CapSense_Init(), since it requires interrupts to be enabled. + CapSense_Start(); + CapSense_ScanAllWidgets(); + + vTaskDelayUntil(&xLastWakeTime, CapSense_Task_Delay); + + while (true) + { + // Check to see if the CapSense hardware is still busy with a previous scan. + if (CapSense_IsBusy() == CapSense_NOT_BUSY) + { + // Process all the widgets and read the touch information. + CapSense_ProcessAllWidgets(); + + // Perform the on-change logic for "Button One". + if (CapSense_IsSensorActive(CapSense_BUTTON0_WDGT_ID, CapSense_BUTTON0_SNS0_ID)) + { + if (CapSense_One_Pressed == false) + { + KEvent_T switch_event = {.ID = KEVENT_CAPSENSE_ONE_PRESSED, .Data = NULL}; + Post_KEvent(&switch_event); + } + CapSense_One_Pressed = true; + } + else + { + if (CapSense_One_Pressed == true) + { + KEvent_T switch_event = {.ID = KEVENT_CAPSENSE_ONE_RELEASED, .Data = NULL}; + Post_KEvent(&switch_event); + } + CapSense_One_Pressed = false; + } + + // Perform the on-change logic for "Button Two". + if (CapSense_IsSensorActive(CapSense_BUTTON0_WDGT_ID, CapSense_BUTTON0_SNS1_ID)) + { + if (CapSense_Two_Pressed == false) + { + KEvent_T switch_event = {.ID = KEVENT_CAPSENSE_TWO_PRESSED, .Data = NULL}; + Post_KEvent(&switch_event); + } + CapSense_Two_Pressed = true; + } + else + { + if (CapSense_Two_Pressed == true) + { + KEvent_T switch_event = {.ID = KEVENT_CAPSENSE_TWO_RELEASED, .Data = NULL}; + Post_KEvent(&switch_event); + } + CapSense_Two_Pressed = false; + } + + // Initiate the next scan. + CapSense_ScanAllWidgets(); + } + + vTaskDelayUntil(&xLastWakeTime, CapSense_Task_Delay); + } +} + +//! Gets the state of the given CapSense button. +/*! + * \param button the button in question + * \return true if the button was pressed last time it was checked; false otherwise + */ +bool HW_IsCapsenseButtonPressed(HW_CapSenseButton_T button) +{ + bool pressed = false; + + if ((button == HW_CAPSENSE_BUTTON_ONE) && (CapSense_One_Pressed == true)) + { + pressed = true; + } + else if ((button == HW_CAPSENSE_BUTTON_TWO) && (CapSense_Two_Pressed == true)) + { + pressed = true; + } + + return pressed; +} + +/* Private Functions */ + diff --git a/2020TPCAppNoDFU.cydsn/HW/HW_CapSense.h b/2020TPCAppNoDFU.cydsn/HW/HW_CapSense.h new file mode 100644 index 0000000..f357e19 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/HW/HW_CapSense.h @@ -0,0 +1,40 @@ +/** \file + * \brief This file defines the interface to the capacitive touch sensing used by this software. + * + */ + +#ifndef HW_CAPSENSE_H +#define HW_CAPSENSE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +#define HW_CAPSENSE_TASK_STACK_SIZE_in_bytes 128 + +typedef enum +{ + HW_CAPSENSE_BUTTON_ONE, + HW_CAPSENSE_BUTTON_TWO +} HW_CapSenseButton_T; + +/* Include Files */ + +/* Public Variables */ + +//! Handle of the HW_CapSense_Task() given when the task was created. +extern TaskHandle_t HW_CapSense_Task_Handle; + +/* Public Functions */ +void HW_CapSense_Init(void); +void HW_CapSense_Task(void * pvParameters); +bool HW_IsCapsenseButtonPressed(HW_CapSenseButton_T button); + +#ifdef __cplusplus +} +#endif + +#endif // HW_CAPSENSE_H + diff --git a/2020TPCAppNoDFU.cydsn/HW/HW_NeoPixels.c b/2020TPCAppNoDFU.cydsn/HW/HW_NeoPixels.c new file mode 100644 index 0000000..d732a10 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/HW/HW_NeoPixels.c @@ -0,0 +1,392 @@ +// NeoPixel Driver using Direct Memory Access +// +// This implementation is based on the one by Alan Hawse of Elkhorn Creek, +// documented at https://iotexpert.com/2019/01/08/psoc-6-dma-ws2812-leds/. +// We are grateful to Mr. Hawse for sharing this. + +#include "KTag.h" + +#define NEOPIXEL_ZOFFSET (1) +#define NEOPIXEL_ONE3 (0b110<<24) +#define NEOPIXEL_ZERO3 (0b100<<24) +#define NEOPIXEL_SPI_BIT_PER_BIT (3) +#define NEOPIXEL_COLOR_PER_PIXEL (3) +#define NEOPIXEL_BYTES_PER_PIXEL (NEOPIXEL_SPI_BIT_PER_BIT * NEOPIXEL_COLOR_PER_PIXEL) +#define FRAME_BUFFER_SIZE (NEOPIXEL_ZOFFSET + (CONFIG_KTAG_MAX_NEOPIXELS_PER_CHANNEL * NEOPIXEL_BYTES_PER_PIXEL)) + +#if (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 1) + static uint8_t NeoPixel_Barrel_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; +#elif (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 4) + static uint8_t NeoPixel_Barrel_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; + static uint8_t NeoPixel_Receiver_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; + static uint8_t NeoPixel_Display_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; + static uint8_t NeoPixel_Effects_Channel_Frame_Buffer[FRAME_BUFFER_SIZE]; +#else + #error "Unsupported number of NeoPixel channels defined. Supported configurations are 1 and 4." +#endif + +static uint8_t* NeoPixel_Frame_Buffers[CONFIG_KTAG_N_NEOPIXEL_CHANNELS] = +{ +#if (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 1) + NeoPixel_Barrel_Channel_Frame_Buffer +#elif (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 4) + NeoPixel_Barrel_Channel_Frame_Buffer, + NeoPixel_Receiver_Channel_Frame_Buffer, + NeoPixel_Display_Channel_Frame_Buffer, + NeoPixel_Effects_Channel_Frame_Buffer +#else + #error "Unsupported number of NeoPixel channels defined. Supported configurations are 1 and 4." +#endif +}; + +ColorOrder_T ColorOrderByChannel[CONFIG_KTAG_N_NEOPIXEL_CHANNELS]; + +// Since the descriptors are (or should be) set to "trigger on descriptor completion" (`.interruptType = CY_DMA_DESCR`), +// this ISR is called after each channel has been written. +static void NeoPixel_DMA_Complete(void) +{ + static BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + Cy_DMA_Channel_ClearInterrupt(DMA_NeoPixel_HW, DMA_NeoPixel_DW_CHANNEL); + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + +#define NEOPIXEL_N_DESCRIPTORS CONFIG_KTAG_N_NEOPIXEL_CHANNELS +static cy_stc_dma_descriptor_t NeoPixel_Descriptors[NEOPIXEL_N_DESCRIPTORS]; +static void NeoPixel_Configure_DMA(void) +{ + // I [AH] copied this structure from the PSoC Creator Component configuration + // in the generated source. + const cy_stc_dma_descriptor_config_t NeoPixel_DMA_Descriptor_Config = + { + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_1ELEMENT, + .channelState = CY_DMA_CHANNEL_ENABLED, + .triggerInType = CY_DMA_1ELEMENT, + .dataSize = CY_DMA_BYTE, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = NULL, + .dstAddress = NULL, + .srcXincrement = 1L, + .dstXincrement = 0L, + .xCount = 256UL, + .srcYincrement = 0L, + .dstYincrement = 0L, + .yCount = 1UL, + .nextDescriptor = NULL + }; + + for (uint_fast8_t i=0; i < NEOPIXEL_N_DESCRIPTORS; i++) + { + Cy_DMA_Descriptor_Init(&NeoPixel_Descriptors[i], &NeoPixel_DMA_Descriptor_Config); + Cy_DMA_Descriptor_SetSrcAddress(&NeoPixel_Descriptors[i], (uint8_t *)&NeoPixel_Frame_Buffers[i][0]); + Cy_DMA_Descriptor_SetDstAddress(&NeoPixel_Descriptors[i], (void *)&SPI_NeoPixel_HW->TX_FIFO_WR); + Cy_DMA_Descriptor_SetXloopDataCount(&NeoPixel_Descriptors[i], FRAME_BUFFER_SIZE); + } + + // Initialize and enable the interrupt from DMA_NeoPixel_HW. + Cy_SysInt_Init(&DMA_NeoPixel_Int_cfg, &NeoPixel_DMA_Complete); + NVIC_EnableIRQ(DMA_NeoPixel_Int_cfg.intrSrc); + Cy_DMA_Channel_SetInterruptMask(DMA_NeoPixel_HW, DMA_NeoPixel_DW_CHANNEL, DMA_NeoPixel_INTR_MASK); + + Cy_DMA_Enable(DMA_NeoPixel_HW); +} + +// Function: NeoPixel_Trigger_DMA +// This function sets up the channel... then enables it to dump the frameBuffer to pixels. +void NeoPixel_Trigger_DMA(uint_fast8_t channel) +{ + cy_stc_dma_channel_config_t channel_config; + channel_config.descriptor = &NeoPixel_Descriptors[channel]; + channel_config.preemptable = DMA_NeoPixel_PREEMPTABLE; + channel_config.priority = DMA_NeoPixel_PRIORITY; + channel_config.enable = false; + Cy_DMA_Channel_Init(DMA_NeoPixel_HW, DMA_NeoPixel_DW_CHANNEL, &channel_config); + Cy_DMA_Channel_Enable(DMA_NeoPixel_HW, DMA_NeoPixel_DW_CHANNEL); +} + +//! Takes an 8-bit value representing a color level and turns it into a WS2812 bit code... +/*! + * ...where 1=110 and 0=011 + * One input byte turns into three output bytes of a uint32_t. + */ +uint32_t NeoPixel_ConvertTo3Code(uint8_t input) +{ + uint32_t rval=0; + for (uint_fast8_t i=0; i < 8; i++) + { + if (input % 2) + { + rval |= NEOPIXEL_ONE3; + } + else + { + rval |= NEOPIXEL_ZERO3; + } + rval = rval >> 3; + + input = input >> 1; + } + return rval; +} + +//! Takes a position and a three byte RGB value and updates the corresponding NeoPixel_Frame_Buffer with the correct nine bytes. +SystemKResult_T HW_NeoPixels_Set_RGB(NeoPixelsChannel_T channel, uint8_t position, uint8_t red, uint8_t green, uint8_t blue) +{ + typedef union { + uint8_t bytes[4]; + uint32_t word; + } NeoPixel_ColorByNumber; + + NeoPixel_ColorByNumber color; + ColorOrder_T order = ColorOrderByChannel[channel]; + + if (order == COLOR_ORDER_RGB) + { + color.word = NeoPixel_ConvertTo3Code(red); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+0+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+1+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+2+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(green); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+3+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+4+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+5+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(blue); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+6+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+7+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+8+NEOPIXEL_ZOFFSET] = color.bytes[0]; + } + else if (order == COLOR_ORDER_GRB) + { + color.word = NeoPixel_ConvertTo3Code(green); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+0+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+1+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+2+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(red); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+3+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+4+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+5+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(blue); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+6+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+7+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+8+NEOPIXEL_ZOFFSET] = color.bytes[0]; + } + else + { + // Color order is not handled--log this and use RGB. + { + static bool error_logged = false; + if (error_logged == false) + { + COMM_Console_Print_String("Color order "); + COMM_Console_Print_UInt8(order); + COMM_Console_Print_String(" not yet supported!"); + error_logged = true; + } + } + + color.word = NeoPixel_ConvertTo3Code(red); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+0+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+1+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+2+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(green); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+3+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+4+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+5+NEOPIXEL_ZOFFSET] = color.bytes[0]; + + color.word = NeoPixel_ConvertTo3Code(blue); + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+6+NEOPIXEL_ZOFFSET] = color.bytes[2]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+7+NEOPIXEL_ZOFFSET] = color.bytes[1]; + NeoPixel_Frame_Buffers[channel][position*NEOPIXEL_BYTES_PER_PIXEL+8+NEOPIXEL_ZOFFSET] = color.bytes[0]; + } + + return SYSTEMK_RESULT_SUCCESS; +} + + +//! Initializes the hardware. +SystemKResult_T HW_NeoPixels_Init(void) +{ + Cy_SCB_SPI_Init(SPI_NeoPixel_HW, &SPI_NeoPixel_config, &SPI_NeoPixel_context); + Cy_SCB_SPI_Enable(SPI_NeoPixel_HW); + NeoPixel_Configure_DMA(); + +#if (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 1) + ColorOrderByChannel[NEOPIXEL_CHANNEL_BARREL] = NVM_BARREL_COLOR_ORDER; +#elif (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 4) + ColorOrderByChannel[NEOPIXEL_CHANNEL_BARREL] = NVM_BARREL_COLOR_ORDER; + ColorOrderByChannel[NEOPIXEL_CHANNEL_RECEIVER] = NVM_RECEIVER_COLOR_ORDER; + ColorOrderByChannel[NEOPIXEL_CHANNEL_DISPLAY] = NVM_DISPLAY_COLOR_ORDER; + ColorOrderByChannel[NEOPIXEL_CHANNEL_EFFECTS] = NVM_EFFECTS_COLOR_ORDER; +#else + #error "Unsupported number of NeoPixel channels defined. Supported configurations are 1 and 4." +#endif + + return SYSTEMK_RESULT_SUCCESS; +} + + +#if (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 1) +static inline __attribute__((always_inline)) void NeoPixels_Set_Color_On_All_Channels(uint8_t position, color_t color) +{ + HW_NeoPixels_Set_RGB(NEOPIXEL_CHANNEL_BARREL, position, Gamma8[Red(color)], Gamma8[Green(color)], Gamma8[Blue(color)]); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_All_Channels() +{ + // Nothing to do. +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Channel(uint_fast8_t __attribute__ ((unused)) channel) +{ + // Nothing to do. +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Channel(uint_fast8_t __attribute__ ((unused)) channel) +{ + // Nothing to do. +} +#elif (CONFIG_KTAG_N_NEOPIXEL_CHANNELS == 4) + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Barrel_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_0_PORT, Pin_NeoPixel_Select_0_NUM, 1); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Barrel_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_0_PORT, Pin_NeoPixel_Select_0_NUM, 0); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Receiver_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_1_PORT, Pin_NeoPixel_Select_1_NUM, 1); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Receiver_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_1_PORT, Pin_NeoPixel_Select_1_NUM, 0); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Display_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_2_PORT, Pin_NeoPixel_Select_2_NUM, 1); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Display_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_2_PORT, Pin_NeoPixel_Select_2_NUM, 0); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Effects_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_3_PORT, Pin_NeoPixel_Select_3_NUM, 1); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Effects_Channel() +{ + Cy_GPIO_Write(Pin_NeoPixel_Select_3_PORT, Pin_NeoPixel_Select_3_NUM, 0); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_All_Channels() +{ + NeoPixel_Enable_Barrel_Channel(); + NeoPixel_Enable_Receiver_Channel(); + NeoPixel_Enable_Display_Channel(); + NeoPixel_Enable_Effects_Channel(); +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_All_Channels() +{ + NeoPixel_Disable_Barrel_Channel(); + NeoPixel_Disable_Receiver_Channel(); + NeoPixel_Disable_Display_Channel(); + NeoPixel_Disable_Effects_Channel(); +} + +static inline __attribute__((always_inline)) void NeoPixel_Enable_Channel(uint_fast8_t channel) +{ + switch (channel) + { + case NEOPIXEL_CHANNEL_BARREL: + NeoPixel_Enable_Barrel_Channel(); + break; + + case NEOPIXEL_CHANNEL_RECEIVER: + NeoPixel_Enable_Receiver_Channel(); + break; + + case NEOPIXEL_CHANNEL_DISPLAY: + NeoPixel_Enable_Display_Channel(); + break; + + case NEOPIXEL_CHANNEL_EFFECTS: + NeoPixel_Enable_Effects_Channel(); + break; + + default: + // Do nothing. + break; + } +} + +static inline __attribute__((always_inline)) void NeoPixel_Disable_Channel(uint_fast8_t channel) +{ + switch (channel) + { + case NEOPIXEL_CHANNEL_BARREL: + NeoPixel_Disable_Barrel_Channel(); + break; + + case NEOPIXEL_CHANNEL_RECEIVER: + NeoPixel_Disable_Receiver_Channel(); + break; + + case NEOPIXEL_CHANNEL_DISPLAY: + NeoPixel_Disable_Display_Channel(); + break; + + case NEOPIXEL_CHANNEL_EFFECTS: + NeoPixel_Disable_Effects_Channel(); + break; + + default: + // Do nothing. + break; + } +} +#else + #error "Unsupported number of NeoPixel channels defined. Supported configurations are 1 and 4." +#endif + +SystemKResult_T HW_NeoPixels_Publish(void) +{ + // Update the NeoPixels using DMA. + for (uint_fast8_t Current_NeoPixel_Channel = 0; Current_NeoPixel_Channel < CONFIG_KTAG_N_NEOPIXEL_CHANNELS; Current_NeoPixel_Channel++) + { + xSemaphoreTake(NeoPixels_Semaphore, portMAX_DELAY); + NeoPixel_Enable_Channel(Current_NeoPixel_Channel); + NeoPixel_Trigger_DMA(Current_NeoPixel_Channel); + // Allow time for the DMA transfer to go out on the wire. + vTaskDelay(portTICK_PERIOD_MS); + NeoPixel_Disable_Channel(Current_NeoPixel_Channel); + xSemaphoreGive(NeoPixels_Semaphore); + } + + return SYSTEMK_RESULT_SUCCESS; +} + +//! \todo Refactor this somehow...it doesn't belong here. +color_t HW_NeoPixels_Get_My_Color(void) +{ + return PROTOCOLS_GetColor(GetWeaponFromID(NVM_WEAPON_ID).Protocol, NVM_TEAM_ID, NVM_PLAYER_ID); +} diff --git a/2020TPCAppNoDFU.cydsn/KTag.h b/2020TPCAppNoDFU.cydsn/KTag.h new file mode 100644 index 0000000..8bbe992 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/KTag.h @@ -0,0 +1,81 @@ +/** \file + * \brief This is the top-level include file for the entire project. + * + * By including this file (and only this file), include dependency order is maintained. + * + */ + +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKky+.`/ykKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKds/. -+o:` ./sdNKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKNds+-` `-+hNKKKKNho:` `-+shNKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKNkhyo+:. `-/sdNKKKKKKKKKKKKKky+:` .-/oyhdNKKKKKKKKKK +// KKys++:-.````.-:+oykNKKKKKKKKKKKKKKKKKKKKKKNkhs+/-.````.-:/+syKK +// KK -/+osydkNNNKKKkkkkkkkNKKKKKKKKKKKkkkkkkkkNKKKKNNkdhyso/: KK +// KK sKKKKKKKKKKKKK```````/KKKKKKKKKd-```````:kKKKKKKKKKKKKKd `KK +// KK- oKKKKKKKKKKKKK :KKKKKKKKo` `oNKKKKKKKKKKKKKKh :KK +// KK/ +KKKKKKKKKKKKK :KKKKKKd- -dKKKKKKKKKKKKKKKKy /KK +// KK+ /KKKKKKKKKKKKK :KKKKKs` +NKKKKKKKKKKKKKKKKKs +KK +// KKo :KKKKKKKKKKKKK :KKKk: .hKKKKKKKKKKKKKKKKKKKo oKK +// KKy -KKKKKKKKKKKKK :KKy` +NKKKKKKKKKKKKKKKKKKKK/ yKK +// KKd `KKKKKKKKKKKKK :k/ .hKKKKKKKKKKKKKKKKKKKKKK: dKK +// KKN NKKKKKKKKKKKK .. /kKKKKKKKKKKKKKKKKKKKKKKK. NKK +// KKK. dKKKKKKKKKKKK .yKKKKKKKKKKKKKKKKKKKKKKKKN .KKK +// KKK+ oKKKKKKKKKKKK -kKKKKKKKKKKKKKKKKKKKKKKKKKh +KKK +// KKKd .KKKKKKKKKKKK `sNKKKKKKKKKKKKKKKKKKKKKKKK/ dKKK +// KKKK: hKKKKKKKKKKK :kKKKKKKKKKKKKKKKKKKKKKKk :KKKK +// KKKKh -KKKKKKKKKKK `` .yKKKKKKKKKKKKKKKKKKKKK+ hKKKK +// KKKKK/ yKKKKKKKKKK T :d: /kKKKKKKKKKKKKKKKKKKk`:KKKKK +// KKKKKk`.NKKKKKKKKK :KNo` .hKKKKKKKKKKKKKKKKK:`kKKKKK +// KKKKKKy /KKKKKKKKK A :KKKd- +NKKKKKKKKKKKKKKo yKKKKKK +// KKKKKKK+ oKKKKKKKK :KKKKN+` -hKKKKKKKKKKKKy`+KKKKKKK +// KKKKKKKN/ sKKKKKKK G :KKKKKKh. `oNKKKKKKKKKh`/KKKKKKKK +// KKKKKKKKN/`sKKKKKK :KKKKKKKN/ -dKKKKKKKh`/NKKKKKKKK +// KKKKKKKKKK+ +NKKKK :KKKKKKKKKy. `sNKKKKs`+KKKKKKKKKK +// KKKKKKKKKKKs`:kKKK-------+KKKKKKKKKKk/--------oKKN+`sKKKKKKKKKKK +// KKKKKKKKKKKKh..yKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKd--dKKKKKKKKKKKK +// KKKKKKKKKKKKKN+`/kKKKKKKKKKKKKKKKKKKKKKKKKKKKKNo`+NKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKh-`sNKKKKKKKKKKKKKKKKKKKKKKKKNy.-hKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKs..sNKKKKKKKKKKKKKKKKKKKKNy-.yKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKNs..okKKKKKKKKKKKKKKKKNs-.sNKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKy-`/hKKKKKKKKKKKKd+`-yKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKd/`.odKKKKKKks-`/dKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKNs: .+yy+-`:sNKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKNy/..+yNKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK +// KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK + + +#ifndef KTAG_H +#define KTAG_H + +/* Include FreeRTOS APIs and defines */ +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" +#include "semphr.h" +#include "portmacro.h" +#include "timers.h" + +/* Include PSoC system and component APIs and defines */ +#include + +#include +#include +#include +#include + +#include "CONFIG.h" +#include "SystemK.h" +#include "HW.h" +#include "Audio.h" +#include "NVM.h" +#include "COMM.h" +#include "Fire_Control.h" +#include "Sample_Tasks.h" +#include "Tag_Sensors.h" +#include "Switches.h" +#include "Util.h" + +#endif // KTAG_H diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM.h b/2020TPCAppNoDFU.cydsn/NVM/NVM.h new file mode 100644 index 0000000..ffd8cad --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM.h @@ -0,0 +1,105 @@ +/** \dir NVM + * + * \brief Non-Volatile Memory + * + * This directory/namespace contains all the software used to manage non-volatile memory for this CPU. + * + */ + +/** \file + * \brief This file defines the interface to the NVM package. + * + * This file should be included by any file outside the NVM package wishing to make use + * of any of the NVM functionality. + */ + +#ifndef NVM_H +#define NVM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +//! Enumeration of the various states of a nonvolatile memory entry. +typedef enum +{ + //! This entry has not yet been initialized. + NVM_STATE_UNINITIALIZED = 0, + + //! This entry has been read from nonvolatile memory, and the cyclic redundancy check failed. + NVM_STATE_CRC_FAILED, + + //! No changes are pending for this entry. + NVM_STATE_IDLE, + + //! A request has been made to save this entry to NVM. + NVM_STATE_SAVE_REQUESTED +} NVM_Entry_State_T; + + +typedef struct +{ + // Size of the NVM data. + const size_t Size; + + // Address of the NVM data in the EEPROM memory. + const uint16_t EE_Address; + + // Address of the calculated CRC value in the EEPROM memory. + const uint16_t EE_CRC_Address; + + // Address of the NVM data in RAM. + uint8_t * const Value; + + // Address of the default data in ROM. + uint8_t const * const Default; + + // Current state of this NVM entry + NVM_Entry_State_T State; + +} NVM_EEPROMEntry_T; + + +/* Include Files */ +#include "NVM_CRC.h" + +#if (CONFIG__HAS_EXTERNAL_NVM) +#include "NVM_ExternalEEPROM.h" +#include "NVM_ExternalEEPROMEntries.h" +#endif // CONFIG__HAS_EXTERNAL_NVM + +#if (CONFIG__HAS_INTERNAL_NVM) +#include "NVM_OnChipEEPROM.h" +#include "NVM_OnChipEEPROMEntries.h" +#endif // CONFIG__HAS_INTERNAL_NVM + +/* Public Variables */ + +/* Public Functions */ + +inline bool IsNVMInitialized() +{ + taskENTER_CRITICAL(); + bool is_initialized = + +#if (CONFIG__HAS_EXTERNAL_NVM) + NVM_IsExternalEEPROMInitialized && +#endif // CONFIG__HAS_EXTERNAL_NVM + +#if (CONFIG__HAS_INTERNAL_NVM) + NVM_IsOnChipEEPROMInitialized && +#endif // CONFIG__HAS_INTERNAL_NVM + + true; + taskEXIT_CRITICAL(); + + return is_initialized; +} + +#ifdef __cplusplus +} +#endif + +#endif // NVM_H \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_CRC.c b/2020TPCAppNoDFU.cydsn/NVM/NVM_CRC.c new file mode 100644 index 0000000..09a9026 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_CRC.c @@ -0,0 +1,72 @@ +/** + * \file + * Functions and types for CRC checks. + * + * Generated on Sat Jun 15 14:34:15 2019 + * by pycrc v0.9.2, https://pycrc.org + * using the configuration: + * - Width = 16 + * - Poly = 0xed2f + * - XorIn = 0xbeef + * - ReflectIn = False + * - XorOut = 0x0000 + * - ReflectOut = False + * - Algorithm = table-driven + */ +#include "NVM_CRC.h" /* include the header file generated with pycrc */ +#include +#include + + + +/** + * Static table used for the table_driven implementation. + */ +static const NVM_CRC_t crc_table[256] = { + 0x0000, 0xed2f, 0x3771, 0xda5e, 0x6ee2, 0x83cd, 0x5993, 0xb4bc, + 0xddc4, 0x30eb, 0xeab5, 0x079a, 0xb326, 0x5e09, 0x8457, 0x6978, + 0x56a7, 0xbb88, 0x61d6, 0x8cf9, 0x3845, 0xd56a, 0x0f34, 0xe21b, + 0x8b63, 0x664c, 0xbc12, 0x513d, 0xe581, 0x08ae, 0xd2f0, 0x3fdf, + 0xad4e, 0x4061, 0x9a3f, 0x7710, 0xc3ac, 0x2e83, 0xf4dd, 0x19f2, + 0x708a, 0x9da5, 0x47fb, 0xaad4, 0x1e68, 0xf347, 0x2919, 0xc436, + 0xfbe9, 0x16c6, 0xcc98, 0x21b7, 0x950b, 0x7824, 0xa27a, 0x4f55, + 0x262d, 0xcb02, 0x115c, 0xfc73, 0x48cf, 0xa5e0, 0x7fbe, 0x9291, + 0xb7b3, 0x5a9c, 0x80c2, 0x6ded, 0xd951, 0x347e, 0xee20, 0x030f, + 0x6a77, 0x8758, 0x5d06, 0xb029, 0x0495, 0xe9ba, 0x33e4, 0xdecb, + 0xe114, 0x0c3b, 0xd665, 0x3b4a, 0x8ff6, 0x62d9, 0xb887, 0x55a8, + 0x3cd0, 0xd1ff, 0x0ba1, 0xe68e, 0x5232, 0xbf1d, 0x6543, 0x886c, + 0x1afd, 0xf7d2, 0x2d8c, 0xc0a3, 0x741f, 0x9930, 0x436e, 0xae41, + 0xc739, 0x2a16, 0xf048, 0x1d67, 0xa9db, 0x44f4, 0x9eaa, 0x7385, + 0x4c5a, 0xa175, 0x7b2b, 0x9604, 0x22b8, 0xcf97, 0x15c9, 0xf8e6, + 0x919e, 0x7cb1, 0xa6ef, 0x4bc0, 0xff7c, 0x1253, 0xc80d, 0x2522, + 0x8249, 0x6f66, 0xb538, 0x5817, 0xecab, 0x0184, 0xdbda, 0x36f5, + 0x5f8d, 0xb2a2, 0x68fc, 0x85d3, 0x316f, 0xdc40, 0x061e, 0xeb31, + 0xd4ee, 0x39c1, 0xe39f, 0x0eb0, 0xba0c, 0x5723, 0x8d7d, 0x6052, + 0x092a, 0xe405, 0x3e5b, 0xd374, 0x67c8, 0x8ae7, 0x50b9, 0xbd96, + 0x2f07, 0xc228, 0x1876, 0xf559, 0x41e5, 0xacca, 0x7694, 0x9bbb, + 0xf2c3, 0x1fec, 0xc5b2, 0x289d, 0x9c21, 0x710e, 0xab50, 0x467f, + 0x79a0, 0x948f, 0x4ed1, 0xa3fe, 0x1742, 0xfa6d, 0x2033, 0xcd1c, + 0xa464, 0x494b, 0x9315, 0x7e3a, 0xca86, 0x27a9, 0xfdf7, 0x10d8, + 0x35fa, 0xd8d5, 0x028b, 0xefa4, 0x5b18, 0xb637, 0x6c69, 0x8146, + 0xe83e, 0x0511, 0xdf4f, 0x3260, 0x86dc, 0x6bf3, 0xb1ad, 0x5c82, + 0x635d, 0x8e72, 0x542c, 0xb903, 0x0dbf, 0xe090, 0x3ace, 0xd7e1, + 0xbe99, 0x53b6, 0x89e8, 0x64c7, 0xd07b, 0x3d54, 0xe70a, 0x0a25, + 0x98b4, 0x759b, 0xafc5, 0x42ea, 0xf656, 0x1b79, 0xc127, 0x2c08, + 0x4570, 0xa85f, 0x7201, 0x9f2e, 0x2b92, 0xc6bd, 0x1ce3, 0xf1cc, + 0xce13, 0x233c, 0xf962, 0x144d, 0xa0f1, 0x4dde, 0x9780, 0x7aaf, + 0x13d7, 0xfef8, 0x24a6, 0xc989, 0x7d35, 0x901a, 0x4a44, 0xa76b +}; + + +NVM_CRC_t NVM_CRC_update(NVM_CRC_t crc, const void *data, size_t data_len) +{ + const unsigned char *d = (const unsigned char *)data; + unsigned int tbl_idx; + + while (data_len--) { + tbl_idx = ((crc >> 8) ^ *d) & 0xff; + crc = (crc_table[tbl_idx] ^ (crc << 8)) & 0xffff; + d++; + } + return crc & 0xffff; +} \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_CRC.h b/2020TPCAppNoDFU.cydsn/NVM/NVM_CRC.h new file mode 100644 index 0000000..bbb2807 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_CRC.h @@ -0,0 +1,115 @@ +/** + * \file + * Functions and types for CRC checks. + * + * Generated on Sat Jun 15 14:34:05 2019 + * by pycrc v0.9.2, https://pycrc.org + * using the configuration: + * - Width = 16 + * - Poly = 0xed2f + * - XorIn = 0xbeef + * - ReflectIn = False + * - XorOut = 0x0000 + * - ReflectOut = False + * - Algorithm = table-driven + * + * This file defines the functions NVM_CRC_init(), NVM_CRC_update() and NVM_CRC_finalize(). + * + * The NVM_CRC_init() function returns the inital \c crc value and must be called + * before the first call to NVM_CRC_update(). + * Similarly, the NVM_CRC_finalize() function must be called after the last call + * to NVM_CRC_update(), before the \c crc is being used. + * is being used. + * + * The NVM_CRC_update() function can be called any number of times (including zero + * times) in between the NVM_CRC_init() and NVM_CRC_finalize() calls. + * + * This pseudo-code shows an example usage of the API: + * \code{.c} + * NVM_CRC_t crc; + * unsigned char data[MAX_DATA_LEN]; + * size_t data_len; + * + * crc = NVM_CRC_init(); + * while ((data_len = read_data(data, MAX_DATA_LEN)) > 0) { + * crc = NVM_CRC_update(crc, data, data_len); + * } + * crc = NVM_CRC_finalize(crc); + * \endcode + * + * ## Additional Notes + * + * The CRC polynomial (0xED2F) was chosen based on the research published by Philip Koopman of Carnegie Mellon + * University [here](http://users.ece.cmu.edu/~koopman/crc/). Dr. Koopman claims this polynomial has a + * Hamming Distance of 10. + * + * The initial value, 0xBEEF, was chosen simply to avoid the most common EE values of 0xFFFF and 0x0000. + * + */ +#ifndef NVM_CRC_H +#define NVM_CRC_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * The definition of the used algorithm. + * + * This is not used anywhere in the generated code, but it may be used by the + * application code to call algorithm-specific code, if desired. + */ +#define CRC_ALGO_TABLE_DRIVEN 1 + + +/** + * The type of the CRC values. + * + * CRCs are sixteen bits wide. + */ +typedef uint16_t NVM_CRC_t; + + +/** + * Calculate the initial crc value. + * + * \return The initial crc value. + */ +static inline NVM_CRC_t NVM_CRC_init(void) +{ + return 0xbeef; +} + + +/** + * Update the crc value with new data. + * + * \param[in] crc The current crc value. + * \param[in] data Pointer to a buffer of \a data_len bytes. + * \param[in] data_len Number of bytes in the \a data buffer. + * \return The updated crc value. + */ +NVM_CRC_t NVM_CRC_update(NVM_CRC_t crc, const void *data, size_t data_len); + + +/** + * Calculate the final crc value. + * + * \param[in] crc The current crc value. + * \return The final crc value. + */ +static inline NVM_CRC_t NVM_CRC_finalize(NVM_CRC_t crc) +{ + return crc; +} + + +#ifdef __cplusplus +} /* closing brace for extern "C" */ +#endif + +#endif /* NVM_CRC_H */ \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROM.c b/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROM.c new file mode 100644 index 0000000..84cf845 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROM.c @@ -0,0 +1,302 @@ +/** \file + * \brief This file contains functions that manage the external EEPROM. + * + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +//! This is the same for both the MCP98243 and the CAT24C256. +#define EXTERNAL_EEPROM_I2C_ADDRESS 0x50 +#define EXTERNAL_EEPROM_TEMP_SENSOR_I2C_ADDRESS 0x18 + +//! Read-only register used to identify the temperature sensor capability. +#define MCP98243_REGISTER_CAPABILITY 0x00 +//! Sensor configuration register. +#define MCP98243_REGISTER_CONFIG 0x01 +//! Upper temperature limit register. +#define MCP98243_REGISTER_T_UPPER 0x02 +//! Lower temperature limit register. +#define MCP98243_REGISTER_T_LOWER 0x03 +//! Critical temperature limit register. +#define MCP98243_REGISTER_T_CRIT 0x04 +//! Ambient temperature register. +#define MCP98243_REGISTER_T_A 0x05 +//! Read-only register used to identify the manufacturer of the device. +#define MCP98243_REGISTER_MANUFACTURER_ID 0x06 +//! Read-only register indicating the device identification and device revision. +#define MCP98243_REGISTER_DEVICE_ID 0x07 +//! Temperature sensor resolution register. +#define MCP98243_REGISTER_RESOLUTION 0x08 + + +/* External Variables [Only if necessary!] */ + +/* External Function Prototypes [Only if necessary!] */ + +/* Public Variables */ + +//! Mutex controlling access to the EEPROM to ensure data/CRC integrity. +SemaphoreHandle_t xSemaphoreExternalEEPROMLock; + +TaskHandle_t NVM_ExternalEEPROM_Task_Handle; + +volatile bool NVM_IsExternalEEPROMInitialized = false; + +/* Private Variables */ + +static QueueHandle_t xQueueExternalEEPROM; + +//! Shared master transfer configuration variable. +static cy_stc_scb_i2c_master_xfer_config_t Master_Transfer_Config = +{ + .slaveAddress = EXTERNAL_EEPROM_I2C_ADDRESS, + .buffer = NULL, + .bufferSize = 0U, + .xferPending = false +}; + + +/* Private Function Prototypes */ + +/* Inline Functions */ + +//! Waits a given time for an I²C transfer to complete. +/*! + * \param timeout_in_ms The time (in milliseconds) to wait for the transfer to complete. + * \return #true if the transfer completed, or #false if the time ran out without + * a successful transfer. + */ +static inline bool Wait_For_Transfer_To_Complete(uint16_t timeout_in_ms) +{ + bool success = false; + + // Time to wait for an in-process transfer before looking again. This wait grows longer as time + // passes, until timeout_in_ms runs out. + uint16_t HOLDOFF_TIME_IN_ms = 1; + + while ((success == false) && (timeout_in_ms > 0)) + { + vTaskDelay(pdMS_TO_TICKS(HOLDOFF_TIME_IN_ms)); + + if (timeout_in_ms > HOLDOFF_TIME_IN_ms) + { + timeout_in_ms -= HOLDOFF_TIME_IN_ms; + + // Wait a little longer next time. + HOLDOFF_TIME_IN_ms++; + } + else + { + timeout_in_ms = 0; + } + + if ((I2C_MasterGetStatus() & CY_SCB_I2C_MASTER_BUSY) != CY_SCB_I2C_MASTER_BUSY) + { + success = true; + } + } + + return success; +} + +//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination. +static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n) +{ + uint8_t xfer_buffer[5]; + + if (xSemaphoreTake(COMM_I2C_Bus_Mutex, portMAX_DELAY) == pdTRUE) + { + // Write the initial address to the EEPROM. + xfer_buffer[0] = (source >> 8); + xfer_buffer[1] = source & 0xFF; + + Master_Transfer_Config.buffer = (uint8_t *)xfer_buffer; + Master_Transfer_Config.bufferSize = 2; + + cy_en_scb_i2c_status_t errStatus = I2C_MasterWrite(&Master_Transfer_Config); + + if (errStatus == CY_SCB_I2C_SUCCESS) + { + (void) Wait_For_Transfer_To_Complete(100); + } + else + { + // What? + } + + // Read n bytes at EEPROM[source]. + Master_Transfer_Config.buffer = (uint8_t *)destination; + Master_Transfer_Config.bufferSize = n; + + errStatus = I2C_MasterRead(&Master_Transfer_Config); + + if (errStatus == CY_SCB_I2C_SUCCESS) + { + (void) Wait_For_Transfer_To_Complete(100); + } + else + { + // What? + } + + xSemaphoreGive(COMM_I2C_Bus_Mutex); + } +} + +//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination. +static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n) +{ + uint8_t xfer_buffer[4]; + + if (xSemaphoreTake(COMM_I2C_Bus_Mutex, portMAX_DELAY) == pdTRUE) + { + // Write the data one byte at a time. + for (uint8_t i = 0; i < n; i++) + { + uint16_t destination_address = destination + i; + xfer_buffer[0] = (destination_address >> 8); + xfer_buffer[1] = destination_address & 0xFF; + xfer_buffer[2] = *(source + i); + + Master_Transfer_Config.buffer = (uint8_t *)xfer_buffer; + Master_Transfer_Config.bufferSize = 3; + + cy_en_scb_i2c_status_t errStatus = I2C_MasterWrite(&Master_Transfer_Config); + + if (errStatus == CY_SCB_I2C_SUCCESS) + { + (void) Wait_For_Transfer_To_Complete(100); + } + else + { + // What? + } + + // The CAT24C256 has a nominal Write Cycle time (t_WR) of 5ms (no maximum specified). + // Wait 6ms between writes to have some margin (and avoid being NAKed). + vTaskDelay(pdMS_TO_TICKS(6)); + } + + xSemaphoreGive(COMM_I2C_Bus_Mutex); + } +} + + +/* Public Functions */ + +//! Sets up the external EEPROM, but does not read from it (yet). +void NVM_InitExternalEEPROM(void) +{ + /// Create a mutex-type semaphore. + xSemaphoreExternalEEPROMLock = xSemaphoreCreateMutex(); + + if (xSemaphoreExternalEEPROMLock == NULL) + { + CY_ASSERT(0); + } + + xQueueExternalEEPROM = xQueueCreate(5, sizeof(uint8_t)); +} + +//! Handles the ongoing external EEPROM tasks. +/*! + * First, it loops through all the external EEPROM entries, and reads them in to RAM. + * Then, it priodically loops through all the external EEPROM entries, and saves the ones that have been flagged. + */ +void NVM_ExternalEEPROMTask(void * pvParameters) +{ + portBASE_TYPE xStatus; + static TickType_t xTicksToWait = pdMS_TO_TICKS(NVM_EXTERNAL_EEPROM_TASK_RATE_IN_ms); + + for (uint8_t i = 0; i < NVM_N_EXTERNAL_EEPROM_ENTRIES; i++) + { + NVM_CRC_t calculated_crc; + NVM_CRC_t stored_crc = 0; + + EEPROM_read_block(NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->EE_Address, NVM_ExternalEEPROMEntries[i]->Size); + EEPROM_read_block((uint8_t *)&stored_crc, NVM_ExternalEEPROMEntries[i]->EE_CRC_Address, sizeof(NVM_CRC_t)); + + calculated_crc = NVM_CRC_init(); + calculated_crc = NVM_CRC_update(calculated_crc, NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->Size); + calculated_crc = NVM_CRC_finalize(calculated_crc); + + if (calculated_crc == stored_crc) + { + NVM_ExternalEEPROMEntries[i]->State = NVM_STATE_IDLE; + } + else + { + NVM_ExternalEEPROMEntries[i]->State = NVM_STATE_CRC_FAILED; + + COMM_Console_Print_String("[NVMEx "); + COMM_Console_Print_UInt16((uint16_t) i); + COMM_Console_Print_String("] Calculated/Stored CRCs: "); + COMM_Console_Print_UInt16((uint16_t) calculated_crc); + COMM_Console_Print_String("/"); + COMM_Console_Print_UInt16((uint16_t) stored_crc); + COMM_Console_Print_String("\n"); + + COMM_Console_Print_String("[NVMEx "); + COMM_Console_Print_UInt16((uint16_t) i); + COMM_Console_Print_String("] Applying defaults.\n"); + + memcpy(NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->Default, NVM_ExternalEEPROMEntries[i]->Size); + + // Auto-fix the CRC. + NVM_SaveExternalEEPROMEntry(NVM_ExternalEEPROMEntries[i]); + } + } + + taskENTER_CRITICAL(); + NVM_IsExternalEEPROMInitialized = true; + taskEXIT_CRITICAL(); + + while(true) + { + uint8_t dummy; + + // Wait for a call to NVM_SaveExternalEEPROMEntry(). + xStatus = xQueueReceive(xQueueExternalEEPROM, &dummy, xTicksToWait); + + if (xStatus == pdPASS) + { + for (uint8_t i = 0; i < NVM_N_EXTERNAL_EEPROM_ENTRIES; i++) + { + NVM_CRC_t crc; + + if (NVM_ExternalEEPROMEntries[i]->State == NVM_STATE_SAVE_REQUESTED) + { + if (xSemaphoreTake(xSemaphoreExternalEEPROMLock, portMAX_DELAY) == pdTRUE) + { + EEPROM_write_block(NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->EE_Address, NVM_ExternalEEPROMEntries[i]->Size); + + // Calculate the CRC. + crc = NVM_CRC_init(); + crc = NVM_CRC_update(crc, NVM_ExternalEEPROMEntries[i]->Value, NVM_ExternalEEPROMEntries[i]->Size); + crc = NVM_CRC_finalize(crc); + EEPROM_write_block((uint8_t *)&crc, NVM_ExternalEEPROMEntries[i]->EE_CRC_Address, sizeof(uint16_t)); + NVM_ExternalEEPROMEntries[i]->State = NVM_STATE_IDLE; + xSemaphoreGive(xSemaphoreExternalEEPROMLock); + } + } + } + } + } +} + +//! Flags the given external EEPROM entry to be saved next time the NVM_ExternalEEPROMTask() is run. +void NVM_SaveExternalEEPROMEntry(NVM_EEPROMEntry_T * const this) +{ + if (xSemaphoreTake(xSemaphoreExternalEEPROMLock, portMAX_DELAY) == pdTRUE) + { + this->State = NVM_STATE_SAVE_REQUESTED; + xSemaphoreGive(xSemaphoreExternalEEPROMLock); + uint8_t dummy = 0; + xQueueSend(xQueueExternalEEPROM, &dummy, 0); + } +} + +/* Private Functions */ diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROM.h b/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROM.h new file mode 100644 index 0000000..afa7440 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROM.h @@ -0,0 +1,44 @@ +/** \file + * \brief This file contains the public interface to the external EEPROM. + * + * On the 2020TPC, the external EEPROM is the Onsemi [CAT24C256](https://www.onsemi.com/pdf/datasheet/cat24c256-d.pdf). + * + */ + +#ifndef NVM_EXTERNALEEPROM_H +#define NVM_EXTERNALEEPROM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +#define NVM_EXTERNAL_EEPROM_TASK_STACK_SIZE_in_bytes 256 + +//! The time between calls to NVM_ExternalEEPROMTask(). +#define NVM_EXTERNAL_EEPROM_TASK_RATE_IN_ms 2000 + +/* Include Files */ + +/* Public Variables */ + +extern SemaphoreHandle_t xSemaphoreExternalEEPROMLock; + +//! Handle of the NVM_ExternalEEPROMTask() given when the task was created. +extern TaskHandle_t NVM_ExternalEEPROM_Task_Handle; + +extern volatile bool NVM_IsExternalEEPROMInitialized; + +/* Public Functions */ +void NVM_InitExternalEEPROM(void); +void NVM_ExternalEEPROMTask(void * pvParameters); +void NVM_SaveExternalEEPROMEntry(NVM_EEPROMEntry_T * const this); + +/* Inline Functions */ + +#ifdef __cplusplus +} +#endif + +#endif // NVM_EXTERNALEEPROM_H diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROMEntries.c b/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROMEntries.c new file mode 100644 index 0000000..832da53 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROMEntries.c @@ -0,0 +1,153 @@ +/* + * __ ________ _____ ______ __ + * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ + * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ + * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ + * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ + * /____/ + * + * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞 + * + */ + +/** \file + * \brief [Autogenerated] This file defines the External EEPROM entries. + * + * \note AUTOGENERATED: This file was generated automatically on Friday, April 28, 2023 at 11:31:31 AM. + * DO NOT MODIFY THIS FILE MANUALLY! + */ + +/* Include Files */ +#include "KTag.h" + +/* EEPROM Entries */ + +/** \defgroup NVM_EXTERNAL_EEPROM NVM External EEPROM + * + * The External EEPROM is divided into logical "entries", represented by instances of the #NVM_EEPROMEntry_T type. + * At startup, these entries are loaded into their respective RAM copies by NVM_InitExternalEEPROM(). The application + * then updates the RAM copies directly, and requests that the NVM_ExternalEEPROMTask() save these back to the EEPROM + * when necessary. + * @{ */ + +static NVM_External_Test_T RAM_External_Test; + +static const NVM_External_Test_T DEFAULT_External_Test = +{ + //! Test Code 3 + .External_Test_3 = UINT16_MAX, + //! Test Code 4 + .External_Test_4 = UINT32_MAX, +}; + +NVM_EEPROMEntry_T NVM_External_Test = +{ + //! Size == sizeof(NVM_External_Test_T) + .Size = 6, + .EE_Address = 0, + .EE_CRC_Address = 6, + .Value = (uint8_t *)&RAM_External_Test, + .Default = (uint8_t *)&DEFAULT_External_Test, + .State = NVM_STATE_UNINITIALIZED +}; +static NVM_Info_T RAM_Info; + +static const NVM_Info_T DEFAULT_Info = +{ + //! Date this unit was first programmed. + .Date_Code_as_YYYYMMDD = 20200101, +}; + +NVM_EEPROMEntry_T NVM_Info = +{ + //! Size == sizeof(NVM_Info_T) + .Size = 4, + .EE_Address = 8, + .EE_CRC_Address = 12, + .Value = (uint8_t *)&RAM_Info, + .Default = (uint8_t *)&DEFAULT_Info, + .State = NVM_STATE_UNINITIALIZED +}; +static NVM_Hardware_Settings_T RAM_Hardware_Settings; + +static const NVM_Hardware_Settings_T DEFAULT_Hardware_Settings = +{ + //! Color order for the barrel Neopixels. + .Barrel_Color_Order = 2, + //! Color order for the receiver NeoPixels. + .Receiver_Color_Order = 0, + //! Color order for the display NeoPixels. + .Display_Color_Order = 2, + //! Color order for the effects NeoPixels. + .Effects_Color_Order = 2, + //! true if this unit is configured for a right-handed person; false if for a left-handed person. + .Is_Right_Handed = true, + //! Audio volume. + .Volume = 20, +}; + +NVM_EEPROMEntry_T NVM_Hardware_Settings = +{ + //! Size == sizeof(NVM_Hardware_Settings_T) + .Size = 6, + .EE_Address = 14, + .EE_CRC_Address = 20, + .Value = (uint8_t *)&RAM_Hardware_Settings, + .Default = (uint8_t *)&DEFAULT_Hardware_Settings, + .State = NVM_STATE_UNINITIALIZED +}; +static NVM_Game_Settings_T RAM_Game_Settings; + +static const NVM_Game_Settings_T DEFAULT_Game_Settings = +{ + //! Selected weapon. + .Weapon_ID = LASER_X_ID, + //! Player identification (is this used?) + .Player_ID = 0, + //! Selected team. + .Team_ID = 1, +}; + +NVM_EEPROMEntry_T NVM_Game_Settings = +{ + //! Size == sizeof(NVM_Game_Settings_T) + .Size = 3, + .EE_Address = 22, + .EE_CRC_Address = 25, + .Value = (uint8_t *)&RAM_Game_Settings, + .Default = (uint8_t *)&DEFAULT_Game_Settings, + .State = NVM_STATE_UNINITIALIZED +}; +static NVM_Hourmeter_T RAM_Hourmeter; + +static const NVM_Hourmeter_T DEFAULT_Hourmeter = +{ + //! Total number of startups for this unit. + .Hourmeter_Startups = 0, +}; + +NVM_EEPROMEntry_T NVM_Hourmeter = +{ + //! Size == sizeof(NVM_Hourmeter_T) + .Size = 2, + .EE_Address = 27, + .EE_CRC_Address = 29, + .Value = (uint8_t *)&RAM_Hourmeter, + .Default = (uint8_t *)&DEFAULT_Hourmeter, + .State = NVM_STATE_UNINITIALIZED +}; + +/** @} */ + +NVM_EEPROMEntry_T * const NVM_ExternalEEPROMEntries[] = +{ + &NVM_External_Test, + &NVM_Info, + &NVM_Hardware_Settings, + &NVM_Game_Settings, + &NVM_Hourmeter, +}; + +//! Size of the #NVM_ExternalEEPROMEntries array (i.e. the number of External EEPROM entries). +const uint8_t NVM_N_EXTERNAL_EEPROM_ENTRIES = (uint8_t) (sizeof(NVM_ExternalEEPROMEntries) / sizeof(NVM_EEPROMEntry_T *)); + diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROMEntries.h b/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROMEntries.h new file mode 100644 index 0000000..61d7103 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_ExternalEEPROMEntries.h @@ -0,0 +1,135 @@ +/* + * __ ________ _____ ______ __ + * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ + * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ + * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ + * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ + * /____/ + * + * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞 + * + */ + +/** \file + * \brief [Autogenerated] This file declares the External EEPROM entries. + * + * \note AUTOGENERATED: This file was generated automatically on Friday, April 28, 2023 at 11:31:31 AM. + * DO NOT MODIFY THIS FILE MANUALLY! + */ + +#ifndef NVM_EXTERNALEEPROMENTRIES_H +#define NVM_EXTERNALEEPROMENTRIES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +typedef struct __attribute__((packed)) +{ + //! Test Code 3 + uint16_t External_Test_3; + //! Test Code 4 + uint32_t External_Test_4; +} NVM_External_Test_T; + +typedef struct __attribute__((packed)) +{ + //! Date this unit was first programmed. + uint32_t Date_Code_as_YYYYMMDD; +} NVM_Info_T; + +typedef struct __attribute__((packed)) +{ + //! Color order for the barrel Neopixels. + uint8_t Barrel_Color_Order; + //! Color order for the receiver NeoPixels. + uint8_t Receiver_Color_Order; + //! Color order for the display NeoPixels. + uint8_t Display_Color_Order; + //! Color order for the effects NeoPixels. + uint8_t Effects_Color_Order; + //! true if this unit is configured for a right-handed person; false if for a left-handed person. + bool Is_Right_Handed; + //! Audio volume. + uint8_t Volume; +} NVM_Hardware_Settings_T; + +typedef struct __attribute__((packed)) +{ + //! Selected weapon. + uint8_t Weapon_ID; + //! Player identification (is this used?) + uint8_t Player_ID; + //! Selected team. + uint8_t Team_ID; +} NVM_Game_Settings_T; + +typedef struct __attribute__((packed)) +{ + //! Total number of startups for this unit. + uint16_t Hourmeter_Startups; +} NVM_Hourmeter_T; + + +/* Include Files */ + +/* Public Variables */ + +extern NVM_EEPROMEntry_T NVM_External_Test; +extern NVM_EEPROMEntry_T NVM_Info; +extern NVM_EEPROMEntry_T NVM_Hardware_Settings; +extern NVM_EEPROMEntry_T NVM_Game_Settings; +extern NVM_EEPROMEntry_T NVM_Hourmeter; + +extern NVM_EEPROMEntry_T * const NVM_ExternalEEPROMEntries[]; +extern const uint8_t NVM_N_EXTERNAL_EEPROM_ENTRIES; + +// Shorthand macros, to save you time. +#define NVM_EXTERNAL_TEST_3 (((NVM_External_Test_T*)NVM_External_Test.Value)->External_Test_3) +#define NVM_EXTERNAL_TEST_3_ENTRY_PTR (&NVM_External_Test) + +#define NVM_EXTERNAL_TEST_4 (((NVM_External_Test_T*)NVM_External_Test.Value)->External_Test_4) +#define NVM_EXTERNAL_TEST_4_ENTRY_PTR (&NVM_External_Test) + +#define NVM_DATE_CODE_AS_YYYYMMDD (((NVM_Info_T*)NVM_Info.Value)->Date_Code_as_YYYYMMDD) +#define NVM_DATE_CODE_AS_YYYYMMDD_ENTRY_PTR (&NVM_Info) + +#define NVM_BARREL_COLOR_ORDER (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Barrel_Color_Order) +#define NVM_BARREL_COLOR_ORDER_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_RECEIVER_COLOR_ORDER (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Receiver_Color_Order) +#define NVM_RECEIVER_COLOR_ORDER_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_DISPLAY_COLOR_ORDER (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Display_Color_Order) +#define NVM_DISPLAY_COLOR_ORDER_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_EFFECTS_COLOR_ORDER (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Effects_Color_Order) +#define NVM_EFFECTS_COLOR_ORDER_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_IS_RIGHT_HANDED (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Is_Right_Handed) +#define NVM_IS_RIGHT_HANDED_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_VOLUME (((NVM_Hardware_Settings_T*)NVM_Hardware_Settings.Value)->Volume) +#define NVM_VOLUME_ENTRY_PTR (&NVM_Hardware_Settings) + +#define NVM_WEAPON_ID (((NVM_Game_Settings_T*)NVM_Game_Settings.Value)->Weapon_ID) +#define NVM_WEAPON_ID_ENTRY_PTR (&NVM_Game_Settings) + +#define NVM_PLAYER_ID (((NVM_Game_Settings_T*)NVM_Game_Settings.Value)->Player_ID) +#define NVM_PLAYER_ID_ENTRY_PTR (&NVM_Game_Settings) + +#define NVM_TEAM_ID (((NVM_Game_Settings_T*)NVM_Game_Settings.Value)->Team_ID) +#define NVM_TEAM_ID_ENTRY_PTR (&NVM_Game_Settings) + +#define NVM_HOURMETER_STARTUPS (((NVM_Hourmeter_T*)NVM_Hourmeter.Value)->Hourmeter_Startups) +#define NVM_HOURMETER_STARTUPS_ENTRY_PTR (&NVM_Hourmeter) + + +#ifdef __cplusplus +} +#endif + +#endif // NVM_EXTERNALEEPROMENTRIES_H + diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROM.c b/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROM.c new file mode 100644 index 0000000..5fd56b0 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROM.c @@ -0,0 +1,260 @@ +/** \file + * \brief This file contains functions that manage the on-chip EEPROM. + * + */ + +/* Include Files */ +#include "KTag.h" + +/* Local Definitions and Constants */ + +/* External Variables [Only if necessary!] */ + +/* External Function Prototypes [Only if necessary!] */ + +/* Public Variables */ + +//! Mutex controlling access to the EEPROM to ensure data/CRC integrity. +SemaphoreHandle_t xSemaphoreOnChipEEPROMLock; + +TaskHandle_t NVM_OnChipEEPROM_Task_Handle; + +volatile bool NVM_IsOnChipEEPROMInitialized = false; + +/* Private Variables */ + +static QueueHandle_t xQueueOnChipEEPROM; + +#if CY_PSOC4 +const uint8_t Emulated_EEPROM_Storage[On_Chip_Emulated_EEPROM_PHYSICAL_SIZE] +__ALIGNED(CY_FLASH_SIZEOF_ROW) = {0u}; +#endif // CY_PSOC4 + +/* Private Function Prototypes */ + +/* Inline Functions */ + +#if CY_PSOC4 +//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination. +static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n) +{ + On_Chip_Emulated_EEPROM_Read(source, destination, n); +} + +//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination. +static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n) +{ + On_Chip_Emulated_EEPROM_Write(destination, source, n); +} +#endif // CY_PSOC4 + +#if CY_PSOC5 +//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination. +static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n) +{ + for (uint_fast16_t i = 0; i < n; i++) + { + uint8_t temp = On_Chip_EEPROM_ReadByte(source + i); + *(destination + i) = temp; + } +} + +//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination. +static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n) +{ + for (uint_fast16_t i = 0; i < n; i++) + { + On_Chip_EEPROM_WriteByte(*(source + i), destination + i); + } +} +#endif // CY_PSOC5 + +#if CY_PSOC6 +//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination. +static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n) +{ + cy_en_em_eeprom_status_t result = On_Chip_EEPROM_Read(source, destination, n); + + if (result != CY_EM_EEPROM_SUCCESS) + { + CY_ASSERT(0); + } +} + +//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination. +static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n) +{ + cy_en_em_eeprom_status_t result = On_Chip_EEPROM_Write(destination, source, n); + + if (result != CY_EM_EEPROM_SUCCESS) + { + CY_ASSERT(0); + } +} +#endif // CY_PSOC6 + +/* Public Functions */ + +//! Sets up the on-chip EEPROM, but does not read from it (yet). +void NVM_InitOnChipEEPROM(void) +{ + /// Create a mutex-type semaphore. + xSemaphoreOnChipEEPROMLock = xSemaphoreCreateMutex(); + + if (xSemaphoreOnChipEEPROMLock == NULL) + { + CY_ASSERT(0); + } + + xQueueOnChipEEPROM = xQueueCreate(5, sizeof(uint8_t)); + +#if CY_PSOC4 + On_Chip_Emulated_EEPROM_Init((uint32_t)Emulated_EEPROM_Storage); +#endif // CY_PSOC4 + +#if CY_PSOC5 + On_Chip_EEPROM_Start(); +#endif // CY_PSOC5 + +#if CY_PSOC6 + // From the docs: "For PSoC 6, if Emulated EEPROM is selected for EEPROM storage, the start address will be + // overwritten to some address from Emulated EEPROM flash area." + On_Chip_EEPROM_Init(0); +#endif // CY_PSOC6 +} + +//! Handles the ongoing on-chip EEPROM tasks. +/*! + * First, it loops through all the on-chip EEPROM entries, and reads them in to RAM. + * Then, it priodically loops through all the on-chip EEPROM entries, and saves the ones that have been flagged. + */ +void NVM_OnChipEEPROMTask(void * pvParameters) +{ + portBASE_TYPE xStatus; + static TickType_t xTicksToWait = pdMS_TO_TICKS(NVM_ON_CHIP_EEPROM_TASK_RATE_IN_ms); + + for (uint8_t i = 0; i < NVM_N_ONCHIP_EEPROM_ENTRIES; i++) + { + NVM_CRC_t calculated_crc; + NVM_CRC_t stored_crc = 0; + + EEPROM_read_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size); + EEPROM_read_block((uint8_t *)&stored_crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(NVM_CRC_t)); + + calculated_crc = NVM_CRC_init(); + calculated_crc = NVM_CRC_update(calculated_crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size); + calculated_crc = NVM_CRC_finalize(calculated_crc); + + if (calculated_crc == stored_crc) + { + NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE; + } + else + { + NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_CRC_FAILED; + + COMM_Console_Print_String("[NVMOn "); + COMM_Console_Print_UInt16((uint16_t) i); + COMM_Console_Print_String("] Calculated/Stored CRCs: "); + COMM_Console_Print_UInt16((uint16_t) calculated_crc); + COMM_Console_Print_String("/"); + COMM_Console_Print_UInt16((uint16_t) stored_crc); + COMM_Console_Print_String("\n"); + + COMM_Console_Print_String("[NVMOn "); + COMM_Console_Print_UInt16((uint16_t) i); + COMM_Console_Print_String("] Applying defaults.\n"); + + memcpy(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Default, NVM_OnChipEEPROMEntries[i]->Size); + + // Auto-fix the CRC. + NVM_SaveOnChipEEPROMEntry(NVM_OnChipEEPROMEntries[i]); + } + } + + taskENTER_CRITICAL(); + NVM_IsOnChipEEPROMInitialized = true; + taskEXIT_CRITICAL(); + + while(true) + { + uint8_t dummy; + + // Wait for a call to NVM_SaveOnChipEEPROMEntry(). + xStatus = xQueueReceive(xQueueOnChipEEPROM, &dummy, xTicksToWait); + + if (xStatus == pdPASS) + { + for (uint8_t i = 0; i < NVM_N_ONCHIP_EEPROM_ENTRIES; i++) + { + NVM_CRC_t crc; + +#if (defined CY_PSOC4) || (defined CY_PSOC6) + if (NVM_OnChipEEPROMEntries[i]->State == NVM_STATE_SAVE_REQUESTED) + { + if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE) + { + EEPROM_write_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size); + + // Calculate the CRC. + crc = NVM_CRC_init(); + crc = NVM_CRC_update(crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size); + crc = NVM_CRC_finalize(crc); + + EEPROM_write_block((uint8_t *)&crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(uint16_t)); + NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE; + xSemaphoreGive(xSemaphoreOnChipEEPROMLock); + } + } +#endif // (defined CY_PSOC4) || (defined CY_PSOC6) + +#if CY_PSOC5 + // From the component datasheet: + // "[On_Chip_EEPROM_UpdateTemperature()] updates the store temperature value. This should + // be called anytime the EEPROM is active and temperature may have changed by more than + // 10°C." + if (On_Chip_EEPROM_UpdateTemperature() == CYRET_SUCCESS) + { + if (NVM_OnChipEEPROMEntries[i]->State == NVM_STATE_SAVE_REQUESTED) + { + if (On_Chip_EEPROM_Query() == CYRET_SUCCESS) + { + if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE) + { + EEPROM_write_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size); + + // Calculate the CRC. + crc = NVM_CRC_init(); + crc = NVM_CRC_update(crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size); + crc = NVM_CRC_finalize(crc); + + EEPROM_write_block((uint8_t *)&crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(uint16_t)); + NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE; + xSemaphoreGive(xSemaphoreOnChipEEPROMLock); + } + } + } + } + else + { + vSerialPutString("ERROR: Couldn't update EEPROM temperature!", 80); + } +#endif // CY_PSOC5 + } + } + } +} + +//! Flags the given on-chip EEPROM entry to be saved next time the NVM_OnChipEEPROMTask() is run. +void NVM_SaveOnChipEEPROMEntry(NVM_EEPROMEntry_T * const this) +{ + if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE) + { + this->State = NVM_STATE_SAVE_REQUESTED; + xSemaphoreGive(xSemaphoreOnChipEEPROMLock); + uint8_t dummy = 0; + xQueueSend(xQueueOnChipEEPROM, &dummy, 0); + } +} + +/* Private Functions */ \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROM.h b/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROM.h new file mode 100644 index 0000000..325ef39 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROM.h @@ -0,0 +1,42 @@ +/** \file + * \brief This file contains the public interface to the on-chip EEPROM driver. + * + */ + +#ifndef NVM_ONCHIPEEPROM_H +#define NVM_ONCHIPEEPROM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +#define NVM_ON_CHIP_EEPROM_TASK_STACK_SIZE_in_bytes 256 + +//! The time between calls to NVM_OnChipEEPROMTask(). +#define NVM_ON_CHIP_EEPROM_TASK_RATE_IN_ms 2000 + +/* Include Files */ + +/* Public Variables */ + +extern SemaphoreHandle_t xSemaphoreOnChipEEPROMLock; + +//! Handle of the NVM_OnChipEEPROMTask() given when the task was created. +extern TaskHandle_t NVM_OnChipEEPROM_Task_Handle; + +extern volatile bool NVM_IsOnChipEEPROMInitialized; + +/* Public Functions */ +void NVM_InitOnChipEEPROM(void); +void NVM_OnChipEEPROMTask(void * pvParameters); +void NVM_SaveOnChipEEPROMEntry(NVM_EEPROMEntry_T * const this); + +/* Inline Functions */ + +#ifdef __cplusplus +} +#endif + +#endif // NVM_ONCHIPEEPROM_H \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROMEntries.c b/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROMEntries.c new file mode 100644 index 0000000..08b72a4 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROMEntries.c @@ -0,0 +1,63 @@ +/* + * __ ________ _____ ______ __ + * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ + * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ + * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ + * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ + * /____/ + * + * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞 + * + */ + +/** \file + * \brief [Autogenerated] This file defines the OnChip EEPROM entries. + * + * \note AUTOGENERATED: This file was generated automatically on Friday, April 28, 2023 at 11:31:31 AM. + * DO NOT MODIFY THIS FILE MANUALLY! + */ + +/* Include Files */ +#include "KTag.h" + +/* EEPROM Entries */ + +/** \defgroup NVM_ONCHIP_EEPROM NVM OnChip EEPROM + * + * The OnChip EEPROM is divided into logical "entries", represented by instances of the #NVM_EEPROMEntry_T type. + * At startup, these entries are loaded into their respective RAM copies by NVM_InitOnChipEEPROM(). The application + * then updates the RAM copies directly, and requests that the NVM_OnChipEEPROMTask() save these back to the EEPROM + * when necessary. + * @{ */ + +static NVM_OnChip_Test_T RAM_OnChip_Test; + +static const NVM_OnChip_Test_T DEFAULT_OnChip_Test = +{ + //! Test Code 1 + .OnChip_Test_1 = UINT16_MAX, + //! Test Code 2 + .OnChip_Test_2 = UINT32_MAX, +}; + +NVM_EEPROMEntry_T NVM_OnChip_Test = +{ + //! Size == sizeof(NVM_OnChip_Test_T) + .Size = 6, + .EE_Address = 0, + .EE_CRC_Address = 6, + .Value = (uint8_t *)&RAM_OnChip_Test, + .Default = (uint8_t *)&DEFAULT_OnChip_Test, + .State = NVM_STATE_UNINITIALIZED +}; + +/** @} */ + +NVM_EEPROMEntry_T * const NVM_OnChipEEPROMEntries[] = +{ + &NVM_OnChip_Test, +}; + +//! Size of the #NVM_OnChipEEPROMEntries array (i.e. the number of OnChip EEPROM entries). +const uint8_t NVM_N_ONCHIP_EEPROM_ENTRIES = (uint8_t) (sizeof(NVM_OnChipEEPROMEntries) / sizeof(NVM_EEPROMEntry_T *)); + diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROMEntries.h b/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROMEntries.h new file mode 100644 index 0000000..507737a --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROMEntries.h @@ -0,0 +1,60 @@ +/* + * __ ________ _____ ______ __ + * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ + * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ + * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ + * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ + * /____/ + * + * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞 + * + */ + +/** \file + * \brief [Autogenerated] This file declares the OnChip EEPROM entries. + * + * \note AUTOGENERATED: This file was generated automatically on Friday, April 28, 2023 at 11:31:31 AM. + * DO NOT MODIFY THIS FILE MANUALLY! + */ + +#ifndef NVM_ONCHIPEEPROMENTRIES_H +#define NVM_ONCHIPEEPROMENTRIES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Preprocessor and Type Definitions */ + +typedef struct __attribute__((packed)) +{ + //! Test Code 1 + uint16_t OnChip_Test_1; + //! Test Code 2 + uint32_t OnChip_Test_2; +} NVM_OnChip_Test_T; + + +/* Include Files */ + +/* Public Variables */ + +extern NVM_EEPROMEntry_T NVM_OnChip_Test; + +extern NVM_EEPROMEntry_T * const NVM_OnChipEEPROMEntries[]; +extern const uint8_t NVM_N_ONCHIP_EEPROM_ENTRIES; + +// Shorthand macros, to save you time. +#define NVM_ONCHIP_TEST_1 (((NVM_OnChip_Test_T*)NVM_OnChip_Test.Value)->OnChip_Test_1) +#define NVM_ONCHIP_TEST_1_ENTRY_PTR (&NVM_OnChip_Test) + +#define NVM_ONCHIP_TEST_2 (((NVM_OnChip_Test_T*)NVM_OnChip_Test.Value)->OnChip_Test_2) +#define NVM_ONCHIP_TEST_2_ENTRY_PTR (&NVM_OnChip_Test) + + +#ifdef __cplusplus +} +#endif + +#endif // NVM_ONCHIPEEPROMENTRIES_H + diff --git a/2020TPCAppNoDFU.cydsn/NVM/NVM_Settings.c b/2020TPCAppNoDFU.cydsn/NVM/NVM_Settings.c new file mode 100644 index 0000000..4585506 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/NVM/NVM_Settings.c @@ -0,0 +1,125 @@ +/** \file + * \brief This file contains functions that implement the settings interface for SystemK. + * + */ + +/* Include Files */ +#include "KTag.h" + + +SystemKResult_T SETTINGS_get_uint8_t(SystemKSettingID_T id, uint8_t * value) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + switch (id) + { + case SYSTEMK_SETTING_IS_RIGHT_HANDED: + *value = NVM_IS_RIGHT_HANDED; + break; + + case SYSTEMK_SETTING_AUDIO_VOLUME: + *value = NVM_VOLUME; + break; + + case SYSTEMK_SETTING_TEAMID: + *value = NVM_TEAM_ID; + break; + + case SYSTEMK_SETTING_PLAYERID: + *value = NVM_PLAYER_ID; + break; + + case SYSTEMK_SETTING_WEAPONID: + *value = NVM_WEAPON_ID; + break; + + default: + result = SYSTEMK_RESULT_WRONG_DATATYPE; + break; + } + + return result; +} + +SystemKResult_T SETTINGS_set_uint8_t(SystemKSettingID_T id, uint8_t value) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + switch (id) + { + case SYSTEMK_SETTING_IS_RIGHT_HANDED: + NVM_IS_RIGHT_HANDED = value; + break; + + case SYSTEMK_SETTING_AUDIO_VOLUME: + NVM_VOLUME = value; + break; + + case SYSTEMK_SETTING_TEAMID: + NVM_TEAM_ID = value; + break; + + case SYSTEMK_SETTING_PLAYERID: + NVM_PLAYER_ID = value; + break; + + case SYSTEMK_SETTING_WEAPONID: + NVM_WEAPON_ID = value; + break; + + default: + result = SYSTEMK_RESULT_WRONG_DATATYPE; + break; + } + + return result; +} + +SystemKResult_T SETTINGS_get_uint32_t(SystemKSettingID_T id, uint32_t * value) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + switch (id) + { + case SYSTEMK_SETTING_T_START_GAME_in_ms: + *value = CONFIG_KTAG_T_DEFAULT_START_GAME_in_ms; + break; + + default: + result = SYSTEMK_RESULT_WRONG_DATATYPE; + break; + } + + return result; +} + +SystemKResult_T SETTINGS_set_uint32_t(SystemKSettingID_T id, uint32_t value) +{ + SystemKResult_T result = SYSTEMK_RESULT_SUCCESS; + + switch (id) + { + case SYSTEMK_SETTING_T_START_GAME_in_ms: + result = SYSTEMK_RESULT_NOT_IMPLEMENTED; + break; + + default: + result = SYSTEMK_RESULT_WRONG_DATATYPE; + break; + } + + return result; +} + +SystemKResult_T SETTINGS_Save(void) +{ +#if (CONFIG__HAS_EXTERNAL_NVM) + NVM_SaveExternalEEPROMEntry(&NVM_Hardware_Settings); + NVM_SaveExternalEEPROMEntry(&NVM_Game_Settings); +#else // CONFIG__HAS_EXTERNAL_NVM + NVM_SaveOnChipEEPROMEntry(&NVM_Hardware_Settings); + NVM_SaveOnChipEEPROMEntry(&NVM_Game_Settings); +#endif // CONFIG__HAS_EXTERNAL_NVM + + return SYSTEMK_RESULT_SUCCESS; +} diff --git a/2020TPCAppNoDFU.cydsn/Sample_Tasks.c b/2020TPCAppNoDFU.cydsn/Sample_Tasks.c new file mode 100644 index 0000000..46bf192 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Sample_Tasks.c @@ -0,0 +1,93 @@ +/* Include Files */ +#include "KTag.h" + +TaskHandle_t Sample_Task_Handle; + +// LED Functionality +static void LED_CoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ); +#define LED_COROUTINE_PRIORITY 0 +static const TickType_t Delay_50ms = 50 / portTICK_PERIOD_MS; +static const TickType_t Delay_100ms = 100 / portTICK_PERIOD_MS; +static const TickType_t Delay_600ms = 600 / portTICK_PERIOD_MS; + +// Serial Debug Functionality +static void Serial_Debug_CoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ); +#define SERIAL_DEBUG_COROUTINE_PRIORITY 0 +static const TickType_t Delay_1s = 1000 / portTICK_PERIOD_MS; + +void Sample_Task_Init(void) +{ +} + +//! Sample task: blinks the LED and sends text out on the UART. +/*! + * \param pvParameters (not used) + * \return None (infinite loop) + */ +void Sample_Task(void * pvParameters) +{ + xCoRoutineCreate(LED_CoRoutine, LED_COROUTINE_PRIORITY, 0 ); + xCoRoutineCreate(Serial_Debug_CoRoutine, SERIAL_DEBUG_COROUTINE_PRIORITY, 0 ); + + while (true) + { + vCoRoutineSchedule(); + + // Delay a bit here so as to not starve the idle task. + vTaskDelay(10 / portTICK_PERIOD_MS); + } +} + +//! Blinks the LED. +static void LED_CoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) +{ + crSTART( xHandle ); + + static bool is_startup = false; + + while (true) + { + if (is_startup == false) + { + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 1); + crDELAY(xHandle, Delay_100ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 0); + crDELAY(xHandle, Delay_50ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 1); + crDELAY(xHandle, Delay_100ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 0); + crDELAY(xHandle, Delay_50ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 1); + crDELAY(xHandle, Delay_100ms); + + Cy_GPIO_Write(Red_LED_PORT, Red_LED_NUM, 0); + + is_startup = true; + } + crDELAY(xHandle, Delay_600ms); + } + + crEND(); +} + +static void Serial_Debug_CoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex ) +{ + crSTART( xHandle ); + + //static uint32_t i = 0; + + while (true) + { + //Debug_printf("%lu\n", i++); + //vSerialPutString(" * ", 50); + crDELAY(xHandle, Delay_1s); + } + + crEND(); +} + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/Sample_Tasks.h b/2020TPCAppNoDFU.cydsn/Sample_Tasks.h new file mode 100644 index 0000000..4d0780a --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Sample_Tasks.h @@ -0,0 +1,9 @@ +#ifndef SAMPLE_TASKS_H +#define SAMPLE_TASKS_H + +extern TaskHandle_t Sample_Task_Handle; + +void Sample_Task_Init(void); +void Sample_Task(void * pvParameters); + +#endif // SAMPLE_TASKS_H diff --git a/2020TPCAppNoDFU.cydsn/Switches.c b/2020TPCAppNoDFU.cydsn/Switches.c new file mode 100644 index 0000000..8fbdbeb --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Switches.c @@ -0,0 +1,196 @@ +/* Include Files */ +#include "KTag.h" + +TaskHandle_t Switches_Task_Handle; + +#define SWITCHES_TASK_PERIOD_IN_TICKS (100 / portTICK_PERIOD_MS) + +//! Continuously pressing a switch for this length of time will be interpreted as a long press. +/*! + * #Duration_Of_Long_Press_in_Ticks must be an integer multiple of #SWITCHES_TASK_PERIOD_IN_TICKS! + */ +static const TickType_t Duration_Of_Long_Press_in_Ticks = (10 * SWITCHES_TASK_PERIOD_IN_TICKS); + +#if (defined LIL_BRUV) || (defined LITTLE_BOY_BLUE) +static TickType_t Up_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Up_Switch_Time_Released_in_Ticks = 0; +static TickType_t Down_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Down_Switch_Time_Released_in_Ticks = 0; +static TickType_t Forward_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Forward_Switch_Time_Released_in_Ticks = 0; +static TickType_t Backward_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Backward_Switch_Time_Released_in_Ticks = 0; +#elif (defined TWENTY20TPC) +static TickType_t Accessory_Switch_Time_Pressed_in_Ticks = 0; +static TickType_t Accessory_Switch_Total_Time_Pressed_in_Ticks = 0; +static TickType_t Accessory_Switch_Time_Released_in_Ticks = 0; +static TickType_t Accessory_Switch_Time_Since_Last_Release_in_Ticks = 0; +#endif // Model + +void Switches_Init(void) +{ + +} + + +//! Reads the hardware switches and creates press and release events. +/*! + * This is a periodic task--see https://www.freertos.org/vtaskdelayuntil.html. + */ +void Switches_Task(void * pvParameters) +{ + TickType_t xLastWakeTime; + + // Initialize the xLastWakeTime variable with the current time. + xLastWakeTime = xTaskGetTickCount(); + + while (true) + { +#if (defined LIL_BRUV) || (defined LITTLE_BOY_BLUE) + if (Cy_GPIO_Read(Pin_Up_PORT, Pin_Up_NUM) == 0) + { + if (Up_Switch_Time_Pressed_in_Ticks == 0) + { + Up_Switch_Time_Released_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_UP_SWITCH_PRESSED, .Data = &Up_Switch_Time_Released_in_Ticks}; + Post_KEvent(&switch_event); + } + else if (Up_Switch_Time_Pressed_in_Ticks == Duration_Of_Long_Press_in_Ticks) + { + KEvent_T switch_event = {.ID = KEVENT_UP_SWITCH_LONG_PRESSED, .Data = &Up_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Up_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + else + { + if (Up_Switch_Time_Released_in_Ticks == 0) + { + Up_Switch_Time_Pressed_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_UP_SWITCH_RELEASED, .Data = &Up_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Up_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + + if (Cy_GPIO_Read(Pin_Down_PORT, Pin_Down_NUM) == 0) + { + if (Down_Switch_Time_Pressed_in_Ticks == 0) + { + Down_Switch_Time_Released_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_DOWN_SWITCH_PRESSED, .Data = &Down_Switch_Time_Released_in_Ticks}; + Post_KEvent(&switch_event); + } + else if (Down_Switch_Time_Pressed_in_Ticks == Duration_Of_Long_Press_in_Ticks) + { + KEvent_T switch_event = {.ID = KEVENT_DOWN_SWITCH_LONG_PRESSED, .Data = &Down_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Down_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + else + { + if (Down_Switch_Time_Released_in_Ticks == 0) + { + Down_Switch_Time_Pressed_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_DOWN_SWITCH_RELEASED, .Data = &Down_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Down_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + + if (Cy_GPIO_Read(Pin_Forward_PORT, Pin_Forward_NUM) == 0) + { + if (Forward_Switch_Time_Pressed_in_Ticks == 0) + { + Forward_Switch_Time_Released_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_FORWARD_SWITCH_PRESSED, .Data = &Forward_Switch_Time_Released_in_Ticks}; + Post_KEvent(&switch_event); + } + else if (Forward_Switch_Time_Pressed_in_Ticks == Duration_Of_Long_Press_in_Ticks) + { + KEvent_T switch_event = {.ID = KEVENT_FORWARD_SWITCH_LONG_PRESSED, .Data = &Forward_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Forward_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + else + { + if (Forward_Switch_Time_Released_in_Ticks == 0) + { + Forward_Switch_Time_Pressed_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_FORWARD_SWITCH_RELEASED, .Data = &Forward_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Forward_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + + if (Cy_GPIO_Read(Pin_Backward_PORT, Pin_Backward_NUM) == 0) + { + if (Backward_Switch_Time_Pressed_in_Ticks == 0) + { + Backward_Switch_Time_Released_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_BACKWARD_SWITCH_PRESSED, .Data = &Backward_Switch_Time_Released_in_Ticks}; + Post_KEvent(&switch_event); + } + else if (Backward_Switch_Time_Pressed_in_Ticks == Duration_Of_Long_Press_in_Ticks) + { + KEvent_T switch_event = {.ID = KEVENT_BACKWARD_SWITCH_LONG_PRESSED, .Data = &Backward_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Backward_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + else + { + if (Backward_Switch_Time_Released_in_Ticks == 0) + { + Backward_Switch_Time_Pressed_in_Ticks = 0; + KEvent_T switch_event = {.ID = KEVENT_BACKWARD_SWITCH_RELEASED, .Data = &Backward_Switch_Time_Pressed_in_Ticks}; + Post_KEvent(&switch_event); + } + + Backward_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } +#elif (defined TWENTY20TPC) + // Use the Remote Trigger pin as the Accessory input, since we never got around to using remote triggers. + if (Cy_GPIO_Read(Pin_Remote_Trigger_PORT, Pin_Remote_Trigger_NUM) == 0) + { + if (Accessory_Switch_Time_Pressed_in_Ticks == 0) + { + Accessory_Switch_Time_Since_Last_Release_in_Ticks = Accessory_Switch_Time_Released_in_Ticks; + KEvent_T switch_event = {.ID = KEVENT_ACCESSORY_SWITCH_PRESSED, .Data = (void *) pdTICKS_TO_MS(Accessory_Switch_Time_Since_Last_Release_in_Ticks)}; + Post_KEvent(&switch_event); + Accessory_Switch_Time_Released_in_Ticks = 0; + } + if ((UINT32_MAX - Accessory_Switch_Time_Pressed_in_Ticks) > SWITCHES_TASK_PERIOD_IN_TICKS) + { + Accessory_Switch_Time_Pressed_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + } + else + { + if (Accessory_Switch_Time_Released_in_Ticks == 0) + { + Accessory_Switch_Total_Time_Pressed_in_Ticks = Accessory_Switch_Time_Pressed_in_Ticks; + KEvent_T switch_event = {.ID = KEVENT_ACCESSORY_SWITCH_RELEASED, .Data = (void *) pdTICKS_TO_MS(Accessory_Switch_Total_Time_Pressed_in_Ticks)}; + Post_KEvent(&switch_event); + Accessory_Switch_Time_Pressed_in_Ticks = 0; + } + if ((UINT32_MAX - Accessory_Switch_Time_Released_in_Ticks) > SWITCHES_TASK_PERIOD_IN_TICKS) + { + Accessory_Switch_Time_Released_in_Ticks += SWITCHES_TASK_PERIOD_IN_TICKS; + } + } +#endif // Model + + // Wait for the next cycle. + vTaskDelayUntil(&xLastWakeTime, SWITCHES_TASK_PERIOD_IN_TICKS); + } +} diff --git a/2020TPCAppNoDFU.cydsn/Switches.h b/2020TPCAppNoDFU.cydsn/Switches.h new file mode 100644 index 0000000..5472fdf --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Switches.h @@ -0,0 +1,9 @@ +#ifndef SWITCHES_H +#define SWITCHES_H + +extern TaskHandle_t Switches_Task_Handle; + +void Switches_Init(void); +void Switches_Task(void * pvParameters); + +#endif // SWITCHES_H diff --git a/2020TPCAppNoDFU.cydsn/SystemK b/2020TPCAppNoDFU.cydsn/SystemK new file mode 160000 index 0000000..4fe072f --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/SystemK @@ -0,0 +1 @@ +Subproject commit 4fe072f2d3280b19aa53e197bd22ec44b174ff88 diff --git a/2020TPCAppNoDFU.cydsn/Tag_Sensors.c b/2020TPCAppNoDFU.cydsn/Tag_Sensors.c new file mode 100644 index 0000000..2b535e1 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Tag_Sensors.c @@ -0,0 +1,582 @@ +/* Include Files */ +#include "KTag.h" + +TaskHandle_t Tag_Sensors_Task_Handle; + +//#define DEBUG_TAG_SENSORS + +#define MAX_RX_PULSES (2 * MAX_PULSES) + +typedef enum +{ + FALLING_EDGE, + RISING_EDGE +} EdgeDirection_T; + +static volatile uint32_t LocalIncomingPulseDurations[MAX_RX_PULSES]; +static volatile uint32_t RemoteIncomingPulseDurations[MAX_RX_PULSES]; +static volatile uint16_t LocalPulseIndex = 0; +static volatile uint16_t RemotePulseIndex = 0; +static volatile uint16_t NumberOfLocalIncomingPulses = 0; +static volatile uint16_t NumberOfRemoteIncomingPulses = 0; +static volatile TagSensorLocation_T LocalActiveSensor = TAG_SENSOR_NONE; +static uint32_t LocalProcessingPulseDurations[MAX_RX_PULSES]; +static uint32_t RemoteProcessingPulseDurations[MAX_RX_PULSES]; +static uint16_t NumberOfLocalProcessingPulses = 0; +static uint16_t NumberOfRemoteProcessingPulses = 0; +static TimedPulseTrain_T LocalProcessingPulses; +static TimedPulseTrain_T RemoteProcessingPulses; +static TagSensorLocation_T LocalProcessingSensor = TAG_SENSOR_NONE; +static volatile EdgeDirection_T LocalExpectedEdgeDirection = FALLING_EDGE; +static volatile EdgeDirection_T RemoteExpectedEdgeDirection = FALLING_EDGE; + + +void On_Forward_Tag_Sensor_Rising_Edge(); +void On_Forward_Tag_Sensor_Falling_Edge(); +void On_Left_Tag_Sensor_Rising_Edge(); +void On_Left_Tag_Sensor_Falling_Edge(); +void On_Right_Tag_Sensor_Rising_Edge(); +void On_Right_Tag_Sensor_Falling_Edge(); +void On_Remote_Tag_Sensor_Rising_Edge(); +void On_Remote_Tag_Sensor_Falling_Edge(); +void On_Local_Tag_Sensor_Bit_Stream_Timer(); +void On_Remote_Tag_Sensor_Bit_Stream_Timer(); + +QueueHandle_t xQueueTagSensors; + +#ifdef DEBUG_TAG_SENSORS +static char8 buffer[30]; +#endif // DEBUG_TAG_SENSORS + +inline static void AppendLocalPulse(uint32_t duration) +{ + LocalIncomingPulseDurations[LocalPulseIndex] = duration; + + if (LocalPulseIndex < (MAX_RX_PULSES - 1)) + { + LocalPulseIndex++; + } +} + +inline static void AppendRemotePulse(uint32_t duration) +{ + RemoteIncomingPulseDurations[RemotePulseIndex] = duration; + + if (RemotePulseIndex < (MAX_RX_PULSES - 1)) + { + RemotePulseIndex++; + } +} + +inline static void EnableAllLocalEdgeISRs(void) +{ + NVIC_EnableIRQ(Forward_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Forward_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Left_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Right_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Right_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void EnableAllRemoteEdgeISRs(void) +{ + NVIC_EnableIRQ(Remote_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_EnableIRQ(Remote_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllLocalRisingEdgeISRs(void) +{ + NVIC_DisableIRQ(Forward_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_DisableIRQ(Left_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_DisableIRQ(Right_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllRemoteRisingEdgeISRs(void) +{ + NVIC_DisableIRQ(Remote_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllLocalFallingEdgeISRs(void) +{ + NVIC_DisableIRQ(Forward_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_DisableIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_DisableIRQ(Right_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllRemoteFallingEdgeISRs(void) +{ + NVIC_DisableIRQ(Remote_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void DisableAllLocalEdgeISRs(void) +{ + DisableAllLocalRisingEdgeISRs(); + DisableAllLocalFallingEdgeISRs(); +} + +inline static void DisableAllRemoteEdgeISRs(void) +{ + DisableAllRemoteRisingEdgeISRs(); + DisableAllRemoteFallingEdgeISRs(); +} + +inline static void ClearAllPendingLocalEdgeISRs(void) +{ + NVIC_ClearPendingIRQ(Forward_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Forward_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Right_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Right_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +inline static void ClearAllPendingRemoteEdgeISRs(void) +{ + NVIC_ClearPendingIRQ(Remote_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + NVIC_ClearPendingIRQ(Remote_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); +} + +void Tag_Sensors_Init(void) +{ + // Register the Local ISRs. + Cy_SysInt_Init(&Forward_Tag_Sensor_Rising_Edge_ISR_cfg, On_Forward_Tag_Sensor_Rising_Edge); + Cy_SysInt_Init(&Forward_Tag_Sensor_Falling_Edge_ISR_cfg, On_Forward_Tag_Sensor_Falling_Edge); + Cy_SysInt_Init(&Left_Tag_Sensor_Rising_Edge_ISR_cfg, On_Left_Tag_Sensor_Rising_Edge); + Cy_SysInt_Init(&Left_Tag_Sensor_Falling_Edge_ISR_cfg, On_Left_Tag_Sensor_Falling_Edge); + Cy_SysInt_Init(&Right_Tag_Sensor_Rising_Edge_ISR_cfg, On_Right_Tag_Sensor_Rising_Edge); + Cy_SysInt_Init(&Right_Tag_Sensor_Falling_Edge_ISR_cfg, On_Right_Tag_Sensor_Falling_Edge); + Cy_SysInt_Init(&Local_Tag_Sensor_Bit_Stream_Timer_Interrupt_cfg, On_Local_Tag_Sensor_Bit_Stream_Timer); + + // Register the Remote ISRs. + Cy_SysInt_Init(&Remote_Tag_Sensor_Rising_Edge_ISR_cfg, On_Remote_Tag_Sensor_Rising_Edge); + Cy_SysInt_Init(&Remote_Tag_Sensor_Falling_Edge_ISR_cfg, On_Remote_Tag_Sensor_Falling_Edge); + Cy_SysInt_Init(&Remote_Tag_Sensor_Bit_Stream_Timer_Interrupt_cfg, On_Remote_Tag_Sensor_Bit_Stream_Timer); + + // Enable the forward, left, right, and remote sensors. + Tag_Sensor_Register_Write(0xFF - 0x0F); + + xQueueTagSensors = xQueueCreate(5, sizeof(TagSensorsAction_T)); + + // Enable the timers. + NVIC_EnableIRQ(Local_Tag_Sensor_Bit_Stream_Timer_Interrupt_cfg.intrSrc); + NVIC_EnableIRQ(Remote_Tag_Sensor_Bit_Stream_Timer_Interrupt_cfg.intrSrc); + + // Enable the sensors. + EnableAllLocalEdgeISRs(); + EnableAllRemoteEdgeISRs(); + +} + +void Tag_Sensors_Task(void * pvParameters) +{ + portBASE_TYPE xStatus; + + while (true) + { + TagSensorsAction_T action; + + xStatus = xQueueReceive(xQueueTagSensors, &action, 0); + + if (xStatus == pdPASS) + { + switch (action) + { + case TAG_SENSOR_PROCESS_LOCAL_BUFFER: + { + for (uint8_t i = 0; i < NumberOfLocalIncomingPulses; i++) + { + LocalProcessingPulseDurations[i] = LocalIncomingPulseDurations[i]; + } + NumberOfLocalProcessingPulses = NumberOfLocalIncomingPulses; + NumberOfLocalIncomingPulses = 0; + LocalProcessingSensor = LocalActiveSensor; + LocalActiveSensor = TAG_SENSOR_NONE; + EnableAllLocalEdgeISRs(); + +#ifdef DEBUG_TAG_SENSORS + COMM_Console_Print_String("\n"); + + switch (LocalProcessingSensor) + { + case TAG_SENSOR_FORWARD: + COMM_Console_Print_String("Tag Rx'd FORWARD\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + break; + + case TAG_SENSOR_LEFT: + COMM_Console_Print_String("Tag Rx'd LEFT\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + break; + + case TAG_SENSOR_RIGHT: + COMM_Console_Print_String("Tag Rx'd RIGHT\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + break; + + default: + case TAG_SENSOR_REMOTE: + case TAG_SENSOR_NONE: + break; + } + + for (uint_fast16_t i = 0; i < NumberOfLocalProcessingPulses; i++) + { + // Even pulses are marks; odd pulses are spaces. + if ((i % 2) == 0) + { + COMM_Console_Print_String("{.symbol = MARK, .time = "); + sprintf(buffer, "%lu}, // %d\n", LocalProcessingPulseDurations[i], i); + COMM_Console_Print_String(buffer); + vTaskDelay(pdMS_TO_TICKS(10)); + } + // A falling edge is the end of space. + else + { + COMM_Console_Print_String("{.symbol = SPACE, .time = "); + sprintf(buffer, "%lu}, // %d\n", LocalProcessingPulseDurations[i], i); + COMM_Console_Print_String(buffer); + vTaskDelay(pdMS_TO_TICKS(10)); + } + } +#endif // DEBUG_TAG_SENSORS + + LocalProcessingPulses.count = NumberOfLocalProcessingPulses; + for (uint_fast16_t i = 0; (i < NumberOfLocalProcessingPulses) && (i < MAX_RX_PULSES); i++) + { + if ((i % 2) == 0) + { + LocalProcessingPulses.bitstream[i].symbol = MARK; + } + else + { + LocalProcessingPulses.bitstream[i].symbol = SPACE; + } + LocalProcessingPulses.bitstream[i].duration = LocalProcessingPulseDurations[i]; + } + LocalProcessingPulses.bitstream[NumberOfLocalProcessingPulses].duration = LAST_PULSE; + LocalProcessingPulses.receiver = LocalProcessingSensor; + + DecodedPacket_T * result = PROTOCOLS_MaybeDecodePacket(&LocalProcessingPulses); + + if (result != NULL) + { + if (result->Generic.type == DECODED_PACKET_TYPE_TAG_RECEIVED) + { + KEvent_T tag_received_event = {.ID = KEVENT_TAG_RECEIVED, .Data = result}; + Post_KEvent(&tag_received_event); + } + else if (result->Generic.type == DECODED_PACKET_TYPE_COMMAND_RECEIVED) + { + KEvent_T command_received_event = {.ID = KEVENT_COMMAND_RECEIVED, .Data = result}; + Post_KEvent(&command_received_event); + } + } + else + { + KEvent_T near_miss_event = {.ID = KEVENT_NEAR_MISS, .Data = NULL}; + Post_KEvent(&near_miss_event); + } + } + break; + + case TAG_SENSOR_PROCESS_REMOTE_BUFFER: + { + for (uint8_t i = 0; i < NumberOfRemoteIncomingPulses; i++) + { + RemoteProcessingPulseDurations[i] = RemoteIncomingPulseDurations[i]; + } + NumberOfRemoteProcessingPulses = NumberOfRemoteIncomingPulses; + NumberOfRemoteIncomingPulses = 0; + EnableAllRemoteEdgeISRs(); + +#ifdef DEBUG_TAG_SENSORS + COMM_Console_Print_String("\n"); + + COMM_Console_Print_String("Tag Rx'd REMOTE\n"); + vTaskDelay(pdMS_TO_TICKS(10)); + + for (uint_fast16_t i = 0; i < NumberOfRemoteProcessingPulses; i++) + { + // Even pulses are marks; odd pulses are spaces. + if ((i % 2) == 0) + { + COMM_Console_Print_String("{.symbol = MARK, .time = "); + sprintf(buffer, "%lu}, // %d\n", RemoteProcessingPulseDurations[i], i); + COMM_Console_Print_String(buffer); + vTaskDelay(pdMS_TO_TICKS(10)); + } + // A falling edge is the end of space. + else + { + COMM_Console_Print_String("{.symbol = SPACE, .time = "); + sprintf(buffer, "%lu}, // %d\n", RemoteProcessingPulseDurations[i], i); + COMM_Console_Print_String(buffer); + vTaskDelay(pdMS_TO_TICKS(10)); + } + } +#endif // DEBUG_TAG_SENSORS + RemoteProcessingPulses.count = NumberOfRemoteProcessingPulses; + for (uint_fast16_t i = 0; (i < NumberOfRemoteProcessingPulses) && (i < MAX_RX_PULSES); i++) + { + if ((i % 2) == 0) + { + RemoteProcessingPulses.bitstream[i].symbol = MARK; + } + else + { + RemoteProcessingPulses.bitstream[i].symbol = SPACE; + } + RemoteProcessingPulses.bitstream[i].duration = RemoteProcessingPulseDurations[i]; + } + RemoteProcessingPulses.bitstream[NumberOfRemoteProcessingPulses].duration = LAST_PULSE; + RemoteProcessingPulses.receiver = TAG_SENSOR_REMOTE; + + DecodedPacket_T * result = PROTOCOLS_MaybeDecodePacket(&RemoteProcessingPulses); + + if (result != NULL) + { + if (result->Generic.type == DECODED_PACKET_TYPE_TAG_RECEIVED) + { + KEvent_T tag_received_event = {.ID = KEVENT_TAG_RECEIVED, .Data = result}; + Post_KEvent(&tag_received_event); + } + else if (result->Generic.type == DECODED_PACKET_TYPE_COMMAND_RECEIVED) + { + KEvent_T command_received_event = {.ID = KEVENT_COMMAND_RECEIVED, .Data = result}; + Post_KEvent(&command_received_event); + } + } + else + { + KEvent_T near_miss_event = {.ID = KEVENT_NEAR_MISS, .Data = NULL}; + Post_KEvent(&near_miss_event); + } + } + break; + + default: + break; + } + } + + vTaskDelay(100 / portTICK_PERIOD_MS); + } +} + +// A rising edge means the IR carrier frequency is no longer detected. +void On_Forward_Tag_Sensor_Rising_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (LocalActiveSensor == TAG_SENSOR_FORWARD) + { + if (LocalExpectedEdgeDirection == RISING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Forward_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + + AppendLocalPulse(counter); + LocalExpectedEdgeDirection = FALLING_EDGE; + } + } +} + +// A falling edge means the IR carrier frequency has been detected. +void On_Forward_Tag_Sensor_Falling_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if ((LocalActiveSensor == TAG_SENSOR_FORWARD) || (LocalActiveSensor == TAG_SENSOR_NONE)) + { + if (LocalExpectedEdgeDirection == FALLING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Forward_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + + if (LocalPulseIndex == 0) + { + Local_Tag_Sensor_Bit_Stream_Timer_Start(); + LocalActiveSensor = TAG_SENSOR_FORWARD; + } + else + { + AppendLocalPulse(counter); + } + LocalExpectedEdgeDirection = RISING_EDGE; + } + } +} + +// A rising edge means the IR carrier frequency is no longer detected. +void On_Left_Tag_Sensor_Rising_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (LocalActiveSensor == TAG_SENSOR_LEFT) + { + if (LocalExpectedEdgeDirection == RISING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + + AppendLocalPulse(counter); + LocalExpectedEdgeDirection = FALLING_EDGE; + } + } +} + +// A falling edge means the IR carrier frequency has been detected. +void On_Left_Tag_Sensor_Falling_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if ((LocalActiveSensor == TAG_SENSOR_LEFT) || (LocalActiveSensor == TAG_SENSOR_NONE)) + { + if (LocalExpectedEdgeDirection == FALLING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + + if (LocalPulseIndex == 0) + { + Local_Tag_Sensor_Bit_Stream_Timer_Start(); + LocalActiveSensor = TAG_SENSOR_LEFT; + } + else + { + AppendLocalPulse(counter); + } + LocalExpectedEdgeDirection = RISING_EDGE; + } + } +} + +// A rising edge means the IR carrier frequency is no longer detected. +void On_Right_Tag_Sensor_Rising_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (LocalActiveSensor == TAG_SENSOR_RIGHT) + { + if (LocalExpectedEdgeDirection == RISING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Right_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + + AppendLocalPulse(counter); + LocalExpectedEdgeDirection = FALLING_EDGE; + } + } +} + +// A falling edge means the IR carrier frequency has been detected. +void On_Right_Tag_Sensor_Falling_Edge() +{ + uint32_t counter = Local_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if ((LocalActiveSensor == TAG_SENSOR_RIGHT) || (LocalActiveSensor == TAG_SENSOR_NONE)) + { + if (LocalExpectedEdgeDirection == FALLING_EDGE) + { + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Left_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + + if (LocalPulseIndex == 0) + { + Local_Tag_Sensor_Bit_Stream_Timer_Start(); + LocalActiveSensor = TAG_SENSOR_RIGHT; + } + else + { + AppendLocalPulse(counter); + } + LocalExpectedEdgeDirection = RISING_EDGE; + } + } +} + +// A rising edge means the IR carrier frequency is no longer detected. +void On_Remote_Tag_Sensor_Rising_Edge() +{ + uint32_t counter = Remote_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (RemoteExpectedEdgeDirection == RISING_EDGE) + { + Remote_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Remote_Tag_Sensor_Rising_Edge_ISR_cfg.intrSrc); + + AppendRemotePulse(counter); + RemoteExpectedEdgeDirection = FALLING_EDGE; + } +} + +// A falling edge means the IR carrier frequency has been detected. +void On_Remote_Tag_Sensor_Falling_Edge() +{ + uint32_t counter = Remote_Tag_Sensor_Bit_Stream_Timer_GetCounter(); + + if (RemoteExpectedEdgeDirection == FALLING_EDGE) + { + Remote_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NVIC_ClearPendingIRQ(Remote_Tag_Sensor_Falling_Edge_ISR_cfg.intrSrc); + + if (RemotePulseIndex == 0) + { + Remote_Tag_Sensor_Bit_Stream_Timer_Start(); + } + else + { + AppendRemotePulse(counter); + } + RemoteExpectedEdgeDirection = RISING_EDGE; + } +} + +void On_Local_Tag_Sensor_Bit_Stream_Timer() +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + // Read and clear the interrupt status. + uint32_t status = Local_Tag_Sensor_Bit_Stream_Timer_GetInterruptStatus(); + Local_Tag_Sensor_Bit_Stream_Timer_ClearInterrupt(CY_TCPWM_INT_ON_TC); + + if (status & CY_TCPWM_INT_ON_TC) + { + // The timer expired. + Local_Tag_Sensor_Bit_Stream_Timer_TriggerStop(); + Local_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NumberOfLocalIncomingPulses = LocalPulseIndex; + LocalPulseIndex = 0; + DisableAllLocalEdgeISRs(); + LocalExpectedEdgeDirection = FALLING_EDGE; + const TagSensorsAction_T action = TAG_SENSOR_PROCESS_LOCAL_BUFFER; + xQueueSendFromISR(xQueueTagSensors, &action, &xHigherPriorityTaskWoken); + } + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + +void On_Remote_Tag_Sensor_Bit_Stream_Timer() +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; + + // Read and clear the interrupt status. + uint32_t status = Remote_Tag_Sensor_Bit_Stream_Timer_GetInterruptStatus(); + Remote_Tag_Sensor_Bit_Stream_Timer_ClearInterrupt(CY_TCPWM_INT_ON_TC); + + if (status & CY_TCPWM_INT_ON_TC) + { + // The timer expired. + Remote_Tag_Sensor_Bit_Stream_Timer_TriggerStop(); + Remote_Tag_Sensor_Bit_Stream_Timer_SetCounter(0); + NumberOfRemoteIncomingPulses = RemotePulseIndex; + RemotePulseIndex = 0; + DisableAllRemoteEdgeISRs(); + RemoteExpectedEdgeDirection = FALLING_EDGE; + const TagSensorsAction_T action = TAG_SENSOR_PROCESS_REMOTE_BUFFER; + xQueueSendFromISR(xQueueTagSensors, &action, &xHigherPriorityTaskWoken); + } + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +} + diff --git a/2020TPCAppNoDFU.cydsn/Tag_Sensors.h b/2020TPCAppNoDFU.cydsn/Tag_Sensors.h new file mode 100644 index 0000000..d32d049 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/Tag_Sensors.h @@ -0,0 +1,16 @@ +#ifndef TAG_SENSORS_H +#define TAG_SENSORS_H + + +extern TaskHandle_t Tag_Sensors_Task_Handle; + +void Tag_Sensors_Init(void); +void Tag_Sensors_Task(void * pvParameters); + +typedef enum +{ + TAG_SENSOR_PROCESS_LOCAL_BUFFER, + TAG_SENSOR_PROCESS_REMOTE_BUFFER +} TagSensorsAction_T; + +#endif // TAG_SENSORS_H \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/TopDesign/TopDesign.cysch b/2020TPCAppNoDFU.cydsn/TopDesign/TopDesign.cysch new file mode 100644 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Increments a value using modular arithmetic. +/*! + * \param value the value to be incremented + * \param modulus the modulus to use + * \return (value + 1) modulo modulus + */ +inline uint16_t ModuloIncrement(const uint16_t value, const uint16_t modulus) +{ + uint16_t nextValue = value + 1; + if (nextValue >= modulus) + { + nextValue = 0; + } + return (nextValue); +} + +//! Initializes the circular buffer, and clears the flags. +/*! + * \param this pointer to the circular buffer in question + * \param buffer pointer to the memory allocated to store this circular buffer + * \param size size (in bytes) of this circular buffer + */ +void UTIL_InitCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t * buffer, uint16_t size) +{ + this->buffer = buffer; + this->size = size; + this->head = 0; + this->tail = 0; + this->count = 0; + // Note that there is no need to zero out the actual buffer, + // since it will be overwritten when values are added. +} + +//! Adds a value to the end of the circular buffer. +/*! + * If the buffer is full, the value is dropped and the overflow flag is set. + * + * \param this pointer to the circular buffer in question + * \param value the value to be added to the buffer + */ +UTIL_CircularBufferResult_T UTIL_PushToCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t value) +{ + UTIL_CircularBufferResult_T result = UTIL_CIRCULARBUFFERRESULT_UNKNOWN; + + //UBaseType_t uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + portDISABLE_INTERRUPTS(); + + if (this->count < this->size) + { + this->buffer[this->head] = value; + this->head = ModuloIncrement(this->head, this->size); + this->count++; + result = UTIL_CIRCULARBUFFERRESULT_SUCCESS; + } + else + { + result = UTIL_CIRCULARBUFFERRESULT_ERROR_OVERFLOW; + } + + portENABLE_INTERRUPTS(); + //taskEXIT_CRITICAL_FROM_ISR(uxSavedInterruptStatus); + + return result; +} + +//! Retrieves a value from the beginning of the circular buffer (FIFO). +/*! + * If the buffer is empty, zero is returned and the underflow flag is set. + * + * \param this pointer to the circular buffer in question + * \return the oldest value in the buffer + */ +UTIL_CircularBufferResult_T UTIL_PopFromCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t * const value) +{ + UTIL_CircularBufferResult_T result = UTIL_CIRCULARBUFFERRESULT_UNKNOWN; + + //UBaseType_t uxSavedInterruptStatus = taskENTER_CRITICAL_FROM_ISR(); + portDISABLE_INTERRUPTS(); + + if (this->count > 0) + { + *value = this->buffer[this->tail]; + this->tail = ModuloIncrement(this->tail, this->size); + this->count--; + result = UTIL_CIRCULARBUFFERRESULT_SUCCESS; + } + else + { + *value = 0; + result = UTIL_CIRCULARBUFFERRESULT_ERROR_UNDERFLOW; + } + + portENABLE_INTERRUPTS(); + //taskEXIT_CRITICAL_FROM_ISR(uxSavedInterruptStatus); + + return result; +} + +//! Determines whether or not the circular buffer is empty. +/*! + * \param this pointer to the circular buffer in question + * \return true if the buffer is empty; false otherwise + */ +bool UTIL_IsCircularBufferEmpty(UTIL_CircularBuffer_T * const this) +{ + bool result = false; + + if (this->count == 0) + { + result = true; + } + + return result; +} + +//! Determines whether or not the circular buffer is full. +/*! + * \param this pointer to the circular buffer in question + * \return true if the buffer is full; false otherwise + */ +bool UTIL_IsCircularBufferFull(UTIL_CircularBuffer_T * const this) +{ + bool result = false; + + if (this->count >= this->size) + { + result = true; + } + + return result; +} diff --git a/2020TPCAppNoDFU.cydsn/UTIL/UTIL_CircularBuffer.h b/2020TPCAppNoDFU.cydsn/UTIL/UTIL_CircularBuffer.h new file mode 100644 index 0000000..1e5fa9b --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/UTIL/UTIL_CircularBuffer.h @@ -0,0 +1,41 @@ +/** \file + * \brief This file contains definitions for a circular buffer. + * + */ + +#ifndef UTIL_CIRCULARBUFFER_H +#define UTIL_CIRCULARBUFFER_H + +/* Definitions */ + +typedef enum +{ + //! The result could not be determined. + UTIL_CIRCULARBUFFERRESULT_UNKNOWN = 0, + //! The requested action completed successfully. + UTIL_CIRCULARBUFFERRESULT_SUCCESS, + //! There is no more room in the buffer. + UTIL_CIRCULARBUFFERRESULT_ERROR_OVERFLOW, + //! There is no data left in the buffer. + UTIL_CIRCULARBUFFERRESULT_ERROR_UNDERFLOW +} UTIL_CircularBufferResult_T; + +//! Circular buffer data structure. +typedef struct +{ + uint8_t * buffer; + uint16_t size; + volatile uint16_t head; + volatile uint16_t tail; + volatile uint16_t count; +} UTIL_CircularBuffer_T; + +/* Function Declarations */ + +void UTIL_InitCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t * buffer, uint16_t size); +UTIL_CircularBufferResult_T UTIL_PushToCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t value); +UTIL_CircularBufferResult_T UTIL_PopFromCircularBuffer(UTIL_CircularBuffer_T * const this, uint8_t * const value); +bool UTIL_IsCircularBufferEmpty(UTIL_CircularBuffer_T * const this); +bool UTIL_IsCircularBufferFull(UTIL_CircularBuffer_T * const this); + +#endif // UTIL_CIRCULARBUFFER_H diff --git a/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.icf b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.icf new file mode 100644 index 0000000..71ba887 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.icf @@ -0,0 +1,218 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.icf +* \version 2.20 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; +place in IROM1_region { block RO }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_header, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.ld b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.ld new file mode 100644 index 0000000..90fb447 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.ld @@ -0,0 +1,402 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm0plus.ld +* \version 2.20 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'. + */ + ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x24000 + flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x4000 /* 16 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .cy_app_header : + { + KEEP(*(.cy_app_header)) + } > flash + + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.scat b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.scat new file mode 100644 index 0000000..6c49340 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm0plus.scat @@ -0,0 +1,207 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm0plus.scat +;* \version 2.20 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM0+ core. +; You can change the memory allocation by editing the RAM and Flash defines. +; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'. +; RAM +#define RAM_START 0x08000000 +#define RAM_SIZE 0x00024000 +; Flash +#define FLASH_START 0x10000000 +#define FLASH_SIZE 0x00080000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_FLASH FLASH_START FLASH_SIZE +{ + .cy_app_header +0 + { + * (.cy_app_header) + } + + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.icf b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.icf new file mode 100644 index 0000000..0f831e7 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,219 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.icf +* \version 2.20 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol __ICFEDIT_size_cstack__ = 0x1000; +} else { + define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; +} +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + + +/*-Placement-*/ + +/* Flash */ +place at start of IROM1_region { block RO }; +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { readwrite }; +place at end of IRAM1_region { block HSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.ld b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.ld new file mode 100644 index 0000000..54e5e5e --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,408 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.20 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x23800 + flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x80000 + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14004000, LENGTH = 0x4000 /* 16 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + .text : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > ram + + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + KEEP(*(.stack*)) + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.scat b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.scat new file mode 100644 index 0000000..d45ccea --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/cy8c6xx7_cm4_dual.scat @@ -0,0 +1,213 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.scat +;* \version 2.20 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;******************************************************************************/ + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START 0x08024000 +#define RAM_SIZE 0x00023800 +; Flash +#define FLASH_START 0x10080000 +#define FLASH_SIZE 0x00080000 + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +LR_FLASH FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + ER_RAM_DATA +0 + { + * (.cy_ramfunc) + .ANY (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + ER_RAM_NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/cy_ble_config.h b/2020TPCAppNoDFU.cydsn/cy_ble_config.h new file mode 100644 index 0000000..2f382ef --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/cy_ble_config.h @@ -0,0 +1,66 @@ +/***************************************************************************//** +* \file cy_ble_config.h +* \version 2.80 +* +* \brief +* The user BLE configuration file. Allows redefining the configuration #define(s) +* generated by the BLE customizer. +* +******************************************************************************** +* \copyright +* Copyright 2017-2023, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef CY_BLE_CONF_H +#define CY_BLE_CONF_H + +#include "ble/cy_ble_defines.h" + +/** + * The BLE_config.h file is generated by the BLE customizer and includes all common + * configuration defines (CY_BLE_CONFIG_***). + */ +#include "BLE_config.h" + +#include +#ifndef CY_IP_MXBLESS + #error "The BLE middleware is not supported on this device" +#endif + +/** + * The BLE Interrupt Notification Feature - Exposes BLE interrupt notifications + * to an application that indicates a different link layer and radio state + * transition to the user from the BLESS interrupt context. + * This callback is triggered at the beginning of a received BLESS interrupt + * (based on the registered interrupt mask). After this feature is enabled, + * the following APIs are available: + * Cy_BLE_RegisterInterruptCallback() and Cy_BLE_UnRegisterInterruptCallback(). + * + * The valid value: 1u - enable / 0u - disable. + * + * BLE Dual mode requires an additional define IPC channel and IPC Interrupt + * structure to send notification from the controller core to host core. + * Use the following defines: + * #define CY_BLE_INTR_NOTIFY_IPC_CHAN (9..15) + * #define CY_BLE_INTR_NOTIFY_IPC_INTR (9..15) + * #define CY_BLE_INTR_NOTIFY_IPC_INTR_PRIOR (0..7) + */ +#define CY_BLE_INTR_NOTIFY_FEATURE_ENABLE (0u) + + +/** + * To redefine the config #define(s) generated by the BLE customizer, + * use the construction #undef... #define. + * + * #undef CY_BLE_CONFIG_ENABLE_LL_PRIVACY + * #define CY_BLE_CONFIG_ENABLE_LL_PRIVACY (1u) + * + */ + + +#endif /* !defined(CY_BLE_CONF_H)*/ + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/cyapicallbacks.h b/2020TPCAppNoDFU.cydsn/cyapicallbacks.h new file mode 100644 index 0000000..e919754 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/cyapicallbacks.h @@ -0,0 +1,28 @@ +/* ======================================== + * + * Copyright YOUR COMPANY, THE YEAR + * All Rights Reserved + * UNPUBLISHED, LICENSED SOFTWARE. + * + * CONFIDENTIAL AND PROPRIETARY INFORMATION + * WHICH IS THE PROPERTY OF your company. + * + * ======================================== +*/ +#ifndef CYAPICALLBACKS_H +#define CYAPICALLBACKS_H + + +#if CY_CPU_CORTEX_M0P + /*Define your Cortex-M0P macro callbacks here */ +#endif + +#if CY_CPU_CORTEX_M4 + /*Define your Cortex-M4 macro callbacks here */ +#endif + + /*For more information, refer to the Writing Code topic in the PSoC Creator Help.*/ + + +#endif /* CYAPICALLBACKS_H */ +/* [] */ diff --git a/2020TPCAppNoDFU.cydsn/gcc/startup_psoc6_01_cm0plus.S b/2020TPCAppNoDFU.cydsn/gcc/startup_psoc6_01_cm0plus.S new file mode 100644 index 0000000..e26df0a --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/gcc/startup_psoc6_01_cm0plus.S @@ -0,0 +1,404 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm0plus.S + * @brief CMSIS Core Device Startup File for + * ARMCM0plus Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */ + def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */ + def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */ + def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */ + def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */ + def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */ + def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */ + def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */ + def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */ + def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */ + def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */ + def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */ + def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */ + def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */ + def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */ + def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */ + def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */ + def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */ + def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */ + def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */ + def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */ + def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */ + def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */ + def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */ + def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */ + def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */ + def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */ + def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */ + def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */ + def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */ + def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */ + def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */ + + .end + + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/gcc/startup_psoc6_01_cm4.S b/2020TPCAppNoDFU.cydsn/gcc/startup_psoc6_01_cm4.S new file mode 100644 index 0000000..b904621 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/gcc/startup_psoc6_01_cm4.S @@ -0,0 +1,635 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + + bl main + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/iar/startup_psoc6_01_cm0plus.s b/2020TPCAppNoDFU.cydsn/iar/startup_psoc6_01_cm0plus.s new file mode 100644 index 0000000..a867384 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/iar/startup_psoc6_01_cm0plus.s @@ -0,0 +1,423 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Power Mode Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK NvicMux0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux0_IRQHandler + B NvicMux0_IRQHandler + + PUBWEAK NvicMux1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux1_IRQHandler + B NvicMux1_IRQHandler + + PUBWEAK NvicMux2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux2_IRQHandler + B NvicMux2_IRQHandler + + PUBWEAK NvicMux3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux3_IRQHandler + B NvicMux3_IRQHandler + + PUBWEAK NvicMux4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux4_IRQHandler + B NvicMux4_IRQHandler + + PUBWEAK NvicMux5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux5_IRQHandler + B NvicMux5_IRQHandler + + PUBWEAK NvicMux6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux6_IRQHandler + B NvicMux6_IRQHandler + + PUBWEAK NvicMux7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux7_IRQHandler + B NvicMux7_IRQHandler + + PUBWEAK NvicMux8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux8_IRQHandler + B NvicMux8_IRQHandler + + PUBWEAK NvicMux9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux9_IRQHandler + B NvicMux9_IRQHandler + + PUBWEAK NvicMux10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux10_IRQHandler + B NvicMux10_IRQHandler + + PUBWEAK NvicMux11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux11_IRQHandler + B NvicMux11_IRQHandler + + PUBWEAK NvicMux12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux12_IRQHandler + B NvicMux12_IRQHandler + + PUBWEAK NvicMux13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux13_IRQHandler + B NvicMux13_IRQHandler + + PUBWEAK NvicMux14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux14_IRQHandler + B NvicMux14_IRQHandler + + PUBWEAK NvicMux15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux15_IRQHandler + B NvicMux15_IRQHandler + + PUBWEAK NvicMux16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux16_IRQHandler + B NvicMux16_IRQHandler + + PUBWEAK NvicMux17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux17_IRQHandler + B NvicMux17_IRQHandler + + PUBWEAK NvicMux18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux18_IRQHandler + B NvicMux18_IRQHandler + + PUBWEAK NvicMux19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux19_IRQHandler + B NvicMux19_IRQHandler + + PUBWEAK NvicMux20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux20_IRQHandler + B NvicMux20_IRQHandler + + PUBWEAK NvicMux21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux21_IRQHandler + B NvicMux21_IRQHandler + + PUBWEAK NvicMux22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux22_IRQHandler + B NvicMux22_IRQHandler + + PUBWEAK NvicMux23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux23_IRQHandler + B NvicMux23_IRQHandler + + PUBWEAK NvicMux24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux24_IRQHandler + B NvicMux24_IRQHandler + + PUBWEAK NvicMux25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux25_IRQHandler + B NvicMux25_IRQHandler + + PUBWEAK NvicMux26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux26_IRQHandler + B NvicMux26_IRQHandler + + PUBWEAK NvicMux27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux27_IRQHandler + B NvicMux27_IRQHandler + + PUBWEAK NvicMux28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux28_IRQHandler + B NvicMux28_IRQHandler + + PUBWEAK NvicMux29_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux29_IRQHandler + B NvicMux29_IRQHandler + + PUBWEAK NvicMux30_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux30_IRQHandler + B NvicMux30_IRQHandler + + PUBWEAK NvicMux31_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +NvicMux31_IRQHandler + B NvicMux31_IRQHandler + + + END + + +; [] END OF FILE diff --git a/2020TPCAppNoDFU.cydsn/iar/startup_psoc6_01_cm4.s b/2020TPCAppNoDFU.cydsn/iar/startup_psoc6_01_cm4.s new file mode 100644 index 0000000..6f1e869 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/iar/startup_psoc6_01_cm4.s @@ -0,0 +1,1142 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/2020TPCAppNoDFU.cydsn/main_cm0p.c b/2020TPCAppNoDFU.cydsn/main_cm0p.c new file mode 100644 index 0000000..25e9c11 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/main_cm0p.c @@ -0,0 +1,30 @@ +#include "project.h" + +#include "COMM_IPC_Messages.h" + +int main(void) +{ + __enable_irq(); + +#if(CY_BLE_STACK_MODE_IPC) + /* Start BLE Controller for dual core mode */ + Cy_BLE_Start(NULL); +#endif /* (CY_BLE_STACK_MODE_IPC)*/ + + COMM_InitIPCMessages(); + + /* Enable CM4. CY_CORTEX_M4_APPL_ADDR must be updated if CM4 memory layout is changed. */ + Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR); + + while(true) + { +#if(CY_BLE_STACK_MODE_IPC) + /* Process BLE events continuously for controller in dual core mode */ + Cy_BLE_ProcessEvents(); +#endif /* CY_BLE_STACK_MODE_IPC */ + + /* To achieve low power in the device */ + Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT); + } +} + diff --git a/2020TPCAppNoDFU.cydsn/main_cm4.c b/2020TPCAppNoDFU.cydsn/main_cm4.c new file mode 100644 index 0000000..2f41a28 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/main_cm4.c @@ -0,0 +1,107 @@ +/** \file + * \brief This file provides the entry point for the application running on the Cortex-M4 core. + * + * ## CapSense + * To tune the CapSense buttons, do the following: + * 1. Define `TUNE_CAPSENSE` below. + * 2. Rebuild the project, and load it on to your board. + * 3. Right-click on the `CapSense` component on the "CapSense" schematic page in `TopDesign.cysch`, and choose "Launch Tuner". + * 4. Follow the instructions in [AN85951 - PSoC 4 and PSoC 6 MCU CapSense Design Guide](https://www.cypress.com/documentation/application-notes/an85951-psoc-4-and-psoc-6-mcu-capsense-design-guide) to complete the tuning. + * + */ + + +/* Include Files */ +#include "KTag.h" + + +// See the instructions at the top of this file for how to tune CapSense--this is only part of what you need. +//#define TUNE_CAPSENSE + + +#ifndef TUNE_CAPSENSE +int main() +{ + CONFIG_InitTasks(); + + /* Enable global interrupts. */ + __enable_irq(); + + COMM_InitIPCMessages(); + + CONFIG_RunTasks(); +} +#endif // TUNE_CAPSENSE + + +void vApplicationIdleHook(void) +{ + CyDelay(500); +} + + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + /* Halt the CPU */ + CY_ASSERT(0); +} + + +void vApplicationMallocFailedHook( void ) +{ + /* Halt the CPU */ + CY_ASSERT(0); +} + + +#ifdef TUNE_CAPSENSE +int main() +{ + uint8 header[] = {0x0Du, 0x0Au}; + uint8 tail[] = {0x00u, 0xFFu, 0xFFu}; + + __enable_irq(); /* Enable global interrupts. */ + + UART_Console_Start(); /* Start UART SCB Component */ + CapSense_Start(); /* Initialize Component */ + CapSense_ScanAllWidgets(); /* Scan all widgets */ + + for(;;) + { + /* Do this only when a scan is done */ + if(CapSense_NOT_BUSY == CapSense_IsBusy()) + { + CapSense_ProcessAllWidgets(); /* Process all widgets */ + + /* Send packet header */ + UART_Console_PutArrayBlocking((uint8 *)(&header), sizeof(header)); + /* Send packet with CapSense data */ + UART_Console_PutArrayBlocking((uint8 *)(&CapSense_dsRam), sizeof(CapSense_dsRam)); + /* Send packet tail */ + UART_Console_PutArrayBlocking((uint8 *)(&tail), sizeof(tail)); + + CapSense_ScanAllWidgets(); /* Start next scan */ + } + } +} +#endif // TUNE_CAPSENSE + +void vApplicationGetIdleTaskMemory(StaticTask_t** ppxIdleTaskTCBBuffer, StackType_t** ppxIdleTaskStackBuffer, uint32_t* pulIdleTaskStackSize) +{ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[configMINIMAL_STACK_SIZE]; + + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} + +void vApplicationGetTimerTaskMemory(StaticTask_t** ppxTimerTaskTCBBuffer, StackType_t** ppxTimerTaskStackBuffer, uint32_t* pulTimerTaskStackSize) +{ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH]; + + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} \ No newline at end of file diff --git a/2020TPCAppNoDFU.cydsn/mdk/startup_psoc6_01_cm0plus.s b/2020TPCAppNoDFU.cydsn/mdk/startup_psoc6_01_cm0plus.s new file mode 100644 index 0000000..9358665 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/mdk/startup_psoc6_01_cm0plus.s @@ -0,0 +1,321 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm0plus.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0plus Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + + ; External interrupts Description + DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0 + DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1 + DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2 + DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3 + DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4 + DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5 + DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6 + DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7 + DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8 + DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9 + DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10 + DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11 + DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12 + DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13 + DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14 + DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15 + DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16 + DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17 + DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18 + DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19 + DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20 + DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21 + DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22 + DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23 + DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24 + DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25 + DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26 + DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27 + DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28 + DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29 + DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30 + DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP + +HardFault_Handler PROC + EXPORT HardFault_Handler [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT NvicMux0_IRQHandler [WEAK] + EXPORT NvicMux1_IRQHandler [WEAK] + EXPORT NvicMux2_IRQHandler [WEAK] + EXPORT NvicMux3_IRQHandler [WEAK] + EXPORT NvicMux4_IRQHandler [WEAK] + EXPORT NvicMux5_IRQHandler [WEAK] + EXPORT NvicMux6_IRQHandler [WEAK] + EXPORT NvicMux7_IRQHandler [WEAK] + EXPORT NvicMux8_IRQHandler [WEAK] + EXPORT NvicMux9_IRQHandler [WEAK] + EXPORT NvicMux10_IRQHandler [WEAK] + EXPORT NvicMux11_IRQHandler [WEAK] + EXPORT NvicMux12_IRQHandler [WEAK] + EXPORT NvicMux13_IRQHandler [WEAK] + EXPORT NvicMux14_IRQHandler [WEAK] + EXPORT NvicMux15_IRQHandler [WEAK] + EXPORT NvicMux16_IRQHandler [WEAK] + EXPORT NvicMux17_IRQHandler [WEAK] + EXPORT NvicMux18_IRQHandler [WEAK] + EXPORT NvicMux19_IRQHandler [WEAK] + EXPORT NvicMux20_IRQHandler [WEAK] + EXPORT NvicMux21_IRQHandler [WEAK] + EXPORT NvicMux22_IRQHandler [WEAK] + EXPORT NvicMux23_IRQHandler [WEAK] + EXPORT NvicMux24_IRQHandler [WEAK] + EXPORT NvicMux25_IRQHandler [WEAK] + EXPORT NvicMux26_IRQHandler [WEAK] + EXPORT NvicMux27_IRQHandler [WEAK] + EXPORT NvicMux28_IRQHandler [WEAK] + EXPORT NvicMux29_IRQHandler [WEAK] + EXPORT NvicMux30_IRQHandler [WEAK] + EXPORT NvicMux31_IRQHandler [WEAK] + +NvicMux0_IRQHandler +NvicMux1_IRQHandler +NvicMux2_IRQHandler +NvicMux3_IRQHandler +NvicMux4_IRQHandler +NvicMux5_IRQHandler +NvicMux6_IRQHandler +NvicMux7_IRQHandler +NvicMux8_IRQHandler +NvicMux9_IRQHandler +NvicMux10_IRQHandler +NvicMux11_IRQHandler +NvicMux12_IRQHandler +NvicMux13_IRQHandler +NvicMux14_IRQHandler +NvicMux15_IRQHandler +NvicMux16_IRQHandler +NvicMux17_IRQHandler +NvicMux18_IRQHandler +NvicMux19_IRQHandler +NvicMux20_IRQHandler +NvicMux21_IRQHandler +NvicMux22_IRQHandler +NvicMux23_IRQHandler +NvicMux24_IRQHandler +NvicMux25_IRQHandler +NvicMux26_IRQHandler +NvicMux27_IRQHandler +NvicMux28_IRQHandler +NvicMux29_IRQHandler +NvicMux30_IRQHandler +NvicMux31_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, =Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, =(Heap_Mem + Heap_Size) + LDR R3, =Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END + + +; [] END OF FILE diff --git a/2020TPCAppNoDFU.cydsn/mdk/startup_psoc6_01_cm4.s b/2020TPCAppNoDFU.cydsn/mdk/startup_psoc6_01_cm4.s new file mode 100644 index 0000000..c41752b --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/mdk/startup_psoc6_01_cm4.s @@ -0,0 +1,696 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Power Mode Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END + + +; [] END OF FILE diff --git a/2020TPCAppNoDFU.cydsn/stdio_user.c b/2020TPCAppNoDFU.cydsn/stdio_user.c new file mode 100644 index 0000000..077d110 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/stdio_user.c @@ -0,0 +1,65 @@ +/***************************************************************************//** +* \file stdio_user.c +* \version 1.20 +* +* \brief +* This file provides low level function implementation to retarget +* I/O functions of the standard C run-time library. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "stdio_user.h" + +#if defined (IO_STDOUT_ENABLE) && defined (IO_STDOUT_UART) +/******************************************************************************* +* Function Name: STDIO_PutChar +******************************************************************************** +* +* This function outputs a character through user defined target. +* Note: this is a template function which may be overwritten by the USER in order +* to change the target used in redirecting STDOUT stream. +* +* \param ch +* The character to send. +* +*******************************************************************************/ +void STDIO_PutChar(uint32_t ch) +{ + /* Place the call to your function here. */ + while(0U == Cy_SCB_UART_Put(IO_STDOUT_UART, ch)) + { + /* Wait until FIFO is full */ + } +} +#endif /* IO_STDOUT_ENABLE && IO_STDOUT_UART */ + +#if defined (IO_STDIN_ENABLE) && defined (IO_STDIN_UART) +/******************************************************************************* +* Function Name: STDIO_GetChar +******************************************************************************** +* +* This function retrieves STDIN from a user specified input source. +* Note: this is a template function which may be overwritten by the USER in order +* to change the target used in redirecting STDIN stream. +* +* \return +* The received character. +* +*******************************************************************************/ +uint32_t STDIO_GetChar(void) +{ + /* Place the call to your function here. */ + while(0UL == Cy_SCB_UART_GetNumInRxFifo(IO_STDIN_UART)) + { + } + return (Cy_SCB_UART_Get(IO_STDIN_UART)); +} +#endif /* IO_STDIN_ENABLE && IO_STDIN_UART */ + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/stdio_user.h b/2020TPCAppNoDFU.cydsn/stdio_user.h new file mode 100644 index 0000000..a4c3bc1 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/stdio_user.h @@ -0,0 +1,200 @@ +/***************************************************************************//** +* \file stdio_user.h +* \version 1.20 +* +* \brief +* This file provides configuration macros and function prototypes to retarget +* I/O functions of the standard C run-time library. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#ifndef STDIO_USER_H +#define STDIO_USER_H +/** +* \addtogroup group_retarget_io +* \{ +* Retarget the I/O functions of the standard C run-time library to the user-defined target. +* +* Application code frequently uses standard I/O library functions, such as +* scanf()/printf() to perform input/output operations. This utility allows you to retarget +* standard C run-time library I/O functions to the user-defined target. +* +*

Design

+* The file retarget.c defines functions that replace weakly linked I/O functions +* in the standard library (i.e. _write() and _read()). The functions in +* retarget.c in turn call the STDIO_PutChar() and STDIO_GetChar() +* implemented in stdio_user.c. +* +*

Use

+* The files for this utility are in this folder: +* \/utilities/retarget_io +* +* The first thing you need to do is add the source files to your project. +* +* For a 3rd Party IDE, add the retarget_io folder to your list of include +* paths and add the files retarget.c and stdio_user.c to your project. +* +* For PSoC Creator, create a PSoC Creator project. Then click +* Project > Build Setting > Peripheral Driver Library. To +* add Retarget I/O source files to your project, enable it as shown on the +* screenshot below. After selecting Retarget I/O in the PDL software package +* list, click OK and build the project. The Retarget I/O source files are +* added to your project and are available for modification. +* ![Figure 1. Build Settings dialog in PSoC Creator](retarget_io_build_settings.png) +* +* For ModusToolbox, create or open existing ModusToolbox project. Open +* Middleware Selector (Project > ModusToolbox Middleware Selector), +* select Retarget I/O item, and click OK (see the screenshot below). +* The Retarget I/O source files are added to your project and are available for +* modification. +* ![Figure 2. Middleware Selector dialog in ModusToolbox](retarget_io_middleware_selector.png) +* +* There are multiple serial communication blocks (SCB) available. By default +* the Retarget I/O files use SCB0. The stdio_user.h file defines these macros: +* \code #define IO_STDOUT_UART SCB0 +* #define IO_STDIN_UART SCB0 \endcode +* +* Modify these macros to use the SCB in your design. Standard library I/O +* calls are then retargeted to that SCB. +* +* If you use PSoC Creator, the code generator creates a symbol UART_HW +* to represent the SCB block used in your design. In this case you can +* include "project.h" to access that symbol, and modify the macros like this: +* \code #define IO_STDOUT_UART UART_HW +* #define IO_STDIN_UART UART_HW \endcode +* +* The functions implemented in retarget.c are weakly linked. If you wish +* to modify those functions, you can write your own implementation, and +* not use stdio_user.c at all. +* +* \note The standard library is not standard in how it treats an I/O stream. +* Some implement a data buffer by default. The buffer is not flushed until +* it is full. In that case it may appear that your I/O is not working. You +* should be aware of how the library buffers data, and you should identify +* a buffering strategy and buffer size for a specified stream. If you +* supply a buffer, it must exist until the stream is closed. The following +* line of code disables the buffer for the standard library that +* accompanies the GCC compiler: +* \code setvbuf( stdin, NULL, _IONBF, 0 ); \endcode +* +* +*

MISRA-C Compliance

+* The Retarget IO utility has the following specific deviations: +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
5.6ANo identifier in one name space should have the same spelling +* as an identifier in another name space, with the exception of +* structure member and union member names.Violated since the utility redefines the function declared in standard +* library.
6.3Atypedefs that indicate size and signedness should be used in +* place of the basic numerical type.Basic numerical types are used to match the definition of the +* function with the prototype defined in the standard library.
8.8RAn external object or function shall be declared in one and only one file.The _write is declared in the standard i/o library with +* weak attribute and is redefined in the utility.
14.2RAll non-null statements shall either:
(a) have at least one +* side-effect however executed, or
(b) cause control flow to change.		The unused function parameters are cast to void. This statement +* has no side-effect and is used to suppress a compiler warning.
20.9RThe input/output library shall not be used in +* production code.stdio.h file is included to connect the standard function +* definition with their declaration in the standard library.
+* +*

Changelog

+* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
1.20Changed include path for cy_scb_uart.h to reflect the PDL source code structure
1.10Added STDIN support
1.0Initial version
+* \} +*/ +#include +#include "cy_device_headers.h" + +/* Must remain uncommented to use this utility */ +#define IO_STDOUT_ENABLE +#define IO_STDIN_ENABLE +#define IO_STDOUT_UART UART_Console_HW +#define IO_STDIN_UART UART_Console_HW + +#if defined(IO_STDOUT_ENABLE) || defined(IO_STDIN_ENABLE) +#if defined(IO_STDOUT_UART) || defined(IO_STDIN_UART) +#include "cy_scb_uart.h" +#endif /* IO_STDOUT_UART || IO_STDIN_UART */ +#endif /* IO_STDOUT_ENABLE || IO_STDIN_ENABLE */ + +/* Controls whether CR is added for LF */ +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif /* STDOUT_CR_LF */ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined (IO_STDOUT_ENABLE) && defined (IO_STDOUT_UART) +void STDIO_PutChar(uint32_t ch); +#endif /* IO_STDOUT_ENABLE && IO_STDOUT_UART */ + +#if defined (IO_STDIN_ENABLE) && defined (IO_STDIN_UART) +uint32_t STDIO_GetChar(void); +#endif /* IO_STDIN_ENABLE && IO_STDIN_UART */ + +#if defined(__cplusplus) +} +#endif + +#endif /* STDIO_USER_H */ + + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/system_psoc6.h b/2020TPCAppNoDFU.cydsn/system_psoc6.h new file mode 100644 index 0000000..73d1263 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/system_psoc6.h @@ -0,0 +1,648 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.20 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is _IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#define CY_CORTEX_M4_APPL_ADDR ( CY_FLASH_BASE + CY_FLASH_SIZE / 2U) /* <<< Half of flash is reserved for the Cortex-M0+ application */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +#if defined(__ARMCC_VERSION) + extern void SystemInit(void) __attribute__((constructor)); +#else + extern void SystemInit(void); +#endif /* (__ARMCC_VERSION) */ + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/system_psoc6_cm0plus.c b/2020TPCAppNoDFU.cydsn/system_psoc6_cm0plus.c new file mode 100644 index 0000000..038e7b4 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/system_psoc6_cm0plus.c @@ -0,0 +1,699 @@ +/***************************************************************************//** +* \file system_psoc6_cm0plus.c +* \version 2.20 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4() +*******************************************************************************/ +#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL) +#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL) +#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL) + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* +* Initializes the system: +* - Restores FLL registers to the default state. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) + if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision()) + { + /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */ + IPC_STRUCT7->DATA = 0UL; + /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */ + IPC_STRUCT7->RELEASE = 0UL; + } +#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t slowClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Slow Clock Divider */ + slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + + pathFreqHz = pathFreqHz / periClkDiv; + cy_PeriClkFreqHz = pathFreqHz; + pathFreqHz = pathFreqHz / slowClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/******************************************************************************* +* Function Name: Cy_SysGetCM4Status +****************************************************************************//** +* +* Returns the Cortex-M4 core power mode. +* +* \return \ref group_system_config_cm4_status_macro +* +*******************************************************************************/ +uint32_t Cy_SysGetCM4Status(void) +{ + uint32_t regValue; + + /* Get current power mode */ + regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk; + + return (regValue); +} + + +/******************************************************************************* +* Function Name: Cy_SysEnableCM4 +****************************************************************************//** +* +* Sets vector table base address and enables the Cortex-M4 core. +* +* \note If the CPU is already enabled, it is reset and then enabled. +* +* \param vectorTableOffset The offset of the vector table base address from +* memory address 0x00000000. The offset should be multiple to 1024 bytes. +* +*******************************************************************************/ +void Cy_SysEnableCM4(uint32_t vectorTableOffset) +{ + uint32_t regValue; + uint32_t interruptState; + uint32_t cpuState; + + CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL); + + interruptState = Cy_SysLib_EnterCriticalSection(); + + cpuState = Cy_SysGetCM4Status(); + if (CY_SYS_CM4_STATUS_ENABLED == cpuState) + { + Cy_SysResetCM4(); + } + + CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset; + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_ENABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysDisableCM4 +****************************************************************************//** +* +* Disables the Cortex-M4 core and waits for the mode to take the effect. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the +* CPU. +* +*******************************************************************************/ +void Cy_SysDisableCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_DISABLED; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysRetainCM4 +****************************************************************************//** +* +* Retains the Cortex-M4 core and exists without waiting for the mode to take +* effect. +* +* \note The retained mode can be entered only from the enabled mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysRetainCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RETAINED; + CPUSS->CM4_PWR_CTL = regValue; + + Cy_SysLib_ExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: Cy_SysResetCM4 +****************************************************************************//** +* +* Resets the Cortex-M4 core and waits for the mode to take the effect. +* +* \note The reset mode can not be entered from the retained mode. +* +* \warning Do not call the function while the Cortex-M4 is executing because +* such a call may corrupt/abort a pending bus-transaction by the CPU and cause +* unexpected behavior in the system including a deadlock. Call the function +* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use +* the \ref group_syspm Power Management (syspm) API to put the CPU into the +* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU. +* +*******************************************************************************/ +void Cy_SysResetCM4(void) +{ + uint32_t interruptState; + uint32_t regValue; + + interruptState = Cy_SysLib_EnterCriticalSection(); + + regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk); + regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN); + regValue |= CY_SYS_CM4_STATUS_RESET; + CPUSS->CM4_PWR_CTL = regValue; + + while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL) + { + /* Wait for the power mode to take effect */ + } + + Cy_SysLib_ExitCriticalSection(interruptState); +} +#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */ + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm0 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm0(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR); +} +#endif + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/2020TPCAppNoDFU.cydsn/system_psoc6_cm4.c b/2020TPCAppNoDFU.cydsn/system_psoc6_cm4.c new file mode 100644 index 0000000..c4d8c11 --- /dev/null +++ b/2020TPCAppNoDFU.cydsn/system_psoc6_cm4.c @@ -0,0 +1,542 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.20 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if (rootPath == 1UL) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} + +#endif /* defined (__ARMCC_VERSION) */ + + +/* [] END OF FILE */ diff --git a/Keys/Keys_README.md b/Keys/Keys_README.md new file mode 100644 index 0000000..9fcb7ac --- /dev/null +++ b/Keys/Keys_README.md @@ -0,0 +1,4 @@ +# About the Keys + +This is the folder where the keys go. Thay are not here. If you need them, +[send a message to Joe](https://forum.ktag.clubk.club/new-message?username=joe&title=2020TPC%20Keys&body=I%20need%20the%202020TPC%20keys.%20Here%27s%20why%3A) and tell him why. \ No newline at end of file diff --git a/README.md b/README.md index 28230cc..da8e3d6 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,53 @@ -# 2020TPC-SW +# 2020TPC Software -Software for the 2020TPC using PSoC Creator. \ No newline at end of file +## Overview + +This is software for the [2020TPC](https://git.ktag.clubk.club/Hardware/2020TPC-HW-Body/) using +[PSoC™ Creator](https://www.infineon.com/cms/en/design-support/tools/sdk/psoc-software/psoc-creator/)†. + +The primary documentation for the 2020TPC is on the KTag website at https://ktag.clubk.club/Devices/2020TPC/. + +You can ask questions (and get answers!) about this software on the KTag forum at https://forum.ktag.clubk.club/c/software/. + +## License: [AGPL-3.0-or-later](https://spdx.org/licenses/AGPL-3.0-or-later.html) + +This software is part of the KTag project, a DIY laser tag game with customizable features and wide interoperability. + +🛡️ 🃞 + +Copyright © 2020-2025 Joseph P. Kearney and the KTag developers. + +This program is free software: you can redistribute it and/or modify it under +the terms of the GNU Affero General Public License as published by the Free +Software Foundation, either version 3 of the License, or (at your option) any +later version. + +This program is distributed in the hope that it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU Affero General Public License for more +details. + +There should be a copy of the GNU Affero General Public License in the [LICENSE](LICENSE) +file in the root of this repository. If not, see . + +## Licensed Software + +This software makes use of the following licensed software components and libraries: + +| Name | Version | URL +|----------------------------|---------:|----------------------------------------------- +| Cypress PSoC™ Creator | 4.4.0.80 | https://www.infineon.com/cms/en/design-support/tools/sdk/psoc-software/psoc-creator/ +| PSoC™ 6 Peripheral Driver Library (PDL) for PSoC™ Creator
(installed in C:\Program Files (x86)\Cypress\PDL\3.1.7) | 3.1.7 | https://www.infineon.com/cms/en/design-support/software/device-driver-libraries/psoc-6-peripheral-driver-library-pdl-for-psoc-creator/ + +## Open-Source Software + +This software makes use of the following open-source software libraries and components: + +| Name | Version | License ([SPDX](https://spdx.org/licenses/)) | URL +|----------------------------|--------:|--------------------------------------------------------------------------|--------------------------------------------- +| SystemK | 1.0 | [AGPL-3.0-or-later](https://spdx.org/licenses/AGPL-3.0-or-later.html) | https://git.ktag.clubk.club/Software/SystemK/ +| FreeRTOS™ | 10.0.1 | [MIT](https://spdx.org/licenses/MIT.html) | https://www.freertos.org/ + + + +† PSOC™ Creator is a trademark of Infineon Technologies AG. All trade names, trademarks, and registered trademarks mentioned in this documentation are the property of their respective owners, and are hereby acknowledged. \ No newline at end of file diff --git a/autocode.py b/autocode.py new file mode 100644 index 0000000..85580f3 --- /dev/null +++ b/autocode.py @@ -0,0 +1,392 @@ +#!/usr/bin/env python +"""Generates C code for the nonvolatile memory (NVM) data structures. +""" + +# Imports +import argparse +import codecs +import datetime +import glob +import logging +import os +import pathlib +import pprint +import shutil + +import colorama +import openpyxl + +APP_NAME = "KTag Autocode Generator" +__author__ = "Joe Kearney" +__version__ = "00.02" + +NVM_SPREADSHEET_FILENAME = "2020TPC Nonvolatile Memory.xlsx" +SCRIPT_PATH = os.path.dirname(os.path.realpath(__file__)) +DESTINATION_PATHS = ("2020TPCApp1.cydsn/NVM", "2020TPCAppNoDFU.cydsn/NVM") + +# See https://developer.arm.com/documentation/dui0472/m/c-and-c---implementation-details/basic-data-types-in-arm-c-and-c-- +# and +# https://en.wikibooks.org/wiki/C_Programming/inttypes.h +CortexM_type_sizes_in_bytes = { + "bool": 1, + "int8_t": 1, + "uint8_t": 1, + "int16_t": 2, + "uint16_t": 2, + "int32_t": 4, + "uint32_t": 4, + "float": 4, + "int64_t": 8, + "uint64_t": 8, + "double": 8, +} + +# Initialize the pretty-printer. +pp = pprint.PrettyPrinter(indent=4) + + +# Openpyxl helper function from https://stackoverflow.com/questions/23562366/how-do-i-get-value-present-in-a-merged-cell +def getValueWithMergeLookup(sheet, cell): + idx = cell.coordinate + for my_range in sheet.merged_cells.ranges: + merged_cells = list(openpyxl.utils.rows_from_range(str(my_range))) + for row in merged_cells: + if idx in row: + # If this is a merged cell, + # return the first cell of the merge range + coordinates_of_first_cell = merged_cells[0][0] + return sheet[coordinates_of_first_cell].value + + return sheet[idx].value + + +# Set up logging. +rootLogger = logging.getLogger() +rootLogger.setLevel(logging.DEBUG) +fileHandler = logging.FileHandler('Autocode.log', mode='w') +logFormatter = logging.Formatter( + '{asctime} {name} {levelname:8s} {message}', style='{') +fileHandler.setFormatter(logFormatter) +rootLogger.addHandler(fileHandler) +consoleHandler = logging.StreamHandler() +consoleHandler.setFormatter(logFormatter) +rootLogger.addHandler(consoleHandler) +logger = logging.getLogger('autocode.py') + + +def main(): + version_information = APP_NAME + ' version ' + __version__ + + logger.info(version_information) + + colorama.init(autoreset=True) + + parser = argparse.ArgumentParser( + description='Generate autocode', epilog=version_information) + commands = parser.add_mutually_exclusive_group() + commands.add_argument( + '-n', '--nvm', help='Generate nonvolatile memory autocode', action='store_true') + parser.add_argument('-v', '--version', action='version', + version=version_information) + + args = parser.parse_args() + d = vars(args) + + if (d['nvm'] == True): + generate_NVM_autocode() + else: + # If no commands were specified, show the help and exit. + parser.parse_args(['-h']) + + +def generate_NVM_autocode(): + logger.info('Generating nonvolatile memory autocode...') + + wb = openpyxl.load_workbook( + filename=NVM_SPREADSHEET_FILENAME) + ws = wb['NVM'] + + headerColumnsByName = dict() + for rowIndex, row in enumerate(ws.iter_rows(min_row=1, max_row=1), start=1): + for columnIndex, cell in enumerate(row, start=0): + headerColumnsByName[cell.value] = columnIndex + + NVMItemsByID = dict() + NVMLocations = set() + NVMEntriesByLocation = dict() + + for rowIndex, row in enumerate(ws.iter_rows(min_row=2)): + if (row[headerColumnsByName['ID']].value is not None): + item_ID = int(row[headerColumnsByName['ID']].value) + + nvm_item = dict() + nvm_item['ID'] = item_ID + nvm_item['Location'] = row[headerColumnsByName['Location']].value + if nvm_item['Location'] != 'None': + if nvm_item['Location'] not in NVMLocations: + # This is a new location. + NVMLocations.add(nvm_item['Location']) + NVMEntriesByLocation[nvm_item['Location']] = list() + + nvm_item['Name'] = row[headerColumnsByName['Item Name']].value + nvm_item['Item Name in Code'] = nvm_item['Name'].replace( + ' ', '_') + nvm_item['Item Shorthand Macro'] = 'NVM_' + \ + nvm_item['Name'].upper().replace(' ', '_') + nvm_item['Entry'] = row[headerColumnsByName['Entry Name']].value + nvm_item['Entry Name in Code'] = 'NVM_' + \ + nvm_item['Entry'].replace(' ', '_') + nvm_item['Entry Type Name'] = nvm_item['Entry Name in Code'] + '_T' + nvm_item['RAM Entry Name in Code'] = 'NVM_' + \ + nvm_item['Entry'].replace(' ', '_') + nvm_item['Datatype'] = row[headerColumnsByName['Datatype']].value + + # Validate the datatype and get the size. + if nvm_item['Datatype'] not in CortexM_type_sizes_in_bytes.keys(): + logger.error('NVM item ' + str(item_ID) + ' on row ' + str(rowIndex + 2) + + ' has unknown datatype \"' + str(nvm_item['Datatype']) + '\"!') + else: + nvm_item['Data Size in Bytes'] = CortexM_type_sizes_in_bytes[nvm_item['Datatype']] + + nvm_item['Default Value'] = row[headerColumnsByName['Default Value']].value + nvm_item['Description'] = row[headerColumnsByName['Description']].value + nvm_item['Notes'] = row[headerColumnsByName['Notes']].value + + # pp.pprint(nvm_item) + if nvm_item['Entry'] not in NVMEntriesByLocation[nvm_item['Location']]: + NVMEntriesByLocation[nvm_item['Location']].append( + nvm_item['Entry']) + NVMItemsByID[item_ID] = nvm_item + + for location in NVMLocations: + logger.info('Generating code for ' + location + ' NVM.') + + with codecs.open('NVM_' + location + 'EEPROMEntries.h', 'w', "utf-8") as f: + f.write("/*\n") + f.write( + " * __ ________ _____ ______ __ \n") + f.write( + " * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ \n") + f.write( + " * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ \n") + f.write( + " * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ \n") + f.write( + " * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ \n") + f.write( + " * /____/ \n") + f.write(" *\n") + f.write( + " * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞\n") + f.write(" *\n") + f.write(" */\n") + + f.write('\n') + f.write('/** \\file\n') + f.write( + ' * \\brief [Autogenerated] This file declares the ' + location + ' EEPROM entries.\n') + f.write(' *\n') + f.write( + ' * \\note AUTOGENERATED: This file was generated automatically on ' + + '{dt:%A}, {dt:%B} {dt.day}, {dt.year} at {dt:%r}'.format(dt=datetime.datetime.now()) + + '.\n') + f.write(' * DO NOT MODIFY THIS FILE MANUALLY!\n') + f.write(' */\n') + f.write('\n') + f.write('#ifndef NVM_' + location.upper() + 'EEPROMENTRIES_H\n') + f.write('#define NVM_' + location.upper() + 'EEPROMENTRIES_H\n') + f.write('\n') + f.write('#ifdef __cplusplus\n') + f.write('extern "C" {\n') + f.write('#endif\n') + f.write('\n') + f.write('/* Preprocessor and Type Definitions */\n') + f.write('\n') + + for entry in NVMEntriesByLocation[location]: + entry_name_in_code = 'NVM_' + entry.replace(' ', '_') + entry_type_name = entry_name_in_code + '_T' + f.write('typedef struct __attribute__((packed))\n') + f.write('{\n') + # List all the items in this entry. + for item_ID in NVMItemsByID: + item = NVMItemsByID[item_ID] + if item['Entry'] == entry: + if item['Description'] is not None: + f.write(' //! ' + item['Description'] + '\n') + f.write(' ' + item['Datatype'] + + ' ' + item['Item Name in Code'] + ';\n') + f.write('} ' + entry_type_name + ';\n') + f.write('\n') + + f.write('\n') + f.write('/* Include Files */\n') + f.write('\n') + f.write('/* Public Variables */\n') + f.write('\n') + + for entry in NVMEntriesByLocation[location]: + entry_name_in_code = 'NVM_' + entry.replace(' ', '_') + entry_type_name = entry_name_in_code + '_T' + f.write('extern NVM_EEPROMEntry_T ' + + entry_name_in_code + ';\n') + + f.write('\n') + f.write('extern NVM_EEPROMEntry_T * const NVM_' + + location + 'EEPROMEntries[];\n') + f.write('extern const uint8_t NVM_N_' + + location.upper() + '_EEPROM_ENTRIES;\n') + f.write('\n') + f.write('// Shorthand macros, to save you time.\n') + + for item_ID in NVMItemsByID: + item = NVMItemsByID[item_ID] + if item['Location'] == location: + f.write('#define ' + item['Item Shorthand Macro'] + ' (((' + item['Entry Type Name'] + + '*)' + item['Entry Name in Code'] + '.Value)->' + item['Item Name in Code'] + ')\n') + f.write('#define ' + item['Item Shorthand Macro'] + + '_ENTRY_PTR (&' + item['Entry Name in Code'] + ')\n') + f.write('\n') + + f.write('\n') + f.write('#ifdef __cplusplus\n') + f.write('}\n') + f.write('#endif\n') + f.write('\n') + f.write('#endif // NVM_' + location.upper() + 'EEPROMENTRIES_H\n') + f.write('\n') + + with codecs.open('NVM_' + location + 'EEPROMEntries.c', 'w', "utf-8") as f: + f.write("/*\n") + f.write( + " * __ ________ _____ ______ __ \n") + f.write( + " * / //_/_ __/___ _____ _ / ___/____ __ _______________ / ____/___ ____/ /__ \n") + f.write( + " * / ,< / / / __ `/ __ `/ \__ \/ __ \/ / / / ___/ ___/ _ \ / / / __ \/ __ / _ \ \n") + f.write( + " * / /| | / / / /_/ / /_/ / ___/ / /_/ / /_/ / / / /__/ __/ / /___/ /_/ / /_/ / __/ \n") + f.write( + " * /_/ |_|/_/ \__,_/\__, / /____/\____/\__,_/_/ \___/\___/ \____/\____/\__,_/\___/ \n") + f.write( + " * /____/ \n") + f.write(" *\n") + f.write( + " * 🃞 THIS FILE IS PART OF THE KTAG SOURCE CODE. Visit https://ktag.clubk.club/ for more. 🃞\n") + f.write(" *\n") + f.write(" */\n") + + f.write('\n') + f.write('/** \\file\n') + f.write( + ' * \\brief [Autogenerated] This file defines the ' + location + ' EEPROM entries.\n') + f.write(' *\n') + f.write( + ' * \\note AUTOGENERATED: This file was generated automatically on ' + + '{dt:%A}, {dt:%B} {dt.day}, {dt.year} at {dt:%r}'.format(dt=datetime.datetime.now()) + + '.\n') + f.write(' * DO NOT MODIFY THIS FILE MANUALLY!\n') + f.write(' */\n') + f.write('\n') + + f.write('/* Include Files */\n') + f.write('#include "KTag.h"\n') + f.write('\n') + f.write('/* EEPROM Entries */\n') + f.write('\n') + f.write('/** \defgroup NVM_' + location.upper() + + '_EEPROM NVM ' + location + ' EEPROM\n') + f.write(' *\n') + f.write(' * The ' + location + + ' EEPROM is divided into logical "entries", represented by instances of the #NVM_EEPROMEntry_T type.\n') + f.write(' * At startup, these entries are loaded into their respective RAM copies by NVM_Init' + + location + 'EEPROM(). The application\n') + f.write(' * then updates the RAM copies directly, and requests that the NVM_' + + location + 'EEPROMTask() save these back to the EEPROM\n') + f.write(' * when necessary.\n') + f.write(' * @{ */\n') + f.write('\n') + + # Here is the magic: keep track of the locations in EE as we create the data structures. + current_EE_address_in_bytes = 0 + + for entry in NVMEntriesByLocation[location]: + entry_name_in_code = 'NVM_' + entry.replace(' ', '_') + entry_RAM_name_in_code = 'RAM_' + entry.replace(' ', '_') + entry_default_name_in_code = 'DEFAULT_' + \ + entry.replace(' ', '_') + entry_type_name = entry_name_in_code + '_T' + f.write('static ' + entry_type_name + ' ' + + entry_RAM_name_in_code + ';\n') + f.write('\n') + f.write('static const ' + entry_type_name + ' ' + + entry_default_name_in_code + ' = \n') + f.write('{\n') + + # Assign defaults to all the items in this entry, and calculate the total size. + entry_size_in_bytes = 0 + CRC_size_in_bytes = 2 + for item_ID in NVMItemsByID: + item = NVMItemsByID[item_ID] + if item['Entry'] == entry: + if item['Description'] is not None: + f.write(' //! ' + item['Description'] + '\n') + f.write( + ' .' + item['Item Name in Code'] + ' = ' + str(item['Default Value']) + ',\n') + entry_size_in_bytes += item['Data Size in Bytes'] + + f.write('};\n') + f.write('\n') + + f.write('NVM_EEPROMEntry_T ' + entry_name_in_code + ' = \n') + f.write('{\n') + f.write(' //! Size == sizeof(' + entry_type_name + ')\n') + f.write(' .Size = ' + str(entry_size_in_bytes) + ',\n') + f.write(' .EE_Address = ' + + str(current_EE_address_in_bytes) + ',\n') + current_EE_address_in_bytes += entry_size_in_bytes + f.write(' .EE_CRC_Address = ' + + str(current_EE_address_in_bytes) + ',\n') + current_EE_address_in_bytes += CRC_size_in_bytes + f.write(' .Value = (uint8_t *)&' + + entry_RAM_name_in_code + ',\n') + f.write(' .Default = (uint8_t *)&' + + entry_default_name_in_code + ',\n') + f.write(' .State = NVM_STATE_UNINITIALIZED\n') + f.write('};\n') + + f.write('\n') + f.write('/** @} */\n') + f.write('\n') + f.write('NVM_EEPROMEntry_T * const NVM_' + + location + 'EEPROMEntries[] =\n') + f.write('{\n') + + for entry in NVMEntriesByLocation[location]: + entry_name_in_code = 'NVM_' + entry.replace(' ', '_') + f.write(' &' + entry_name_in_code + ',\n') + + f.write('};\n') + f.write('\n') + f.write('//! Size of the #NVM_' + location + + 'EEPROMEntries array (i.e. the number of ' + location + ' EEPROM entries).\n') + f.write('const uint8_t NVM_N_' + location.upper() + '_EEPROM_ENTRIES = (uint8_t) (sizeof(NVM_' + + location + 'EEPROMEntries) / sizeof(NVM_EEPROMEntry_T *));\n') + f.write('\n') + + for destination in DESTINATION_PATHS: + destination = os.path.normpath(os.path.join(SCRIPT_PATH, destination)) + logger.info("Copying files to " + destination + ".") + for file in glob.glob("NVM_*.[ch]"): + shutil.copy2(file, destination) + + logger.info("Cleaning up.") + for file in glob.glob("NVM_*.[ch]"): + path = pathlib.Path(file) + path.unlink() + + logger.info('Nonvolatile memory autocode generation completed.') + + +if __name__ == "__main__": + main()