Initial public release.
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Joe Kearney
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255 changed files with 68595 additions and 2 deletions
260
2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROM.c
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260
2020TPCAppNoDFU.cydsn/NVM/NVM_OnChipEEPROM.c
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/** \file
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* \brief This file contains functions that manage the on-chip EEPROM.
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*
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*/
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/* Include Files */
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#include "KTag.h"
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/* Local Definitions and Constants */
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/* External Variables [Only if necessary!] */
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/* External Function Prototypes [Only if necessary!] */
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/* Public Variables */
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//! Mutex controlling access to the EEPROM to ensure data/CRC integrity.
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SemaphoreHandle_t xSemaphoreOnChipEEPROMLock;
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TaskHandle_t NVM_OnChipEEPROM_Task_Handle;
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volatile bool NVM_IsOnChipEEPROMInitialized = false;
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/* Private Variables */
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static QueueHandle_t xQueueOnChipEEPROM;
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#if CY_PSOC4
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const uint8_t Emulated_EEPROM_Storage[On_Chip_Emulated_EEPROM_PHYSICAL_SIZE]
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__ALIGNED(CY_FLASH_SIZEOF_ROW) = {0u};
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#endif // CY_PSOC4
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/* Private Function Prototypes */
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/* Inline Functions */
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#if CY_PSOC4
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//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination.
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static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n)
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{
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On_Chip_Emulated_EEPROM_Read(source, destination, n);
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}
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//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination.
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static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n)
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{
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On_Chip_Emulated_EEPROM_Write(destination, source, n);
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}
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#endif // CY_PSOC4
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#if CY_PSOC5
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//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination.
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static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n)
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{
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for (uint_fast16_t i = 0; i < n; i++)
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{
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uint8_t temp = On_Chip_EEPROM_ReadByte(source + i);
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*(destination + i) = temp;
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}
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}
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//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination.
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static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n)
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{
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for (uint_fast16_t i = 0; i < n; i++)
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{
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On_Chip_EEPROM_WriteByte(*(source + i), destination + i);
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}
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}
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#endif // CY_PSOC5
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#if CY_PSOC6
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//! Reads a block of \a n bytes from EEPROM address \a source to SRAM \a destination.
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static inline void EEPROM_read_block(uint8_t * destination, uint16_t source, size_t n)
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{
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cy_en_em_eeprom_status_t result = On_Chip_EEPROM_Read(source, destination, n);
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if (result != CY_EM_EEPROM_SUCCESS)
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{
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CY_ASSERT(0);
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}
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}
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//! Writes a block of \a n bytes from SRAM \a source to EEPROM address \a destination.
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static inline void EEPROM_write_block(uint8_t * source, uint16_t destination, size_t n)
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{
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cy_en_em_eeprom_status_t result = On_Chip_EEPROM_Write(destination, source, n);
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if (result != CY_EM_EEPROM_SUCCESS)
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{
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CY_ASSERT(0);
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}
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}
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#endif // CY_PSOC6
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/* Public Functions */
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//! Sets up the on-chip EEPROM, but does not read from it (yet).
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void NVM_InitOnChipEEPROM(void)
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{
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/// Create a mutex-type semaphore.
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xSemaphoreOnChipEEPROMLock = xSemaphoreCreateMutex();
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if (xSemaphoreOnChipEEPROMLock == NULL)
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{
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CY_ASSERT(0);
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}
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xQueueOnChipEEPROM = xQueueCreate(5, sizeof(uint8_t));
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#if CY_PSOC4
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On_Chip_Emulated_EEPROM_Init((uint32_t)Emulated_EEPROM_Storage);
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#endif // CY_PSOC4
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#if CY_PSOC5
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On_Chip_EEPROM_Start();
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#endif // CY_PSOC5
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#if CY_PSOC6
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// From the docs: "For PSoC 6, if Emulated EEPROM is selected for EEPROM storage, the start address will be
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// overwritten to some address from Emulated EEPROM flash area."
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On_Chip_EEPROM_Init(0);
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#endif // CY_PSOC6
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}
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//! Handles the ongoing on-chip EEPROM tasks.
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/*!
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* First, it loops through all the on-chip EEPROM entries, and reads them in to RAM.
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* Then, it priodically loops through all the on-chip EEPROM entries, and saves the ones that have been flagged.
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*/
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void NVM_OnChipEEPROMTask(void * pvParameters)
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{
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portBASE_TYPE xStatus;
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static TickType_t xTicksToWait = pdMS_TO_TICKS(NVM_ON_CHIP_EEPROM_TASK_RATE_IN_ms);
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for (uint8_t i = 0; i < NVM_N_ONCHIP_EEPROM_ENTRIES; i++)
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{
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NVM_CRC_t calculated_crc;
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NVM_CRC_t stored_crc = 0;
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EEPROM_read_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size);
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EEPROM_read_block((uint8_t *)&stored_crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(NVM_CRC_t));
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calculated_crc = NVM_CRC_init();
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calculated_crc = NVM_CRC_update(calculated_crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size);
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calculated_crc = NVM_CRC_finalize(calculated_crc);
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if (calculated_crc == stored_crc)
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{
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NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE;
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}
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else
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{
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NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_CRC_FAILED;
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COMM_Console_Print_String("[NVMOn ");
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COMM_Console_Print_UInt16((uint16_t) i);
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COMM_Console_Print_String("] Calculated/Stored CRCs: ");
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COMM_Console_Print_UInt16((uint16_t) calculated_crc);
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COMM_Console_Print_String("/");
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COMM_Console_Print_UInt16((uint16_t) stored_crc);
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COMM_Console_Print_String("\n");
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COMM_Console_Print_String("[NVMOn ");
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COMM_Console_Print_UInt16((uint16_t) i);
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COMM_Console_Print_String("] Applying defaults.\n");
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memcpy(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Default, NVM_OnChipEEPROMEntries[i]->Size);
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// Auto-fix the CRC.
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NVM_SaveOnChipEEPROMEntry(NVM_OnChipEEPROMEntries[i]);
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}
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}
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taskENTER_CRITICAL();
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NVM_IsOnChipEEPROMInitialized = true;
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taskEXIT_CRITICAL();
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while(true)
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{
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uint8_t dummy;
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// Wait for a call to NVM_SaveOnChipEEPROMEntry().
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xStatus = xQueueReceive(xQueueOnChipEEPROM, &dummy, xTicksToWait);
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if (xStatus == pdPASS)
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{
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for (uint8_t i = 0; i < NVM_N_ONCHIP_EEPROM_ENTRIES; i++)
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{
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NVM_CRC_t crc;
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#if (defined CY_PSOC4) || (defined CY_PSOC6)
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if (NVM_OnChipEEPROMEntries[i]->State == NVM_STATE_SAVE_REQUESTED)
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{
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if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE)
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{
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EEPROM_write_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size);
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// Calculate the CRC.
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crc = NVM_CRC_init();
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crc = NVM_CRC_update(crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size);
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crc = NVM_CRC_finalize(crc);
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EEPROM_write_block((uint8_t *)&crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(uint16_t));
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NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE;
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xSemaphoreGive(xSemaphoreOnChipEEPROMLock);
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}
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}
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#endif // (defined CY_PSOC4) || (defined CY_PSOC6)
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#if CY_PSOC5
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// From the component datasheet:
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// "[On_Chip_EEPROM_UpdateTemperature()] updates the store temperature value. This should
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// be called anytime the EEPROM is active and temperature may have changed by more than
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// 10°C."
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if (On_Chip_EEPROM_UpdateTemperature() == CYRET_SUCCESS)
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{
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if (NVM_OnChipEEPROMEntries[i]->State == NVM_STATE_SAVE_REQUESTED)
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{
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if (On_Chip_EEPROM_Query() == CYRET_SUCCESS)
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{
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if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE)
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{
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EEPROM_write_block(NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->EE_Address, NVM_OnChipEEPROMEntries[i]->Size);
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// Calculate the CRC.
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crc = NVM_CRC_init();
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crc = NVM_CRC_update(crc, NVM_OnChipEEPROMEntries[i]->Value, NVM_OnChipEEPROMEntries[i]->Size);
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crc = NVM_CRC_finalize(crc);
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EEPROM_write_block((uint8_t *)&crc, NVM_OnChipEEPROMEntries[i]->EE_CRC_Address, sizeof(uint16_t));
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NVM_OnChipEEPROMEntries[i]->State = NVM_STATE_IDLE;
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xSemaphoreGive(xSemaphoreOnChipEEPROMLock);
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}
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}
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}
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}
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else
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{
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vSerialPutString("ERROR: Couldn't update EEPROM temperature!", 80);
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}
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#endif // CY_PSOC5
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}
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}
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}
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}
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//! Flags the given on-chip EEPROM entry to be saved next time the NVM_OnChipEEPROMTask() is run.
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void NVM_SaveOnChipEEPROMEntry(NVM_EEPROMEntry_T * const this)
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{
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if (xSemaphoreTake(xSemaphoreOnChipEEPROMLock, ( TickType_t ) 1000) == pdTRUE)
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{
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this->State = NVM_STATE_SAVE_REQUESTED;
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xSemaphoreGive(xSemaphoreOnChipEEPROMLock);
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uint8_t dummy = 0;
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xQueueSend(xQueueOnChipEEPROM, &dummy, 0);
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}
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}
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/* Private Functions */
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