Initial public release.
This commit is contained in:
Joe Kearney
parent
7b169e8116
commit
dac4af8d25
255 changed files with 68595 additions and 2 deletions
635
2020TPCApp0.cydsn/gcc/startup_psoc6_01_cm4.S
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635
2020TPCApp0.cydsn/gcc/startup_psoc6_01_cm4.S
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/**************************************************************************//**
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* @file startup_psoc6_01_cm4.S
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* @brief CMSIS Core Device Startup File for
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* ARMCM4 Device Series
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* @version V5.00
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* @date 02. March 2016
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******************************************************************************/
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/*
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* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* Address of the NMI handler */
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#define CY_NMI_HANLDER_ADDR 0x0000000D
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/* The CPU VTOR register */
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#define CY_CPU_VTOR_ADDR 0xE000ED08
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/* Copy flash vectors and data section to RAM */
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#define __STARTUP_COPY_MULTIPLE
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/* Clear single BSS section */
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#define __STARTUP_CLEAR_BSS
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.syntax unified
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.arch armv7-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0x00001000
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x00000400
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .vectors
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.align 2
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.globl __Vectors
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__Vectors:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long CY_NMI_HANLDER_ADDR /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long MemManage_Handler /* MPU Fault Handler */
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.long BusFault_Handler /* Bus Fault Handler */
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.long UsageFault_Handler /* Usage Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long DebugMon_Handler /* Debug Monitor Handler */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts Description */
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.long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
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.long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
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.long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
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.long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
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.long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
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.long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
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.long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
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.long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
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.long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
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.long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
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.long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
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.long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
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.long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
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.long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
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.long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
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.long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
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.long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
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.long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
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.long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
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.long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
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.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
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.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
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.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
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.long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
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.long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
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.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
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.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
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.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
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.long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
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.long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
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.long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
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.long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
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.long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
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.long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
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.long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
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.long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
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.long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
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.long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
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.long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
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.long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
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.long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
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.long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
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.long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
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.long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
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.long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
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.long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
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.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
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.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
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.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
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.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
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.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
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.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
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.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
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.long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
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.long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
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.long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
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.long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
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.long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
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.long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
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.long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
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.long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
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.long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
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.long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
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.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
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.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
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.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
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.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
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.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
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.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
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.long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
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.long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
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.long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
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.long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
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.long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
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.long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
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.long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
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.long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
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.long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
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.long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
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.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
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.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
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.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
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.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
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.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
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.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
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.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
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.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
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.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
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.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
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.long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
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.long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
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.long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
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.long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
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.long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
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.long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
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.long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
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.long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
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.long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
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.long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
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.long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
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.long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
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.long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
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.long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
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.long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
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.long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
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.long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
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.long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
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.long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
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.long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
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.long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
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.long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
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.long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
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.long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
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.long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
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.long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
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.long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
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.long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
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.long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
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.long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
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.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
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.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
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.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
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.long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
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.long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
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.long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
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.long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
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.long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
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.long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
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.long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
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.long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
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.long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
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.long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
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.long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
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.long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
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.long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
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.long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
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.long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
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.long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
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.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
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.long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
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.long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
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.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
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.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
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.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
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.long usb_interrupt_med_IRQHandler /* USB Interrupt */
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.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
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.long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
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.size __Vectors, . - __Vectors
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.equ __VectorsSize, . - __Vectors
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.section .ram_vectors
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.align 2
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.globl __ramVectors
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__ramVectors:
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.space __VectorsSize
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.size __ramVectors, . - __ramVectors
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.text
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.thumb
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.thumb_func
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.align 2
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/*
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* Device startup customization
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*
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* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
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* because this function is executed as the first instruction in the ResetHandler.
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* The PDL is also not initialized to use the proper register offsets.
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* The user of this function is responsible for initializing the PDL and resources before using them.
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*/
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.weak Cy_OnResetUser
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.func Cy_OnResetUser, Cy_OnResetUser
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.type Cy_OnResetUser, %function
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Cy_OnResetUser:
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bx lr
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.size Cy_OnResetUser, . - Cy_OnResetUser
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.endfunc
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/* Reset handler */
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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bl Cy_OnResetUser
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cpsid i
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/* Firstly it copies data from read only memory to RAM. There are two schemes
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* to copy. One can copy more than one sections. Another can only copy
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* one section. The former scheme needs more instructions and read-only
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* data to implement than the latter.
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* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
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#ifdef __STARTUP_COPY_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of triplets, each of which specify:
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* offset 0: LMA of start of a section to copy from
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* offset 4: VMA of start of a section to copy to
|
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* offset 8: size of the section to copy. Must be multiply of 4
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r4, =__copy_table_start__
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ldr r5, =__copy_table_end__
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.L_loop0:
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cmp r4, r5
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bge .L_loop0_done
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ldr r1, [r4]
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ldr r2, [r4, #4]
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ldr r3, [r4, #8]
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.L_loop0_0:
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subs r3, #4
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ittt ge
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ldrge r0, [r1, r3]
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strge r0, [r2, r3]
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bge .L_loop0_0
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adds r4, #12
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b .L_loop0
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.L_loop0_done:
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#else
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/* Single section scheme.
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*
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* The ranges of copy from/to are specified by following symbols
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* __etext: LMA of start of the section to copy from. Usually end of text
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* __data_start__: VMA of start of the section to copy to
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* __data_end__: VMA of end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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.L_loop1:
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cmp r2, r3
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ittt lt
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ldrlt r0, [r1], #4
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strlt r0, [r2], #4
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blt .L_loop1
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#endif /*__STARTUP_COPY_MULTIPLE */
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
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* latter.
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||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
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* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
|
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*/
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#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
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||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Update Vector Table Offset Register. */
|
||||
ldr r0, =__ramVectors
|
||||
ldr r1, =CY_CPU_VTOR_ADDR
|
||||
str r0, [r1]
|
||||
dsb 0xF
|
||||
|
||||
/* Enable the FPU if used */
|
||||
bl Cy_SystemInitFpuEnable
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
bl main
|
||||
|
||||
/* Should never get here */
|
||||
b .
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
|
||||
.weak Cy_SysLib_FaultHandler
|
||||
.type Cy_SysLib_FaultHandler, %function
|
||||
|
||||
Cy_SysLib_FaultHandler:
|
||||
b .
|
||||
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
|
||||
.type Fault_Handler, %function
|
||||
|
||||
Fault_Handler:
|
||||
/* Storing LR content for Creator call stack trace */
|
||||
push {LR}
|
||||
movs r0, #4
|
||||
mov r1, LR
|
||||
tst r0, r1
|
||||
beq .L_MSP
|
||||
mrs r0, PSP
|
||||
b .L_API_call
|
||||
.L_MSP:
|
||||
mrs r0, MSP
|
||||
.L_API_call:
|
||||
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
|
||||
adds r0, r0, #4
|
||||
bl Cy_SysLib_FaultHandler
|
||||
b .
|
||||
.size Fault_Handler, . - Fault_Handler
|
||||
|
||||
.macro def_fault_Handler fault_handler_name
|
||||
.weak \fault_handler_name
|
||||
.set \fault_handler_name, Fault_Handler
|
||||
.endm
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
|
||||
def_fault_Handler HardFault_Handler
|
||||
def_fault_Handler MemManage_Handler
|
||||
def_fault_Handler BusFault_Handler
|
||||
def_fault_Handler UsageFault_Handler
|
||||
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
|
||||
def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
|
||||
def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
|
||||
def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
|
||||
def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
|
||||
def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
|
||||
def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
|
||||
def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
|
||||
def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
|
||||
def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
|
||||
def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
|
||||
def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
|
||||
def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
|
||||
def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
|
||||
def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
|
||||
def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
|
||||
def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
|
||||
def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
|
||||
def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
|
||||
def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
|
||||
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
|
||||
def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
|
||||
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
|
||||
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
|
||||
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
|
||||
def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
|
||||
def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
|
||||
def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
|
||||
def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
|
||||
def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
|
||||
def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
|
||||
def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
|
||||
def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
|
||||
def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
|
||||
def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
|
||||
def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
|
||||
def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
|
||||
def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
|
||||
def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
|
||||
def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
|
||||
def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
|
||||
def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
|
||||
def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
|
||||
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
|
||||
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
|
||||
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
|
||||
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
|
||||
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
|
||||
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
|
||||
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
|
||||
def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
|
||||
def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
|
||||
def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
|
||||
def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
|
||||
def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
|
||||
def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
|
||||
def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
|
||||
def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
|
||||
def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
|
||||
def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
|
||||
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
|
||||
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
|
||||
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
|
||||
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
|
||||
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
|
||||
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
|
||||
def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
|
||||
def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
|
||||
def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
|
||||
def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
|
||||
def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
|
||||
def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
|
||||
def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
|
||||
def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
|
||||
def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
|
||||
def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
|
||||
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
|
||||
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
|
||||
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
|
||||
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
|
||||
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
|
||||
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
|
||||
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
|
||||
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
|
||||
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
|
||||
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
|
||||
def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
|
||||
def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
|
||||
def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
|
||||
def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
|
||||
def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
|
||||
def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
|
||||
def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
|
||||
def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
|
||||
def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
|
||||
def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
|
||||
def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
|
||||
def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
|
||||
def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
|
||||
def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
|
||||
def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
|
||||
def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
|
||||
def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
|
||||
def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
|
||||
def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
|
||||
def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
|
||||
def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
|
||||
def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
|
||||
def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
|
||||
def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
|
||||
def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
|
||||
def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
|
||||
def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
|
||||
def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
|
||||
def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
|
||||
def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
|
||||
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
|
||||
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
|
||||
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
|
||||
def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
|
||||
def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
|
||||
def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
|
||||
def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
|
||||
def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
|
||||
def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
|
||||
def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
|
||||
def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
|
||||
def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
|
||||
def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
|
||||
def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
|
||||
def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
|
||||
def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
|
||||
def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
|
||||
def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
|
||||
def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
|
||||
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
|
||||
def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
|
||||
def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
|
||||
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
|
||||
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
|
||||
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
|
||||
|
||||
.end
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
Loading…
Add table
Add a link
Reference in a new issue