Initial public release.
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Joe Kearney
parent
7b169e8116
commit
dac4af8d25
255 changed files with 68595 additions and 2 deletions
251
2020TPCApp0.cydsn/dfu_cm0p.icf
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2020TPCApp0.cydsn/dfu_cm0p.icf
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/***************************************************************************//**
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* \file dfu_cm0p.icf
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* \version 3.0
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*
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* The linker file for the the IAR compiler.
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*
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* \note The entry point is fixed and starts at 0x10000000. The valid application
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* image should be placed there.
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*
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* \note The linker files included with the PDL template projects must be generic
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* and handle all common use cases. Your project may not use every section
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* defined in the linker files. In that case, you may see warnings during the
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* build process. In your project, you can simply comment out or remove the
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* relevant code in the linker file.
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
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/*******************************************************************************
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* Start of CM4 and CM0+ linker script common region
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*******************************************************************************/
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/*-Memory Regions-*/
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/* Flash */
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define exported symbol __cy_memory_0_start = 0x10000000;
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define exported symbol __cy_memory_0_length = 0x00100000;
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define exported symbol __cy_memory_0_row_size = 0x200;
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/* Emulated EEPROM Flash area */
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define exported symbol __cy_memory_1_start = 0x14000000;
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define exported symbol __cy_memory_1_length = 0x8000;
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define exported symbol __cy_memory_1_row_size = 0x200;
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/* Supervisory Flash */
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define exported symbol __cy_memory_2_start = 0x16000000;
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define exported symbol __cy_memory_2_length = 0x8000;
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define exported symbol __cy_memory_2_row_size = 0x200;
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/* XIP */
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define exported symbol __cy_memory_3_start = 0x18000000;
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define exported symbol __cy_memory_3_length = 0x08000000;
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define exported symbol __cy_memory_3_row_size = 0x200;
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/* eFuse */
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define exported symbol __cy_memory_4_start = 0x90700000;
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define exported symbol __cy_memory_4_length = 0x100000;
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define exported symbol __cy_memory_4_row_size = 1;
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define memory mem with size = 4G;
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/* Memory regions for all applications are defined here */
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define region FLASH_app0_core0 = mem:[from 0x10000000 size 0x10000];
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define region FLASH_app0_core1 = mem:[from 0x10010000 size 0x10000];
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define region FLASH_app1_core0 = mem:[from 0x10040000 size 0x10000];
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define region FLASH_app1_core1 = mem:[from 0x10050000 size 0x10000];
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/*
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* The region for DFU SDK metadata
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* when it is outside of any application
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*/
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define region FLASH_boot_meta = mem:[from 0x100FFA00 size 0x200];
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/* eFuse */
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define region ROM_EFUSE = mem:[from 0x90700000 size 0x100000];
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/* SFlash NAR */
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define region SFLASH_NAR = mem:[from 0x16001A00 size 0x200];
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/* SFlash User Data */
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define region SFLASH_USER_DATA = mem:[from 0x16000800 size 0x800];
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/* SFlash Public Key, 6 SFlash rows */
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define region SFLASH_PUBLIC_KEY = mem:[from 0x16005A00 size 0xC00];
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/* Table of Content part 2, two SFlash rows */
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define region SFLASH_TOC = mem:[from 0x16007C00 size 0x400];
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/* Emulated EEPROM app regions */
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define region EM_EEPROM_app0_core0 = mem:[from 0x14000000 size 0x8000];
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define region EM_EEPROM_app0_core1 = mem:[from 0x14000000 size 0x8000];
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define region EM_EEPROM_app1_core0 = mem:[from 0x14000000 size 0x8000];
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define region EM_EEPROM_app1_core1 = mem:[from 0x14000000 size 0x8000];
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/* XIP/SMIF app regions */
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define region EROM_app0_core0 = mem:[from 0x18000000 size 0x1000];
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define region EROM_app0_core1 = mem:[from 0x18000000 size 0x1000];
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define region EROM_app1_core0 = mem:[from 0x18000000 size 0x1000];
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define region EROM_app1_core1 = mem:[from 0x18000000 size 0x1000];
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/* used for RAM sharing across applications */
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define region IRAM_common = mem:[from 0x08000000 size 0x0100];
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/* note: all the IRAM_appX_core0 regions has to be 0x100 aligned */
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/* and the IRAM_appX_core1 regions has to be 0x400 aligned */
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/* as they contain Interrupt Vector Table Remapped at the start */
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define region IRAM_app0_core0 = mem:[from 0x08000100 size 0x1F00];
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define region IRAM_app0_core1 = mem:[from 0x08002000 size 0x8000];
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define region IRAM_app1_core0 = mem:[from 0x08000100 size 0x1F00];
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define region IRAM_app1_core1 = mem:[from 0x08002000 size 0x8000];
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/* Used by all DFU SDK and CyMCUElfTool */
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define exported symbol __cy_boot_metadata_addr = 0x100FFA00;
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define exported symbol __cy_boot_metadata_length = __cy_memory_0_row_size;
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/* Used by CyMCUElfTool to generate ProductID for DFU SDK apps */
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define exported symbol __cy_product_id = 0x01020304;
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/* Used by CyMCUElfTool to generate ChecksumType for DFU SDK apps */
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define exported symbol __cy_checksum_type = 0;
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/*
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* The size of the application signature.
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* E.g. 4 for CRC-32,
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* 32 for SHA256,
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* 256 for RSA 2048.
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*/
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define exported symbol __cy_boot_signature_size = 4;
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/* Used by DFU SDK projects, in dfu_user.c to fill in the metadata table */
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define exported symbol __cy_app0_verify_start = start(FLASH_app0_core0);
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define exported symbol __cy_app0_verify_length = size (FLASH_app0_core0) + size (FLASH_app0_core1)
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- __cy_boot_signature_size;
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define exported symbol __cy_app1_verify_start = start(FLASH_app1_core0);
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define exported symbol __cy_app1_verify_length = size (FLASH_app1_core0) + size (FLASH_app1_core1)
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- __cy_boot_signature_size;
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/*******************************************************************************
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* End of CM4 and CM0+ linker script common region
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*******************************************************************************/
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/*
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* Used by CM0+ to start the CM4 core in DFU SDK applications.
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* Make sure the correct app no. is entered here.
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*/
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define exported symbol __cy_app_core1_start_addr = start(FLASH_app0_core1);
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/* CyMCUElfTool uses this symbol to set a proper app number */
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define exported symbol __cy_app_id = 0;
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/* CyMCUElfTool uses these to generate an application signature */
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/* The size of the default signature (CRC-32C) is 4 bytes */
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define exported symbol __cy_app_verify_start = start(FLASH_app0_core0);
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define exported symbol __cy_app_verify_length = size(FLASH_app0_core0) + size(FLASH_app0_core1)
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- __cy_boot_signature_size;
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/*-Sizes-*/
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if (!isdefinedsymbol(__STACK_SIZE)) {
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
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} else {
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define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
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}
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define symbol __ICFEDIT_size_proc_stack__ = 0x0;
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if (!isdefinedsymbol(__HEAP_SIZE)) {
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define symbol __ICFEDIT_size_heap__ = 0x0400;
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} else {
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define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
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}
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define region IROM1_region = FLASH_app0_core0; /* Flash, user app */
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define region IROM2_region = EM_EEPROM_app0_core0; /* Emulated EEPROM */
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define region IROM3_region = SFLASH_USER_DATA; /* SFlash User Data */
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define region IROM4_region = SFLASH_NAR; /* SFlash NAR */
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define region IROM5_region = SFLASH_PUBLIC_KEY; /* SFlash Public Key */
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define region IROM6_region = SFLASH_TOC; /* SFlash TOC part 2 */
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define region IROM7_region = ROM_EFUSE; /* eFuse */
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define region EROM1_region = EROM_app0_core0; /* XIP / SMIF */
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define region IRAM1_region = IRAM_app0_core0; /* RAM */
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
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define block RO {first section .intvec, readonly};
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/*-Initializations-*/
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initialize by copy { readwrite };
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do not initialize { section .noinit, section .intvec_ram,
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section .cy_boot_noinit.appId, section .cy_boot_noinit };
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/*-Placement-*/
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/* Flash */
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".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
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place in IROM1_region { block RO };
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/* Emulated EEPROM Flash area */
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".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
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/* Supervisory Flash - User Data */
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".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
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/* Supervisory Flash - NAR */
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".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
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/* Supervisory Flash - Public Key */
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".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
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/* Supervisory Flash - TOC2 */
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".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
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/* eFuse */
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".cy_efuse" : place at start of IROM7_region { section .cy_efuse };
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/* Execute in Place (XIP). See the smif driver documentation for details. */
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".cy_xip" : place at start of EROM1_region { section .cy_xip };
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/* RAM */
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place at start of IRAM_common { readwrite section .cy_boot_noinit.appId };
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place in IRAM_common { readwrite section .cy_boot_noinit };
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place at start of IRAM1_region { readwrite section .intvec_ram};
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place in IRAM1_region { readwrite };
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place at end of IRAM1_region { block HSTACK };
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/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
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".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
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keep { section .cy_app_header,
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section .cy_em_eeprom,
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section .cy_sflash_user_data,
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section .cy_sflash_nar,
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section .cy_sflash_public_key,
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section .cy_sflash_toc_2,
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section .cy_efuse,
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section .cy_xip,
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section .cymeta,
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section .cy_boot_noinit,
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section .cy_boot_noinit.appId,
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};
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/* EOF */
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