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Initial public release.

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Joe Kearney 2025-02-01 19:22:12 -06:00
parent 7b169e8116
commit dac4af8d25
255 changed files with 68595 additions and 2 deletions
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<?xml version="1.0" encoding="utf-8"?>
<DesignWideResources xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://cypress.com/xsd/cydwr">
<Group key="Component">
<Group key="v1">
<Data key="LIN_Dynamic" value="LIN_Dynamic_v4_0" />
</Group>
</Group>
<Data key="DataVersionKey" value="2" />
<Group key="DWRInstGuidMapping">
<Group key="Clock">
<Data key="6a193d05-b64b-451d-acf3-e3facd8c438d/b68e5b9d-7828-482d-a282-930f990e3b3e" value="UART_DEB_SCBCLK" />
</Group>
<Group key="Pin">
<Data key="2b5567f1-f32a-4160-a53f-69e9456f9b8c" value="PIN_SW2" />
<Data key="6a193d05-b64b-451d-acf3-e3facd8c438d/65f3af6c-759b-4ccb-8c66-5c95ba1f5f4f" value="UART_DEB_tx" />
<Data key="6a193d05-b64b-451d-acf3-e3facd8c438d/b7e8018e-1ef7-49c0-b5a5-61641a03e31c" value="UART_DEB_rx" />
<Data key="9d38c8a9-8e67-42cf-aadd-aa4ff9265154" value="PIN_LED_GREEN" />
<Data key="120d8658-29e0-4f03-bc08-8768eec2d8f2" value="PIN_LED_RED" />
<Data key="373ac181-e5a7-4dc3-90cc-59173ad1ca56" value="Pin_GreenLED" />
<Data key="a61270bc-07ec-447d-ac9e-34cfe85c30e9" value="Pin_1" />
<Data key="aa9833be-078f-43bb-bfa1-32a88558ac1e" value="PIN_LED_BLUE" />
</Group>
</Group>
<Group key="M0S8Clock">
<Group key="DesigneWideClks">
<Group key="8AF878A3-9701-44BB-864C-92E241DEEFC9">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="NAMED_FREQ" />
<Data key="desired_freq" value="24" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="3" />
<Data key="enabled" value="False" />
<Data key="fract_divider_denominator" value="0" />
<Data key="fract_divider_numerator" value="0" />
<Data key="minus_tolerance" value="10" />
<Data key="name" value="Clk_PumpPeri" />
<Data key="netlist_name" value="PumpClkPeri" />
<Data key="ph_align_clock_id" value="" />
<Data key="ph_align_clock_name" value="" />
<Data key="plus_tolerance" value="10" />
<Data key="scope" value="GLOBAL" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="2FB4EC85-8328-4C5A-9ED9-8B63060178EB" />
<Data key="src_clk_name" value="Clk_Peri" />
<Data key="start_on_reset" value="True" />
<Data key="uses_fract_divider" value="False" />
</Group>
</Group>
<Group key="LocalClks">
<Group key="6a193d05-b64b-451d-acf3-e3facd8c438d/b68e5b9d-7828-482d-a282-930f990e3b3e">
<Data key="check_tolerance" value="True" />
<Data key="derive_type" value="AUTO" />
<Data key="desired_freq" value="1.3824" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="54" />
<Data key="enabled" value="True" />
<Data key="fract_divider_denominator" value="0" />
<Data key="fract_divider_numerator" value="0" />
<Data key="minus_tolerance" value="5" />
<Data key="name" value="UART_DEB_SCBCLK" />
<Data key="netlist_name" value="\UART_DEB:SCBCLK\" />
<Data key="ph_align_clock_id" value="" />
<Data key="ph_align_clock_name" value="" />
<Data key="plus_tolerance" value="5" />
<Data key="scope" value="LOCAL" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="2FB4EC85-8328-4C5A-9ED9-8B63060178EB" />
<Data key="src_clk_name" value="Clk_Peri" />
<Data key="start_on_reset" value="True" />
<Data key="uses_fract_divider" value="False" />
</Group>
</Group>
<Group key="SystemClks">
<Group key="0A08FE05-F885-497B-A02E-BF29CD90D1E9">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="8" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="IMO" />
<Data key="netlist_name" value="IMO" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
<Data key="start_on_reset" value="True" />
<Data key="trim_with" value="NONE" />
</Group>
<Group key="1BBDCBF8-BEDC-475F-91D6-B7000D3ACFC0">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="32.768" />
<Data key="desired_unit" value="3" />
<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="Clk_LF" />
<Data key="netlist_name" value="LFClk" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="0.015" />
<Data key="sourceClk_plus_acuracy_name" value="0.015" />
<Data key="src_clk_id" value="3A033BA1-EB59-48AA-A483-E956063B58F7" />
<Data key="src_clk_name" value="WCO" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="2A8967C4-B635-4C8A-8C91-90EE65E329AC">
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<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="PathMux1" />
<Data key="netlist_name" value="PathMux1" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="0A08FE05-F885-497B-A02E-BF29CD90D1E9" />
<Data key="src_clk_name" value="IMO" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="2FB4EC85-8328-4C5A-9ED9-8B63060178EB">
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<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="75" />
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<Data key="divider" value="2" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="Clk_Peri" />
<Data key="netlist_name" value="PeriClk" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="30F7C581-E9BB-4075-AE9E-3D10352921CE" />
<Data key="src_clk_name" value="Clk_HF0" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="3A033BA1-EB59-48AA-A483-E956063B58F7">
<Data key="accuracy_display_unit" value="0" />
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="32768" />
<Data key="desired_unit" value="0" />
<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="WCO" />
<Data key="netlist_name" value="WCO" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="single_ended" value="False" />
<Data key="sourceClk_minus_acuracy_name" value="0.015" />
<Data key="sourceClk_plus_acuracy_name" value="0.015" />
<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
<Data key="start_on_reset" value="False" />
</Group>
<Group key="3B75F9AC-44ED-4CB5-8723-10BBE7669CF0">
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<Data key="name" value="DigSig1" />
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<Data key="scope" value="BUILTIN" />
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<Data key="sourceClk_plus_acuracy_name" value="0" />
<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
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</Group>
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<Data key="sourceClk_minus_acuracy_name" value="2" />
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<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
<Data key="start_on_reset" value="False" />
</Group>
<Group key="5C4F238B-1818-4FC7-84C6-4E205116253D">
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<Data key="enabled" value="False" />
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<Data key="name" value="Clk_HF1" />
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<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="0.25" />
<Data key="sourceClk_plus_acuracy_name" value="0.25" />
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<Data key="src_clk_name" value="FLL" />
<Data key="start_on_reset" value="False" />
</Group>
<Group key="6EACA723-B6E0-41AC-AE21-41E3ED0E6CA7">
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</Group>
<Group key="14CA2D02-47B3-450D-8582-9F89752FD19F">
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<Data key="peri_divider" value="1" />
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<Data key="pump_mode" value="HighPerformance" />
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<Data key="sourceClk_minus_acuracy_name" value="2.4" />
<Data key="sourceClk_plus_acuracy_name" value="2.4" />
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<Data key="name" value="Clk_HF0" />
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<Data key="src_clk_id" value="A6AA470B-43FB-48E8-AAE4-172941809D61" />
<Data key="src_clk_name" value="PLL0" />
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</Group>
<Group key="43B2A111-B593-448F-A298-491D36F976AF">
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<Data key="enabled" value="True" />
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<Data key="name" value="Clk_AltSysTick" />
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<Data key="sourceClk_minus_acuracy_name" value="0.015" />
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</Group>
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<Data key="port_number" value="0" />
<Data key="port_offset" value="0" />
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<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
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</Group>
<Group key="90A0AFF0-F028-4772-9ECA-35D832B188BB">
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<Data key="src_clk_name" value="IMO" />
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<Data key="enabled" value="True" />
<Data key="LOCK_TOLERANCE" value="35" />
<Data key="MANUAL" value="False" />
<Data key="minus_tolerance" value="0" />
<Data key="MULTIPLIER" value="500" />
<Data key="name" value="FLL" />
<Data key="netlist_name" value="FLL" />
<Data key="OUTPUT" value="True" />
<Data key="plus_tolerance" value="0" />
<Data key="REFERENCE" value="40" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="2.4" />
<Data key="sourceClk_plus_acuracy_name" value="2.4" />
<Data key="src_clk_id" value="90A0AFF0-F028-4772-9ECA-35D832B188BB" />
<Data key="src_clk_name" value="PathMux0" />
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</Group>
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<Data key="name" value="DigSig2" />
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<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
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</Group>
<Group key="4952BDB5-B02C-44C1-9796-82E591C05DF5">
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<Data key="enabled" value="False" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="Clk_HF4" />
<Data key="netlist_name" value="HFClk4" />
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<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="0.25" />
<Data key="sourceClk_plus_acuracy_name" value="0.25" />
<Data key="src_clk_id" value="343F3593-1AA2-4B14-BFF9-C9A56BDE27C9" />
<Data key="src_clk_name" value="FLL" />
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</Group>
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<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="Clk_Bak" />
<Data key="netlist_name" value="BakClk" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="0.015" />
<Data key="sourceClk_plus_acuracy_name" value="0.015" />
<Data key="src_clk_id" value="3A033BA1-EB59-48AA-A483-E956063B58F7" />
<Data key="src_clk_name" value="WCO" />
<Data key="start_on_reset" value="True" />
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<Data key="desired_freq" value="50" />
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<Data key="divider" value="1" />
<Data key="enabled" value="False" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="Clk_HF2" />
<Data key="netlist_name" value="HFClk2" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="0.25" />
<Data key="sourceClk_plus_acuracy_name" value="0.25" />
<Data key="src_clk_id" value="343F3593-1AA2-4B14-BFF9-C9A56BDE27C9" />
<Data key="src_clk_name" value="FLL" />
<Data key="start_on_reset" value="False" />
</Group>
<Group key="86410BAB-C607-4C16-A245-8987C7D5B200">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="32" />
<Data key="desired_unit" value="3" />
<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="ILO" />
<Data key="netlist_name" value="ILO" />
<Data key="plus_tolerance" value="0" />
<Data key="run_in_hibernate" value="True" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="10" />
<Data key="sourceClk_plus_acuracy_name" value="10" />
<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="88997D52-6DD5-4C9C-92CA-966A10C3C276">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="8" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="PathMux2" />
<Data key="netlist_name" value="PathMux2" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="0A08FE05-F885-497B-A02E-BF29CD90D1E9" />
<Data key="src_clk_name" value="IMO" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="A6AA470B-43FB-48E8-AAE4-172941809D61">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="150" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="FEEDBACK" value="75" />
<Data key="LOW_FREQUENCY" value="False" />
<Data key="MANUAL" value="False" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="PLL0" />
<Data key="netlist_name" value="PLL0" />
<Data key="OPTIMIZATION" value="MIN_JITTER" />
<Data key="OUTPUT" value="2" />
<Data key="plus_tolerance" value="0" />
<Data key="REFERENCE" value="2" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="2A8967C4-B635-4C8A-8C91-90EE65E329AC" />
<Data key="src_clk_name" value="PathMux1" />
<Data key="start_on_reset" value="False" />
</Group>
<Group key="A43118E8-985E-494A-967B-3EAE88168DCB">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="50" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="1" />
<Data key="enabled" value="False" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="Clk_HF3" />
<Data key="netlist_name" value="HFClk3" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="0.25" />
<Data key="sourceClk_plus_acuracy_name" value="0.25" />
<Data key="src_clk_id" value="343F3593-1AA2-4B14-BFF9-C9A56BDE27C9" />
<Data key="src_clk_name" value="FLL" />
<Data key="start_on_reset" value="False" />
</Group>
<Group key="ADA77A51-2EDA-49E0-9358-E7A5F2860024">
<Data key="accuracy_display_unit" value="1" />
<Data key="AccuracyMinus" value="0" />
<Data key="AccuracyPlus" value="0" />
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="32" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="0" />
<Data key="Divider" value="1" />
<Data key="ECO Frequency" value="32 MHz" />
<Data key="enabled" value="False" />
<Data key="Load cap (pF)" value="17.025" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="AltHF" />
<Data key="netlist_name" value="AltHF" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="0" />
<Data key="sourceClk_plus_acuracy_name" value="0" />
<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
<Data key="start_on_reset" value="False" />
<Data key="Startup time (μs)" value="1500" />
</Group>
<Group key="BAE5EB24-1ECF-44AC-90E5-F6AE7E694F04">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="75" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="1" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="Clk_Slow" />
<Data key="netlist_name" value="SlowClk" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="2FB4EC85-8328-4C5A-9ED9-8B63060178EB" />
<Data key="src_clk_name" value="Clk_Peri" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="C6FE41CF-98FF-4698-8F2D-2E52D350A99C">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="8" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="1" />
<Data key="enabled" value="True" />
<Data key="hf0_div" value="1" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="Clk_Timer" />
<Data key="netlist_name" value="TimerClk" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="0A08FE05-F885-497B-A02E-BF29CD90D1E9" />
<Data key="src_clk_name" value="IMO" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="D75D74B8-A7D4-4EDE-81F8-A16DF63D7E1D">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="8" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="PathMux4" />
<Data key="netlist_name" value="PathMux4" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="0A08FE05-F885-497B-A02E-BF29CD90D1E9" />
<Data key="src_clk_name" value="IMO" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="DA284A0E-4F7B-459E-94F0-90A7FE6053BD">
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="8" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="0" />
<Data key="enabled" value="True" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="PathMux3" />
<Data key="netlist_name" value="PathMux3" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="1" />
<Data key="sourceClk_plus_acuracy_name" value="1" />
<Data key="src_clk_id" value="0A08FE05-F885-497B-A02E-BF29CD90D1E9" />
<Data key="src_clk_name" value="IMO" />
<Data key="start_on_reset" value="True" />
</Group>
<Group key="E7D3001A-7972-446E-BD84-625E3AAB61E9">
<Data key="accuracy_display_unit" value="1" />
<Data key="c_load" value="18" />
<Data key="check_tolerance" value="False" />
<Data key="derive_type" value="BUILTIN" />
<Data key="desired_freq" value="24" />
<Data key="desired_unit" value="6" />
<Data key="divider" value="0" />
<Data key="drive_level" value="100" />
<Data key="enabled" value="False" />
<Data key="esr" value="50" />
<Data key="minus_tolerance" value="0" />
<Data key="name" value="ECO" />
<Data key="netlist_name" value="ECO" />
<Data key="plus_tolerance" value="0" />
<Data key="scope" value="BUILTIN" />
<Data key="sourceClk_minus_acuracy_name" value="0" />
<Data key="sourceClk_plus_acuracy_name" value="0" />
<Data key="src_clk_id" value="" />
<Data key="src_clk_name" value="" />
<Data key="start_on_reset" value="False" />
</Group>
</Group>
</Group>
<Group key="Pin2">
<Group key="2b5567f1-f32a-4160-a53f-69e9456f9b8c">
<Group key="0">
<Data key="Port Format" value="0,4" />
</Group>
</Group>
<Group key="6a193d05-b64b-451d-acf3-e3facd8c438d/65f3af6c-759b-4ccb-8c66-5c95ba1f5f4f">
<Group key="0">
<Data key="Port Format" value="5,1" />
</Group>
</Group>
<Group key="6a193d05-b64b-451d-acf3-e3facd8c438d/b7e8018e-1ef7-49c0-b5a5-61641a03e31c">
<Group key="0">
<Data key="Port Format" value="5,0" />
</Group>
</Group>
<Group key="9d38c8a9-8e67-42cf-aadd-aa4ff9265154">
<Group key="0">
<Data key="Port Format" value="7,1" />
</Group>
</Group>
<Group key="120d8658-29e0-4f03-bc08-8768eec2d8f2">
<Group key="0">
<Data key="Port Format" value="6,3" />
</Group>
</Group>
<Group key="373ac181-e5a7-4dc3-90cc-59173ad1ca56">
<Group key="0">
<Data key="Port Format" value="1,1" />
</Group>
</Group>
<Group key="a61270bc-07ec-447d-ac9e-34cfe85c30e9">
<Group key="0">
<Data key="Port Format" value="12,4" />
</Group>
</Group>
<Group key="aa9833be-078f-43bb-bfa1-32a88558ac1e">
<Group key="0">
<Data key="Port Format" value="11,1" />
</Group>
</Group>
</Group>
<Group key="PlaceDir">
<Data key="count" value="0" />
</Group>
<Group key="System3">
<Data key="CYDEV_APP_IMAGE_SECURITY" value="NONE" />
<Data key="CYDEV_CHIP_SECURITY" value="NORMAL" />
<Data key="CYDEV_CONFIG_UNUSED_IO" value="AllowButWarn" />
<Data key="CYDEV_CONFIGURATION_MODE" value="COMPRESSED" />
<Data key="CYDEV_CPUSS0_TRACE_CLOCK" value="P70" />
<Data key="CYDEV_CPUSS0_TRACE_DATA0" value="P77" />
<Data key="CYDEV_CPUSS0_TRACE_DATA1" value="P76" />
<Data key="CYDEV_CPUSS0_TRACE_DATA2" value="P75" />
<Data key="CYDEV_CPUSS0_TRACE_DATA3" value="P74" />
<Data key="CYDEV_DEBUGGING_DPS" value="SWD" />
<Data key="CYDEV_FLASH_BOOT_SECURE_DATA0" value="" />
<Data key="CYDEV_FLASH_BOOT_SECURE_DATA1" value="" />
<Data key="CYDEV_FLASH_BOOT_SECURE_DATA2" value="" />
<Data key="CYDEV_PMIC_MODE" value="DISABLED" />
<Data key="CYDEV_POWER_MODE" value="LDO_LINEAR_REG_1_1V" />
<Data key="CYDEV_SECURITY_IMAGE" value="" />
<Data key="CYDEV_SECURITY_KEYS" value="" />
<Data key="CYDEV_SYSTEM_AREF_CURRENT" value="HIGH" />
<Data key="CYDEV_SYSTEM_AREF_DEEPSLEEP" value="False" />
<Data key="CYDEV_SYSTEM_AREF_SOURCE" value="LOCAL_1_2V" />
<Data key="CYDEV_TEMPERATURE" value="-40C - 85C" />
<Data key="CYDEV_TRACE_ENABLED" value="False" />
<Data key="CYDEV_VARIABLE_VDDA" value="False" />
<Data key="CYDEV_VBAC_SUPPLY" value="VDDD" />
<Data key="CYDEV_VBACKUP" value="3.3" />
<Data key="CYDEV_VDD" value="3.3" />
<Data key="CYDEV_VDD_NS" value="3.3" />
<Data key="CYDEV_VDDA" value="3.3" />
<Data key="CYDEV_VDDD" value="3.3" />
<Data key="CYDEV_VDDIO0" value="3.3" />
<Data key="CYDEV_VDDIO1" value="3.3" />
<Data key="CYDEV_VDDR_HVL" value="3.3" />
</Group>
</DesignWideResources>

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/***************************************************************************//**
* \file cy8c6xx7_cm0plus.icf
* \version 2.20
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash */
".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
place in IROM1_region { block RO };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_header,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

402
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/***************************************************************************//**
* \file cy8c6xx7_cm0plus.ld
* \version 2.20
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
*/
ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x24000
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
.cy_app_header :
{
KEEP(*(.cy_app_header))
} > flash
.text :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

207
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#! armcc -E
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xx7_cm0plus.scat
;* \version 2.20
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM0+ core.
; You can change the memory allocation by editing the RAM and Flash defines.
; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
; RAM
#define RAM_START 0x08000000
#define RAM_SIZE 0x00024000
; Flash
#define FLASH_START 0x10000000
#define FLASH_SIZE 0x00080000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
LR_FLASH FLASH_START FLASH_SIZE
{
.cy_app_header +0
{
* (.cy_app_header)
}
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
ER_RAM_DATA +0
{
* (.cy_ramfunc)
.ANY (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
ER_RAM_NOINIT_DATA +0 UNINIT
{
* (.noinit)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
.cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* [] END OF FILE */

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/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.20
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash */
place at start of IROM1_region { block RO };
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

408
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/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.20
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x23800
flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x80000
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
.text :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Used for the digital signature of the secure application and the Bootloader SDK application.
* The size of the section depends on the required data size. */
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
{
KEEP(*(.cy_app_signature))
} > flash
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

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#! armcc -E
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.scat
;* \version 2.20
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
#define RAM_START 0x08024000
#define RAM_SIZE 0x00023800
; Flash
#define FLASH_START 0x10080000
#define FLASH_SIZE 0x00080000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
LR_FLASH FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
ER_RAM_DATA +0
{
* (.cy_ramfunc)
.ANY (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
ER_RAM_NOINIT_DATA +0 UNINIT
{
* (.noinit)
}
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{
* (.cy_app_signature)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
.cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* [] END OF FILE */

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/***************************************************************************//**
* \file cy_ble_config.h
* \version 2.80
*
* \brief
* The user BLE configuration file. Allows redefining the configuration #define(s)
* generated by the BLE customizer.
*
********************************************************************************
* \copyright
* Copyright 2017-2023, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#ifndef CY_BLE_CONF_H
#define CY_BLE_CONF_H
#include "ble/cy_ble_defines.h"
/**
* The BLE_config.h file is generated by the BLE customizer and includes all common
* configuration defines (CY_BLE_CONFIG_***).
*/
#include "BLE_config.h"
#include <cy_device_headers.h>
#ifndef CY_IP_MXBLESS
#error "The BLE middleware is not supported on this device"
#endif
/**
* The BLE Interrupt Notification Feature - Exposes BLE interrupt notifications
* to an application that indicates a different link layer and radio state
* transition to the user from the BLESS interrupt context.
* This callback is triggered at the beginning of a received BLESS interrupt
* (based on the registered interrupt mask). After this feature is enabled,
* the following APIs are available:
* Cy_BLE_RegisterInterruptCallback() and Cy_BLE_UnRegisterInterruptCallback().
*
* The valid value: 1u - enable / 0u - disable.
*
* BLE Dual mode requires an additional define IPC channel and IPC Interrupt
* structure to send notification from the controller core to host core.
* Use the following defines:
* #define CY_BLE_INTR_NOTIFY_IPC_CHAN (9..15)
* #define CY_BLE_INTR_NOTIFY_IPC_INTR (9..15)
* #define CY_BLE_INTR_NOTIFY_IPC_INTR_PRIOR (0..7)
*/
#define CY_BLE_INTR_NOTIFY_FEATURE_ENABLE (0u)
/**
* To redefine the config #define(s) generated by the BLE customizer,
* use the construction #undef... #define.
*
* #undef CY_BLE_CONFIG_ENABLE_LL_PRIVACY
* #define CY_BLE_CONFIG_ENABLE_LL_PRIVACY (1u)
*
*/
#endif /* !defined(CY_BLE_CONF_H)*/
/* [] END OF FILE */

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/***************************************************************************//**
* \file cy_si_config.h
* \version 1.0.1
*
* \brief
* Definitions for Secure Image.
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#ifndef _CY_SI_CONFIG_H_
#define _CY_SI_CONFIG_H_
#include "cy_si_keystorage.h"
#if defined(__cplusplus)
extern "C" {
#endif
/***************************************
* Macros
***************************************/
/*
* Macros to define the secure image version and ID.
*/
#define CY_SI_VERSION_MAJOR 1UL /**< Major version */
#define CY_SI_VERSION_MINOR 0UL /**< Minor version */
#define CY_SI_APP_VERSION ((CY_SI_VERSION_MAJOR << 24u) | (CY_SI_VERSION_MINOR << 16u)) /**< App Version */
#define CY_SI_ID CY_PDL_DRV_ID(0x38u) /**< Secure Image ID */
#define CY_SI_ID_INFO (uint32_t)( CY_SI_ID | CY_PDL_STATUS_INFO ) /**< Secure Image INFO ID */
#define CY_SI_ID_WARNING (uint32_t)( CY_SI_ID | CY_PDL_STATUS_WARNING) /**< Secure Image WARNING ID */
#define CY_SI_ID_ERROR (uint32_t)( CY_SI_ID | CY_PDL_STATUS_ERROR) /**< Secure Image ERROR ID */
#define CY_SI_CHECKID(val) ((uint32_t)(val) & (CY_PDL_MODULE_ID_Msk << CY_PDL_MODULE_ID_Pos)) /**< Check ID macro */
/*
* Clock selection for Flash boot execution.
*/
#define CY_SI_FLASHBOOT_CLK_25MHZ (0x00UL) /**< 25MHz clock selection for Flashboot */
#define CY_SI_FLASHBOOT_CLK_8MHZ (0x01UL) /**< 8MHz clock selection for Flashboot */
#define CY_SI_FLASHBOOT_CLK_50MHZ (0x02UL) /**< 50MHz clock selection for Flashboot */
/*
* Debugger wait window selection for Flash boot execution.
*/
#define CY_SI_FLASHBOOT_WAIT_20MS (0x00UL) /**< 20ms debugger wait window for Flashboot */
#define CY_SI_FLASHBOOT_WAIT_10MS (0x01UL) /**< 10ms debugger wait window for Flashboot */
#define CY_SI_FLASHBOOT_WAIT_1MS (0x02UL) /**< 1ms debugger wait window for Flashboot */
#define CY_SI_FLASHBOOT_WAIT_0MS (0x03UL) /**< 0ms debugger wait window for Flashboot */
#define CY_SI_FLASHBOOT_WAIT_100MS (0x04UL) /**< 100ms debugger wait window for Flashboot */
/*
* Flash boot validation selection in chip NORMAL mode.
*/
#define CY_SI_FLASHBOOT_VALIDATE_NO (0x00UL) /**< Do not validate app1 in NORMAL mode */
#define CY_SI_FLASHBOOT_VALIDATE_YES (0x01UL) /**< Validate app1 in NORMAL mode */
/*
* Application format selection for secure boot.
*/
#define CY_SI_APP_FORMAT_BASIC (0UL) /**< Basic application format (no header) */
#define CY_SI_APP_FORMAT_CYPRESS (1UL) /**< Cypress application format (Cypress header) */
/*
* Application type selection for secure boot.
*/
#define CY_SI_APP_ID_FLASHBOOT (0x8001UL) /**< Flash boot ID Type */
#define CY_SI_APP_ID_SECUREIMG (0x8002UL) /**< Secure image ID Type */
#define CY_SI_APP_ID_BOOTLOADER (0x8003UL) /**< Bootloader ID Type */
/***************************************
* Constants
***************************************/
#define CY_ARM_CM0P_CPUID (0xC6000000u) /** CM0+ partNo value from ARM CPUID[15:4] register shifted to [31:20] bits */
#define CY_ARM_CM4_CPUID (0xC2400000u) /** CM4 partNo value from ARM CPUID[15:4] register shifted to [31:20] bits */
#define CY_SI_TOC_FLAGS_CLOCKS_MASK (0x00000003UL) /**< Mask for Flashboot clock selection */
#define CY_SI_TOC_FLAGS_CLOCKS_POS (0UL) /**< Bit position of Flashboot clock selection */
#define CY_SI_TOC_FLAGS_DELAY_MASK (0x0000001CUL) /**< Mask for Flashboot wait window selection */
#define CY_SI_TOC_FLAGS_DELAY_POS (2UL) /**< Bit position of Flashboot wait window selection */
#define CY_SI_TOC_FLAGS_APP_VERIFY_MASK (0x80000000UL) /**< Mask for Flashboot NORMAL mode app1 validation */
#define CY_SI_TOC_FLAGS_APP_VERIFY_POS (31UL) /**< Bit position of Flashboot NORMAL mode app1 validation */
#define CY_SI_TOC2_MAGICNUMBER (0x01211220UL) /**< TOC2 identifier */
/***************************************
* Structs
***************************************/
/** Table of Content structure */
typedef struct{
volatile uint32_t objSize; /**< Object size (Bytes) */
volatile uint32_t magicNum; /**< TOC ID (magic number) */
volatile uint32_t userKeyAddr; /**< Secure key address in user Flash */
volatile uint32_t smifCfgAddr; /**< SMIF configuration structure */
volatile uint32_t appAddr1; /**< First user application object address */
volatile uint32_t appFormat1; /**< First user application format */
volatile uint32_t appAddr2; /**< Second user application object address */
volatile uint32_t appFormat2; /**< Second user application format */
volatile uint32_t shashObj; /**< Number of additional objects to be verified (S-HASH) */
volatile uint32_t sigKeyAddr; /**< Signature verification key address */
volatile uint32_t addObj[116]; /**< Additional objects to include in S-HASH */
volatile uint32_t tocFlags; /**< Flags in TOC to control Flash boot options */
volatile uint32_t crc; /**< CRC16-CCITT */
}cy_stc_si_toc_t;
/** User application header in Cypress format */
typedef struct{
volatile uint32_t objSize; /**< Object size (Bytes) */
volatile uint32_t appId; /**< Application ID/version */
volatile uint32_t appAttributes; /**< Attributes (reserved for future use) */
volatile uint32_t numCores; /**< Number of cores */
volatile uint32_t core0Vt; /**< (CM0+)VT offset - offset to the vector table from that entry */
volatile uint32_t core1Vt; /**< (CM4)VT offset - offset to the vector table from that entry */
volatile uint32_t core0Id; /**< CM0+ core ID */
volatile uint32_t core1Id; /**< CM4 core ID */
}cy_stc_user_appheader_t;
#if defined(__cplusplus)
}
#endif
#endif /* _CY_SI_CONFIG_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cy_si_keystorage.c
* \version 1.00
*
* \brief
* Secure key storage for the secure image.
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cy_si_keystorage.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** Secure Key Storage (Note: Ensure that the alignment matches the Protection unit configuration) */
CY_ALIGN(1024) __USED const uint8_t CySecureKeyStorage[CY_SI_SECURE_KEY_ARRAY_SIZE][CY_SI_SECURE_KEY_LENGTH] = {
{0x00u}, /* Insert user key #1 values */
{0x00u}, /* Insert user key #2 values */
{0x00u}, /* Insert user key #3 values */
{0x00u} /* Insert user key #4 values */
};
/** Public key in SFlash */
CY_SECTION(".cy_sflash_public_key") __USED const cy_si_stc_public_key_t cy_publicKey =
{
.objSize = sizeof(cy_si_stc_public_key_t),
.signatureScheme = CY_SI_PUBLIC_KEY_RSA_2048,
.publicKeyStruct =
{
.moduloAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, moduloData),
.moduloSize = CY_SI_PUBLIC_KEY_SIZEOF_BYTE * CY_SI_PUBLIC_KEY_MODULOLENGTH,
.expAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, expData),
.expSize = CY_SI_PUBLIC_KEY_SIZEOF_BYTE * CY_SI_PUBLIC_KEY_EXPLENGTH,
.barrettAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, barrettData),
.inverseModuloAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, inverseModuloData),
.rBarAddr = (uint32_t)&(SFLASH->PUBLIC_KEY) + offsetof(cy_si_stc_public_key_t, rBarData),
},
/* Replace key data from this point */
.moduloData =
{
0x0Du, 0x10u, 0x58u, 0x3Fu, 0x4Fu, 0x25u, 0x70u, 0x63u,
0x6Du, 0x3Bu, 0xE6u, 0x10u, 0x9Eu, 0x7Cu, 0x7Cu, 0x9Cu,
0x02u, 0x8Bu, 0x43u, 0x07u, 0x61u, 0x91u, 0xF6u, 0xBFu,
0x12u, 0x7Cu, 0x2Bu, 0xDAu, 0x45u, 0xD5u, 0x75u, 0xBEu,
0xB5u, 0xF1u, 0xBDu, 0x36u, 0x3Au, 0xC1u, 0xD1u, 0x39u,
0x20u, 0x11u, 0x99u, 0x22u, 0x2Fu, 0xE8u, 0xFEu, 0x98u,
0xFBu, 0xCDu, 0x34u, 0xD4u, 0xE2u, 0x2Cu, 0xC5u, 0x7Cu,
0xC5u, 0x50u, 0x62u, 0xFFu, 0xFDu, 0x61u, 0x14u, 0x90u,
0xFAu, 0x43u, 0xBDu, 0xADu, 0xA3u, 0xD5u, 0x86u, 0x85u,
0x4Du, 0xF1u, 0x24u, 0x62u, 0x5Au, 0xECu, 0x87u, 0x4Du,
0xD0u, 0x18u, 0xB0u, 0xE1u, 0x4Fu, 0x40u, 0xDEu, 0x87u,
0xBBu, 0x74u, 0xC5u, 0x5Du, 0x48u, 0x90u, 0x26u, 0x68u,
0x5Cu, 0xECu, 0xC3u, 0x5Cu, 0xC7u, 0x03u, 0x8Au, 0x05u,
0x2Eu, 0x37u, 0xB8u, 0xA0u, 0x05u, 0xC5u, 0x21u, 0x0Fu,
0x76u, 0x9Cu, 0xEEu, 0x19u, 0x4Cu, 0x2Eu, 0x89u, 0xA2u,
0x21u, 0x44u, 0x61u, 0x9Fu, 0x7Fu, 0xD2u, 0x51u, 0x72u,
0xABu, 0x2Cu, 0xA5u, 0xC6u, 0x7Cu, 0x0Au, 0x9Bu, 0x06u,
0x14u, 0xECu, 0x91u, 0x3Du, 0x5Eu, 0x08u, 0x71u, 0x6Au,
0xFEu, 0xABu, 0x3Eu, 0x1Bu, 0x99u, 0x3Cu, 0xF0u, 0x12u,
0x57u, 0x0Cu, 0xF2u, 0x42u, 0x78u, 0xA5u, 0x3Bu, 0xAAu,
0x49u, 0x98u, 0x03u, 0x8Eu, 0x0Fu, 0x5Au, 0xC9u, 0xFCu,
0x26u, 0xC9u, 0x93u, 0xB8u, 0xB8u, 0xEBu, 0x6Fu, 0xF1u,
0x65u, 0x78u, 0x43u, 0x0Au, 0xE5u, 0xFBu, 0x2Bu, 0xCCu,
0x8Bu, 0x2Cu, 0x31u, 0x0Du, 0xE1u, 0x49u, 0x06u, 0x25u,
0xE3u, 0xFAu, 0x92u, 0x7Fu, 0xC7u, 0x96u, 0x35u, 0x17u,
0x2Cu, 0xEEu, 0xEEu, 0x40u, 0xC1u, 0x18u, 0x1Cu, 0x5Cu,
0x45u, 0x4Du, 0xE9u, 0xB5u, 0xFDu, 0x23u, 0x60u, 0x14u,
0x5Fu, 0x78u, 0x88u, 0xB9u, 0x17u, 0xAAu, 0xD5u, 0xB4u,
0x68u, 0xCCu, 0x5Cu, 0xE2u, 0x3Fu, 0xD7u, 0xD4u, 0x6Eu,
0x29u, 0x2Au, 0xD7u, 0x6Fu, 0xE8u, 0x89u, 0xCBu, 0xE3u,
0x97u, 0x54u, 0xBCu, 0x4Eu, 0x85u, 0xA7u, 0x63u, 0xAFu,
0x8Au, 0xFDu, 0xB8u, 0xF2u, 0x8Bu, 0xA4u, 0x36u, 0xD4u,
},
.expData =
{
0x01u, 0x00u, 0x01u, 0x00u,
},
.barrettData =
{
0x44u, 0x94u, 0xA5u, 0xF4u, 0x4Fu, 0xCEu, 0x24u, 0xD0u,
0x3Bu, 0xDCu, 0x6Eu, 0x1Cu, 0x72u, 0xE8u, 0x6Fu, 0x5Eu,
0x32u, 0x38u, 0x0Bu, 0xEDu, 0x73u, 0x8Bu, 0x7Cu, 0x1Cu,
0x8Au, 0x03u, 0x36u, 0x88u, 0xB0u, 0x20u, 0x7Au, 0x90u,
0x7Bu, 0x0Du, 0x44u, 0xA2u, 0xF2u, 0x21u, 0x4Fu, 0xD9u,
0xA3u, 0x31u, 0xD8u, 0x87u, 0xD6u, 0xC8u, 0x36u, 0x94u,
0x9Eu, 0x32u, 0x01u, 0xD6u, 0x18u, 0x2Fu, 0x77u, 0x0Cu,
0xD6u, 0xAAu, 0x9Bu, 0x15u, 0xD8u, 0x50u, 0x6Eu, 0x88u,
0xD7u, 0x28u, 0x11u, 0x84u, 0xE3u, 0x7Au, 0x52u, 0x08u,
0x12u, 0xB8u, 0x05u, 0xECu, 0x70u, 0x1Fu, 0xD7u, 0x0Au,
0x53u, 0x18u, 0x62u, 0xEBu, 0x37u, 0x16u, 0x04u, 0x6Du,
0x86u, 0x4Cu, 0x8Au, 0x1Au, 0x6Eu, 0xCEu, 0x5Au, 0xD4u,
0x8Fu, 0x17u, 0xEBu, 0x20u, 0x03u, 0x36u, 0xACu, 0xDDu,
0x74u, 0x16u, 0xB4u, 0xE7u, 0x40u, 0x81u, 0x82u, 0x7Bu,
0x2Fu, 0x31u, 0x95u, 0x64u, 0xFDu, 0x6Eu, 0x75u, 0xB7u,
0x8Bu, 0xC8u, 0x6Au, 0x5Au, 0x48u, 0x28u, 0x5Du, 0xAEu,
0x0Au, 0x11u, 0x86u, 0xC0u, 0x5Au, 0x4Du, 0xDBu, 0x3Eu,
0x85u, 0xCCu, 0xDFu, 0x0Bu, 0x0Eu, 0xCBu, 0x52u, 0xB7u,
0x45u, 0xACu, 0x42u, 0xC2u, 0x39u, 0x1Fu, 0xE1u, 0x18u,
0xFDu, 0x7Bu, 0x77u, 0x7Fu, 0xE9u, 0xFCu, 0x25u, 0x8Cu,
0xB7u, 0x9Eu, 0x38u, 0x6Fu, 0x22u, 0xE6u, 0x6Du, 0xC5u,
0xB8u, 0x79u, 0x15u, 0x0Fu, 0xD1u, 0xAFu, 0x3Du, 0xC2u,
0xB1u, 0xD8u, 0x4Fu, 0x81u, 0x09u, 0xB7u, 0x02u, 0xF0u,
0xCDu, 0x65u, 0xF9u, 0xDFu, 0x0Bu, 0x74u, 0x14u, 0xDEu,
0x17u, 0xDDu, 0xE6u, 0x85u, 0x19u, 0x7Eu, 0x49u, 0x2Fu,
0x82u, 0xBAu, 0x73u, 0x1Du, 0x44u, 0x84u, 0x4Du, 0x5Cu,
0x5Fu, 0x5Bu, 0x6Du, 0x78u, 0x73u, 0xA3u, 0x6Fu, 0x07u,
0x76u, 0xF3u, 0xCDu, 0x52u, 0xE3u, 0xC3u, 0x89u, 0xE8u,
0xA6u, 0x8Au, 0xFAu, 0xF5u, 0x21u, 0xC3u, 0x25u, 0x16u,
0xD5u, 0x10u, 0xFDu, 0x30u, 0x5Du, 0xC5u, 0xB9u, 0xCAu,
0x2Bu, 0x5Au, 0x92u, 0xEDu, 0xE5u, 0xF4u, 0x3Bu, 0xBFu,
0x08u, 0x06u, 0x8Au, 0x75u, 0x88u, 0x36u, 0xD2u, 0x34u,
0x01u, 0x00u, 0x00u, 0x00u,
},
.inverseModuloData =
{
0x3Bu, 0x41u, 0xE5u, 0xABu, 0xC8u, 0x05u, 0x56u, 0xBFu,
0xF8u, 0xF5u, 0xE6u, 0x9Au, 0x46u, 0xF3u, 0x01u, 0x17u,
0xBEu, 0x0Eu, 0x81u, 0x9Bu, 0x54u, 0x2Fu, 0x2Eu, 0x3Du,
0xCBu, 0xA6u, 0xC3u, 0x35u, 0x02u, 0x18u, 0x38u, 0x1Au,
0x38u, 0x15u, 0x54u, 0x0Eu, 0xA4u, 0xCDu, 0xD1u, 0xEDu,
0x10u, 0x8Eu, 0x6Eu, 0xB9u, 0xCDu, 0x2Fu, 0x8Cu, 0xD6u,
0x56u, 0x95u, 0xE8u, 0x14u, 0x79u, 0xC6u, 0x32u, 0x02u,
0xA6u, 0x03u, 0xA1u, 0x8Du, 0x26u, 0x47u, 0xA1u, 0x99u,
0x96u, 0xECu, 0xA3u, 0x77u, 0x22u, 0xEAu, 0x25u, 0x72u,
0xBCu, 0xB8u, 0x77u, 0xE9u, 0x11u, 0x78u, 0x8Cu, 0x55u,
0xB9u, 0x8Eu, 0x90u, 0x19u, 0x3Cu, 0xFFu, 0x9Fu, 0x40u,
0x46u, 0x6Du, 0x51u, 0x22u, 0x21u, 0x15u, 0x5Cu, 0x4Fu,
0xCAu, 0x15u, 0xB0u, 0xE8u, 0x67u, 0x0Au, 0x2Cu, 0x4Au,
0xB1u, 0x77u, 0xFAu, 0xE6u, 0x3Cu, 0xA6u, 0x02u, 0x2Fu,
0x16u, 0x96u, 0xE3u, 0xADu, 0x29u, 0x83u, 0x4Au, 0x88u,
0xB1u, 0x6Bu, 0x13u, 0x38u, 0xA4u, 0xB0u, 0xE8u, 0xA6u,
0xDBu, 0xA5u, 0xFBu, 0x36u, 0x7Au, 0x10u, 0xB1u, 0x75u,
0x93u, 0x00u, 0xECu, 0x2Bu, 0x1Du, 0x86u, 0xE0u, 0x4Fu,
0x85u, 0xC8u, 0x70u, 0x23u, 0xEBu, 0x96u, 0x87u, 0x70u,
0x39u, 0x58u, 0x2Du, 0xAEu, 0xC3u, 0xC9u, 0xB6u, 0xFDu,
0x27u, 0xEEu, 0x5Fu, 0x14u, 0x4Du, 0xB6u, 0xFAu, 0x55u,
0xC3u, 0x2Cu, 0xFAu, 0x2Au, 0x60u, 0x67u, 0x37u, 0xBAu,
0xB3u, 0xA0u, 0x17u, 0x9Du, 0x5Cu, 0xDCu, 0x0Au, 0x82u,
0xFEu, 0x0Eu, 0xC9u, 0xE7u, 0x36u, 0x09u, 0x38u, 0xF3u,
0xA7u, 0x83u, 0x9Au, 0x71u, 0xD2u, 0x07u, 0x2Bu, 0x4Fu,
0x4Eu, 0xABu, 0x49u, 0xE8u, 0x0Eu, 0xE0u, 0x1Cu, 0x48u,
0x73u, 0x87u, 0x62u, 0xC9u, 0x95u, 0x17u, 0xCCu, 0xE6u,
0xECu, 0x34u, 0x18u, 0xE0u, 0xF0u, 0xCFu, 0x64u, 0x48u,
0xD9u, 0x92u, 0x1Au, 0x82u, 0x21u, 0x68u, 0xBCu, 0x70u,
0x31u, 0xA3u, 0xE0u, 0xC9u, 0xAEu, 0xC8u, 0x94u, 0x83u,
0x4Du, 0x95u, 0x3Bu, 0x4Cu, 0x65u, 0x8Eu, 0xC7u, 0x46u,
0x91u, 0x3Cu, 0xF4u, 0xD1u, 0x0Bu, 0xA5u, 0x64u, 0x13u,
},
.rBarData =
{
0xF3u, 0xEFu, 0xA7u, 0xC0u, 0xB0u, 0xDAu, 0x8Fu, 0x9Cu,
0x92u, 0xC4u, 0x19u, 0xEFu, 0x61u, 0x83u, 0x83u, 0x63u,
0xFDu, 0x74u, 0xBCu, 0xF8u, 0x9Eu, 0x6Eu, 0x09u, 0x40u,
0xEDu, 0x83u, 0xD4u, 0x25u, 0xBAu, 0x2Au, 0x8Au, 0x41u,
0x4Au, 0x0Eu, 0x42u, 0xC9u, 0xC5u, 0x3Eu, 0x2Eu, 0xC6u,
0xDFu, 0xEEu, 0x66u, 0xDDu, 0xD0u, 0x17u, 0x01u, 0x67u,
0x04u, 0x32u, 0xCBu, 0x2Bu, 0x1Du, 0xD3u, 0x3Au, 0x83u,
0x3Au, 0xAFu, 0x9Du, 0x00u, 0x02u, 0x9Eu, 0xEBu, 0x6Fu,
0x05u, 0xBCu, 0x42u, 0x52u, 0x5Cu, 0x2Au, 0x79u, 0x7Au,
0xB2u, 0x0Eu, 0xDBu, 0x9Du, 0xA5u, 0x13u, 0x78u, 0xB2u,
0x2Fu, 0xE7u, 0x4Fu, 0x1Eu, 0xB0u, 0xBFu, 0x21u, 0x78u,
0x44u, 0x8Bu, 0x3Au, 0xA2u, 0xB7u, 0x6Fu, 0xD9u, 0x97u,
0xA3u, 0x13u, 0x3Cu, 0xA3u, 0x38u, 0xFCu, 0x75u, 0xFAu,
0xD1u, 0xC8u, 0x47u, 0x5Fu, 0xFAu, 0x3Au, 0xDEu, 0xF0u,
0x89u, 0x63u, 0x11u, 0xE6u, 0xB3u, 0xD1u, 0x76u, 0x5Du,
0xDEu, 0xBBu, 0x9Eu, 0x60u, 0x80u, 0x2Du, 0xAEu, 0x8Du,
0x54u, 0xD3u, 0x5Au, 0x39u, 0x83u, 0xF5u, 0x64u, 0xF9u,
0xEBu, 0x13u, 0x6Eu, 0xC2u, 0xA1u, 0xF7u, 0x8Eu, 0x95u,
0x01u, 0x54u, 0xC1u, 0xE4u, 0x66u, 0xC3u, 0x0Fu, 0xEDu,
0xA8u, 0xF3u, 0x0Du, 0xBDu, 0x87u, 0x5Au, 0xC4u, 0x55u,
0xB6u, 0x67u, 0xFCu, 0x71u, 0xF0u, 0xA5u, 0x36u, 0x03u,
0xD9u, 0x36u, 0x6Cu, 0x47u, 0x47u, 0x14u, 0x90u, 0x0Eu,
0x9Au, 0x87u, 0xBCu, 0xF5u, 0x1Au, 0x04u, 0xD4u, 0x33u,
0x74u, 0xD3u, 0xCEu, 0xF2u, 0x1Eu, 0xB6u, 0xF9u, 0xDAu,
0x1Cu, 0x05u, 0x6Du, 0x80u, 0x38u, 0x69u, 0xCAu, 0xE8u,
0xD3u, 0x11u, 0x11u, 0xBFu, 0x3Eu, 0xE7u, 0xE3u, 0xA3u,
0xBAu, 0xB2u, 0x16u, 0x4Au, 0x02u, 0xDCu, 0x9Fu, 0xEBu,
0xA0u, 0x87u, 0x77u, 0x46u, 0xE8u, 0x55u, 0x2Au, 0x4Bu,
0x97u, 0x33u, 0xA3u, 0x1Du, 0xC0u, 0x28u, 0x2Bu, 0x91u,
0xD6u, 0xD5u, 0x28u, 0x90u, 0x17u, 0x76u, 0x34u, 0x1Cu,
0x68u, 0xABu, 0x43u, 0xB1u, 0x7Au, 0x58u, 0x9Cu, 0x50u,
0x75u, 0x02u, 0x47u, 0x0Du, 0x74u, 0x5Bu, 0xC9u, 0x2Bu,
},
/* End of key data */
};
#if defined(__cplusplus)
}
#endif
/* [] END OF FILE */

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/***************************************************************************//**
* \file cy_si_keystorage.h
* \version 1.00
*
* \brief
* Secure key storage header for the secure image.
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#ifndef _CY_KEY_STORAGE_H_
#define _CY_KEY_STORAGE_H_
#include <stdint.h>
#include <stddef.h>
#include "syslib/cy_syslib.h"
#if defined(__cplusplus)
extern "C" {
#endif
/***************************************
* Macros
***************************************/
/** \addtogroup group_secure_image_macro
* \{
*/
/** \defgroup group_secure_image_userkey_macros User Key Macros
* Macros used to define the user-defined key array.
* \{
*/
#define CY_SI_SECURE_KEY_LENGTH (256u) /**< Key length (Bytes) */
#define CY_SI_SECURE_KEY_ARRAY_SIZE (4u) /**< Number of Keys */
/** \} group_secure_image_userkey_macros */
/** \defgroup group_secure_image_pubkey_macros Public Key Macros
* Macros used to define the Public key.
* \{
*/
#define CY_SI_PUBLIC_KEY_RSA_2048 (0UL) /**< RSASSA-PKCS1-v1_5-2048 signature scheme */
#define CY_SI_PUBLIC_KEY_RSA_1024 (1UL) /**< RSASSA-PKCS1-v1_5-1024 signature scheme */
#define CY_SI_PUBLIC_KEY_STRUCT_OFFSET (8UL) /**< Offset to public key struct in number of bytes */
#define CY_SI_PUBLIC_KEY_MODULOLENGTH (256UL) /**< Modulus length of the RSA key */
#define CY_SI_PUBLIC_KEY_EXPLENGTH (32UL) /**< Exponent length of the RSA key */
#define CY_SI_PUBLIC_KEY_SIZEOF_BYTE (8UL) /**< Size of Byte in number of bits */
/** \} group_secure_image_pubkey_macros */
/** \} group_secure_image_macro */
/***************************************
* Structs
***************************************/
/**
* \addtogroup group_secure_image_data_structures
* \{
*/
/** Public key definition structure as expected by the Crypto driver */
typedef struct
{
uint32_t moduloAddr; /**< Address of the public key modulus */
uint32_t moduloSize; /**< Size (bits) of the modulus part of the public key */
uint32_t expAddr; /**< Address of the public key exponent */
uint32_t expSize; /**< Size (bits) of the exponent part of the public key */
uint32_t barrettAddr; /**< Address of the Barret coefficient */
uint32_t inverseModuloAddr; /**< Address of the binary inverse modulo */
uint32_t rBarAddr; /**< Address of the (2^moduloLength mod modulo) */
} cy_si_stc_crypto_public_key_t;
/** Public key structure */
typedef struct
{
uint32_t objSize; /**< Public key Object size */
uint32_t signatureScheme; /**< Signature scheme */
cy_si_stc_crypto_public_key_t publicKeyStruct; /**< Public key definition struct */
uint8_t moduloData[CY_SI_PUBLIC_KEY_MODULOLENGTH]; /**< Modulo data */
uint8_t expData[CY_SI_PUBLIC_KEY_EXPLENGTH]; /**< Exponent data */
uint8_t barrettData[CY_SI_PUBLIC_KEY_MODULOLENGTH + 4UL]; /**< Barret coefficient data */
uint8_t inverseModuloData[CY_SI_PUBLIC_KEY_MODULOLENGTH]; /**< Binary inverse modulo data */
uint8_t rBarData[CY_SI_PUBLIC_KEY_MODULOLENGTH]; /**< 2^moduloLength mod modulo data */
} cy_si_stc_public_key_t;
/** \} group_secure_image_data_structures */
/***************************************
* Globals
***************************************/
/** Secure Key Storage (Note: Ensure that the alignment matches the Protection unit configuration) */
extern const uint8_t CySecureKeyStorage[CY_SI_SECURE_KEY_ARRAY_SIZE][CY_SI_SECURE_KEY_LENGTH];
/** Public key in SFlash */
extern const cy_si_stc_public_key_t cy_publicKey;
#if defined(__cplusplus)
}
#endif
#endif
/* [] END OF FILE */

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/*******************************************************************************
* File Name: debug.c
*
* Version: 1.0
*
* Description:
* This file contains functions for printf functionality
* and LED status notification.
*
* Hardware Dependency:
* CY8CKIT-062 PSoC6 BLE Pioneer Kit
*
********************************************************************************
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "project.h"
#include "debug.h"
#if (DEBUG_UART_ENABLED == ENABLED)
#if defined(__ARMCC_VERSION)
/* For MDK/RVDS compiler revise fputc function for printf functionality */
struct __FILE
{
int handle;
};
enum
{
STDIN_HANDLE,
STDOUT_HANDLE,
STDERR_HANDLE
};
FILE __stdin = {STDIN_HANDLE};
FILE __stdout = {STDOUT_HANDLE};
FILE __stderr = {STDERR_HANDLE};
int fputc(int ch, FILE *file)
{
int ret = EOF;
switch( file->handle )
{
case STDOUT_HANDLE:
UART_DEB_PUT_CHAR(ch);
ret = ch ;
break ;
case STDERR_HANDLE:
ret = ch ;
break ;
default:
file = file;
break ;
}
return ret ;
}
#elif defined (__ICCARM__) /* IAR */
/* For IAR compiler revise __write() function for printf functionality */
size_t __write(int handle, const unsigned char * buffer, size_t size)
{
size_t nChars = 0;
(void) handle;
if (buffer == 0)
{
/*
* This means that we should flush internal buffers. Since we
* don't we just return. (Remember, "handle" == -1 means that all
* handles should be flushed.)
*/
return (0);
}
for (/* Empty */; size != 0; --size)
{
UART_DEB_PUT_CHAR(*buffer);
++buffer;
++nChars;
}
return (nChars);
}
#else /* (__GNUC__) GCC */
/* For GCC compiler revise _write() function for printf functionality */
int _write(int file, char *ptr, int len)
{
int i;
file = file;
for (i = 0; i < len; i++)
{
UART_DEB_PUT_CHAR(*ptr);
++ptr;
}
return len;
}
#endif /* (__ARMCC_VERSION) */
#endif /* DEBUG_UART_ENABLED == ENABLED */
#if (DEBUG_LED_ENABLED == ENABLED)
void InitLED(void)
{
#if CYDEV_VDD_MV >= RGB_LED_MIN_VOLTAGE_MV
Cy_GPIO_SetDrivemode(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, CY_GPIO_DM_STRONG_IN_OFF);
Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_OFF);
Cy_GPIO_SetDrivemode(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM, CY_GPIO_DM_STRONG_IN_OFF);
Cy_GPIO_Write(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM, LED_OFF);
#else
Cy_GPIO_SetDrivemode(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, CY_GPIO_DM_STRONG_IN_OFF);
Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_OFF);
#endif
}
void HibernateLED(void)
{
#if CYDEV_VDD_MV >= RGB_LED_MIN_VOLTAGE_MV
Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_ON);
Cy_GPIO_Write(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM, LED_OFF);
#else
Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_ON);
#endif
}
void BlinkLED(void)
{
#if CYDEV_VDD_MV >= RGB_LED_MIN_VOLTAGE_MV
Cy_GPIO_Inv(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM);
Cy_GPIO_Inv(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM);
#else
Cy_GPIO_Inv(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM);
#endif
}
void ConnectedLED(void)
{
#if CYDEV_VDD_MV >= RGB_LED_MIN_VOLTAGE_MV
Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_OFF);
Cy_GPIO_Write(PIN_LED_GREEN_0_PORT, PIN_LED_GREEN_0_NUM, LED_OFF);
#else
Cy_GPIO_Write(PIN_LED_RED_0_PORT, PIN_LED_RED_0_NUM, LED_OFF);
#endif
}
#endif /* DEBUG_LED == ENABLED */
/* [] END OF FILE */

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/***************************************************************************//**
* \file debug.h
*
* \version 1.0
*
* Contains the function prototypes and constants for the UART debugging
* and LED status notification.
*
********************************************************************************
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <stdio.h>
#include "project.h"
#define ENABLED (1u)
#define DISABLED (0u)
/***************************************
* Conditional Compilation Parameters
***************************************/
#define DEBUG_UART_ENABLED ENABLED
#define DEBUG_LED_ENABLED ENABLED
/***************************************
* API Constants
***************************************/
#define LED_ON (0u)
#define LED_OFF (1u)
#define RGB_LED_MIN_VOLTAGE_MV (2700u)
#define ADV_TIMER_TIMEOUT (1u)
/***************************************
* External Function Prototypes
***************************************/
#if (DEBUG_LED_ENABLED)
void InitLED(void);
void HibernateLED(void);
void BlinkLED(void);
void ConnectedLED(void);
#else
#define InitLED()
#define HibernateLED()
#define BlinkLED()
#define ConnectedLED()
#endif
/***************************************
* Macros
***************************************/
#if (DEBUG_UART_ENABLED == ENABLED)
#define DBG_PRINTF(...) (printf(__VA_ARGS__))
#define UART_DEB_PUT_CHAR(ch) while(0UL == UART_DEB_Put(ch))
__STATIC_INLINE char8 UART_DEB_GET_CHAR(void)
{
uint32 rec;
rec = UART_DEB_Get();
return((rec == CY_SCB_UART_RX_NO_DATA) ? 0u : (char8)(rec & 0xff));
}
#define UART_DEB_GET_TX_BUFF_SIZE() ( UART_DEB_GetNumInTxFifo() )
#define UART_START() ( UART_DEB_Start() )
#else
#define DBG_PRINTF(...)
#define UART_DEB_PUT_CHAR(ch)
#define UART_DEB_GET_CHAR(ch) (0u)
#ifndef UART_DEB_GET_TX_FIFO_SR_VALID
#define UART_DEB_GET_TX_FIFO_SR_VALID (0u)
#endif
#define UART_DEB_GET_TX_BUFF_SIZE(...) (0u)
#define UART_START()
#endif /* (DEBUG_UART_ENABLED == ENABLED) */
/* [] END OF FILE */

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/***************************************************************************//**
* \file dfu_cm0p.icf
* \version 3.0
*
* The linker file for the the IAR compiler.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case, you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*******************************************************************************
* Start of CM4 and CM0+ linker script common region
*******************************************************************************/
/*-Memory Regions-*/
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
define memory mem with size = 4G;
/* Memory regions for all applications are defined here */
define region FLASH_app0_core0 = mem:[from 0x10000000 size 0x10000];
define region FLASH_app0_core1 = mem:[from 0x10010000 size 0x10000];
define region FLASH_app1_core0 = mem:[from 0x10040000 size 0x10000];
define region FLASH_app1_core1 = mem:[from 0x10050000 size 0x10000];
/*
* The region for DFU SDK metadata
* when it is outside of any application
*/
define region FLASH_boot_meta = mem:[from 0x100FFA00 size 0x200];
/* eFuse */
define region ROM_EFUSE = mem:[from 0x90700000 size 0x100000];
/* SFlash NAR */
define region SFLASH_NAR = mem:[from 0x16001A00 size 0x200];
/* SFlash User Data */
define region SFLASH_USER_DATA = mem:[from 0x16000800 size 0x800];
/* SFlash Public Key, 6 SFlash rows */
define region SFLASH_PUBLIC_KEY = mem:[from 0x16005A00 size 0xC00];
/* Table of Content part 2, two SFlash rows */
define region SFLASH_TOC = mem:[from 0x16007C00 size 0x400];
/* Emulated EEPROM app regions */
define region EM_EEPROM_app0_core0 = mem:[from 0x14000000 size 0x8000];
define region EM_EEPROM_app0_core1 = mem:[from 0x14000000 size 0x8000];
define region EM_EEPROM_app1_core0 = mem:[from 0x14000000 size 0x8000];
define region EM_EEPROM_app1_core1 = mem:[from 0x14000000 size 0x8000];
/* XIP/SMIF app regions */
define region EROM_app0_core0 = mem:[from 0x18000000 size 0x1000];
define region EROM_app0_core1 = mem:[from 0x18000000 size 0x1000];
define region EROM_app1_core0 = mem:[from 0x18000000 size 0x1000];
define region EROM_app1_core1 = mem:[from 0x18000000 size 0x1000];
/* used for RAM sharing across applications */
define region IRAM_common = mem:[from 0x08000000 size 0x0100];
/* note: all the IRAM_appX_core0 regions has to be 0x100 aligned */
/* and the IRAM_appX_core1 regions has to be 0x400 aligned */
/* as they contain Interrupt Vector Table Remapped at the start */
define region IRAM_app0_core0 = mem:[from 0x08000100 size 0x1F00];
define region IRAM_app0_core1 = mem:[from 0x08002000 size 0x8000];
define region IRAM_app1_core0 = mem:[from 0x08000100 size 0x1F00];
define region IRAM_app1_core1 = mem:[from 0x08002000 size 0x8000];
/* Used by all DFU SDK and CyMCUElfTool */
define exported symbol __cy_boot_metadata_addr = 0x100FFA00;
define exported symbol __cy_boot_metadata_length = __cy_memory_0_row_size;
/* Used by CyMCUElfTool to generate ProductID for DFU SDK apps */
define exported symbol __cy_product_id = 0x01020304;
/* Used by CyMCUElfTool to generate ChecksumType for DFU SDK apps */
define exported symbol __cy_checksum_type = 0;
/*
* The size of the application signature.
* E.g. 4 for CRC-32,
* 32 for SHA256,
* 256 for RSA 2048.
*/
define exported symbol __cy_boot_signature_size = 4;
/* Used by DFU SDK projects, in dfu_user.c to fill in the metadata table */
define exported symbol __cy_app0_verify_start = start(FLASH_app0_core0);
define exported symbol __cy_app0_verify_length = size (FLASH_app0_core0) + size (FLASH_app0_core1)
- __cy_boot_signature_size;
define exported symbol __cy_app1_verify_start = start(FLASH_app1_core0);
define exported symbol __cy_app1_verify_length = size (FLASH_app1_core0) + size (FLASH_app1_core1)
- __cy_boot_signature_size;
/*******************************************************************************
* End of CM4 and CM0+ linker script common region
*******************************************************************************/
/*
* Used by CM0+ to start the CM4 core in DFU SDK applications.
* Make sure the correct app no. is entered here.
*/
define exported symbol __cy_app_core1_start_addr = start(FLASH_app0_core1);
/* CyMCUElfTool uses this symbol to set a proper app number */
define exported symbol __cy_app_id = 0;
/* CyMCUElfTool uses these to generate an application signature */
/* The size of the default signature (CRC-32C) is 4 bytes */
define exported symbol __cy_app_verify_start = start(FLASH_app0_core0);
define exported symbol __cy_app_verify_length = size(FLASH_app0_core0) + size(FLASH_app0_core1)
- __cy_boot_signature_size;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
define region IROM1_region = FLASH_app0_core0; /* Flash, user app */
define region IROM2_region = EM_EEPROM_app0_core0; /* Emulated EEPROM */
define region IROM3_region = SFLASH_USER_DATA; /* SFlash User Data */
define region IROM4_region = SFLASH_NAR; /* SFlash NAR */
define region IROM5_region = SFLASH_PUBLIC_KEY; /* SFlash Public Key */
define region IROM6_region = SFLASH_TOC; /* SFlash TOC part 2 */
define region IROM7_region = ROM_EFUSE; /* eFuse */
define region EROM1_region = EROM_app0_core0; /* XIP / SMIF */
define region IRAM1_region = IRAM_app0_core0; /* RAM */
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram,
section .cy_boot_noinit.appId, section .cy_boot_noinit };
/*-Placement-*/
/* Flash */
".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
place in IROM1_region { block RO };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM7_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */
place at start of IRAM_common { readwrite section .cy_boot_noinit.appId };
place in IRAM_common { readwrite section .cy_boot_noinit };
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_header,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_sflash_toc_2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
section .cy_boot_noinit,
section .cy_boot_noinit.appId,
};
/* EOF */

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/***************************************************************************//**
* \file dfu_cm0p.ld
* \version 3.0
*
* The linker file for the GNU C compiler.
* Used for DFU SDK core0 firmware projects.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case, you may see warnings during the
* build process. In your project, simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/*
* Forces symbol to be added to the output file.
* Otherwise linker may remove it if founds that it is not used in the project.
* This command has the same effect as the -u command-line option.
*/
EXTERN(Reset_Handler)
/*******************************************************************************
* Start of CM4 and CM0+ linker script common region
*******************************************************************************/
/*
* Memory regions, for each application and MCU core.
*/
MEMORY
{
flash_app0_core0 (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000
flash_app0_core1 (rx) : ORIGIN = 0x10010000, LENGTH = 0x30000
flash_app1_core0 (rx) : ORIGIN = 0x10040000, LENGTH = 0x30000
flash_app1_core1 (rx) : ORIGIN = 0x10070000, LENGTH = 0x50000
flash_storage (rw) : ORIGIN = 0x100D0000, LENGTH = 0x1000
flash_boot_meta (rw) : ORIGIN = 0x100FFA00, LENGTH = 0x400
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000
ram_common (rwx) : ORIGIN = 0x08000000, LENGTH = 0x0100
/* note: all the ram_appX_core0 regions has to be 0x100 aligned */
/* and the ram_appX_core1 regions has to be 0x400 aligned */
/* as they contain Interrupt Vector Table Remapped at the start */
ram_app0_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00
ram_app0_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x8000
ram_app1_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00
ram_app1_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x30000
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x08000000
}
/* Regions parameters */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* The DFU SDK metadata limits */
__cy_boot_metadata_addr = ORIGIN(flash_boot_meta);
__cy_boot_metadata_length = __cy_memory_0_row_size;
/* The Product ID, used by CyMCUElfTool to generate a updating file */
__cy_product_id = 0x01020304;
/* The checksum type used by CyMCUElfTool to generate a updating file */
__cy_checksum_type = 0x00;
/* Used by the DFU SDK application to set the metadata */
__cy_app0_verify_start = ORIGIN(flash_app0_core0);
__cy_app0_verify_length = LENGTH(flash_app0_core0) + LENGTH(flash_app0_core1) - __cy_boot_signature_size;
__cy_app1_verify_start = ORIGIN(flash_app1_core0);
__cy_app1_verify_length = LENGTH(flash_app1_core0) + LENGTH(flash_app1_core1) - __cy_boot_signature_size;
/*
* The size of the application signature.
* E.g. 4 for CRC-32,
* 32 for SHA256,
* 256 for RSA 2048.
*/
__cy_boot_signature_size = 256;
/*******************************************************************************
* End of CM4 and CM0+ linker script common region
*******************************************************************************/
/*
* DFU SDK specific: aliases regions, so the rest of code does not use
* application specific memory region names
*/
REGION_ALIAS("flash", flash_app0_core0);
REGION_ALIAS("flash_core1", flash_app0_core1);
REGION_ALIAS("ram", ram_app0_core0);
/* DFU SDK specific: sets an app Id */
__cy_app_id = 0;
/*
* DFU SDK specific: sets a start address of the Core1 application image,
* more specifically an address of the Core1 interrupt vector table.
* CM0+ uses this information to launch Core1.
*/
__cy_app_core1_start_addr = ORIGIN(flash_core1); /* used to start Core1 from Core0 */
/* DFU SDK specific */
/* CyMCUElfTool uses these ELF symbols to generate an application signature */
__cy_app_verify_start = ORIGIN(flash);
__cy_app_verify_length = LENGTH(flash) + LENGTH(flash_core1) - __cy_boot_signature_size;
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* The linker script defines how to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* This linker script defines the symbols, which can be used by code without a definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*
* For the DFU SDK, these additional symbols are defined:
* __cy_app_id
* __cy_product_id
* __cy_checksum_type
* __cy_app_core1_start_addr
* __cy_boot_metadata_addr
* __cy_boot_metadata_length
*/
SECTIONS
{
/* DFU SDK specific */
/* The noinit section, used across all the applications */
.cy_boot_noinit (NOLOAD) :
{
KEEP(*(.cy_boot_noinit));
} > ram_common
/* The last byte of the section is used for AppId to be shared between all the applications */
.cy_boot_noinit.appId ORIGIN(ram_common) + LENGTH(ram_common) - 1 (NOLOAD) :
{
KEEP(*(.cy_boot_noinit.appId));
} > ram_common
/* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */
.cy_boot_metadata :
{
KEEP(*(.cy_boot_metadata))
} > flash_boot_meta
.cy_app_header :
{
KEEP(*(.cy_app_header))
} > flash
.text :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to the RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_{device}_cm0plus.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from Flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_{device}_cm0plus.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells the linker that the .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes the linker: A) not allocate the section in memory;
* B) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get the PROGBITS type.
* This makes the linker: A) allocate the zeroed section in memory; B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > ram
/* The .stack_dummy section doesn't contain any symbols. It is only
* used for the linker to calculate the size of the stack sections, and assign
* values to the stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set the stack top to the end of RAM, and the stack limit move down by
* the size of the stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Places the code in the Execute in the Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* EOF */

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#! armcc -E
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file dfu_cm0p.scat
;* \version 3.0
;*
;* The linker file for the ARMCC.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case, you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;******************************************************************************/
;* DFU SDK specific: includes defines common across all the applications
#include "dfu_mdk_common.h"
;* DFU SDK specific: defines the memory regions
;* Make sure the correct app no. is entered here.
; Flash
#define FLASH_START CY_APP0_CORE0_FLASH_ADDR
#define FLASH_SIZE CY_APP0_CORE0_FLASH_LENGTH
; Emulated EEPROM Flash area
#define EM_EEPROM_START CY_APP0_CORE0_EM_EEPROM_ADDR
#define EM_EEPROM_SIZE CY_APP0_CORE0_EM_EEPROM_LENGTH
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000400
; External memory
#define XIP_START CY_APP0_CORE0_SMIF_ADDR
#define XIP_SIZE CY_APP0_CORE0_SMIF_LENGTH
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; RAM
#define RAM_START CY_APP0_CORE0_RAM_ADDR
#define RAM_SIZE CY_APP0_CORE0_RAM_LENGTH
LR_FLASH FLASH_START FLASH_SIZE
{
.cy_app_header +0
{
* (.cy_app_header)
}
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_COMMON CY_APP_RAM_COMMON_ADDR UNINIT
{
* (.cy_boot_noinit.appId)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
ER_RAM_DATA +0
{
* (.cy_ramfunc)
.ANY (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
ER_RAM_NOINIT_DATA +0 UNINIT
{
* (.noinit)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Places the code in the Execute in the Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
.cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* [] END OF FILE */

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/***************************************************************************//**
* \file dfu_cm4.icf
* \version 3.0
*
* The linker file for the the IAR compiler.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case, you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*******************************************************************************
* Start of CM4 and CM0+ linker script common region
*******************************************************************************/
/*-Memory Regions-*/
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
define memory mem with size = 4G;
/* Memory regions for all applications are defined here */
define region FLASH_app0_core0 = mem:[from 0x10000000 size 0x10000];
define region FLASH_app0_core1 = mem:[from 0x10010000 size 0x10000];
define region FLASH_app1_core0 = mem:[from 0x10040000 size 0x10000];
define region FLASH_app1_core1 = mem:[from 0x10050000 size 0x10000];
/*
* The region for DFU SDK metadata
* when it is outside of any application
*/
define region FLASH_boot_meta = mem:[from 0x100FFA00 size 0x200];
/* eFuse */
define region ROM_EFUSE = mem:[from 0x90700000 size 0x100000];
/* SFlash NAR */
define region SFLASH_NAR = mem:[from 0x16001A00 size 0x200];
/* SFlash User Data */
define region SFLASH_USER_DATA = mem:[from 0x16000800 size 0x800];
/* SFlash Public Key, 6 SFlash rows */
define region SFLASH_PUBLIC_KEY = mem:[from 0x16005A00 size 0xC00];
/* Table of Content part 2, two SFlash rows */
define region SFLASH_TOC = mem:[from 0x16007C00 size 0x400];
/* Emulated EEPROM app regions */
define region EM_EEPROM_app0_core0 = mem:[from 0x14000000 size 0x8000];
define region EM_EEPROM_app0_core1 = mem:[from 0x14000000 size 0x8000];
define region EM_EEPROM_app1_core0 = mem:[from 0x14000000 size 0x8000];
define region EM_EEPROM_app1_core1 = mem:[from 0x14000000 size 0x8000];
/* XIP/SMIF app regions */
define region EROM_app0_core0 = mem:[from 0x18000000 size 0x1000];
define region EROM_app0_core1 = mem:[from 0x18000000 size 0x1000];
define region EROM_app1_core0 = mem:[from 0x18000000 size 0x1000];
define region EROM_app1_core1 = mem:[from 0x18000000 size 0x1000];
/* used for RAM sharing across applications */
define region IRAM_common = mem:[from 0x08000000 size 0x0100];
/* note: all the IRAM_appX_core0 regions has to be 0x100 aligned */
/* and the IRAM_appX_core1 regions has to be 0x400 aligned */
/* as they contain Interrupt Vector Table Remapped at the start */
define region IRAM_app0_core0 = mem:[from 0x08000100 size 0x1F00];
define region IRAM_app0_core1 = mem:[from 0x08002000 size 0x8000];
define region IRAM_app1_core0 = mem:[from 0x08000100 size 0x1F00];
define region IRAM_app1_core1 = mem:[from 0x08002000 size 0x8000];
/* Used by all DFU SDK and CyMCUElfTool */
define exported symbol __cy_boot_metadata_addr = 0x100FFA00;
define exported symbol __cy_boot_metadata_length = __cy_memory_0_row_size;
/* Used by CyMCUElfTool to generate ProductID for DFU SDK apps */
define exported symbol __cy_product_id = 0x01020304;
/* Used by CyMCUElfTool to generate ChecksumType for DFU SDK apps */
define exported symbol __cy_checksum_type = 0;
/*
* The size of the application signature.
* E.g. 4 for CRC-32,
* 32 for SHA256,
* 256 for RSA 2048.
*/
define exported symbol __cy_boot_signature_size = 4;
/* Used by DFU SDK projects, in dfu_user.c to fill in the metadata table */
define exported symbol __cy_app0_verify_start = start(FLASH_app0_core0);
define exported symbol __cy_app0_verify_length = size (FLASH_app0_core0) + size (FLASH_app0_core1)
- __cy_boot_signature_size;
define exported symbol __cy_app1_verify_start = start(FLASH_app1_core0);
define exported symbol __cy_app1_verify_length = size (FLASH_app1_core0) + size (FLASH_app1_core1)
- __cy_boot_signature_size;
/*******************************************************************************
* End of CM4 and CM0+ linker script common region
*******************************************************************************/
/* CyMCUElfTool uses this symbol to set a proper app number */
define exported symbol __cy_app_id = 0;
/* CyMCUElfTool uses these to generate an application signature */
/* The size of the default signature (CRC-32C) is 4 bytes */
define exported symbol __cy_app_verify_start = start(FLASH_app0_core0);
define exported symbol __cy_app_verify_length = size(FLASH_app0_core0) + size(FLASH_app0_core1)
- __cy_boot_signature_size;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = 0x1000;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
define region IROM1_region = FLASH_app0_core1; /* Flash, user app */
define region IROM2_region = EM_EEPROM_app0_core1; /* Emulated EEPROM */
define region IROM3_region = SFLASH_USER_DATA; /* SFlash User Data */
define region IROM4_region = SFLASH_NAR; /* SFlash NAR */
define region IROM5_region = SFLASH_PUBLIC_KEY; /* SFlash Public Key */
define region IROM6_region = SFLASH_TOC; /* SFlash TOC part 2 */
define region IROM7_region = ROM_EFUSE; /* eFuse */
define region EROM1_region = EROM_app0_core1; /* XIP / SMIF */
define region IRAM1_region = IRAM_app0_core1; /* RAM */
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
define block RO {first section .intvec, readonly};
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram,
section .cy_boot_noinit.appId, section .cy_boot_noinit };
/*-Placement-*/
/* Flash */
place at start of IROM1_region { block RO };
".cy_app_signature": place at end of IROM1_region { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM7_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */
place at start of IRAM_common { readwrite section .cy_boot_noinit.appId };
place in IRAM_common { readwrite section .cy_boot_noinit };
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { readwrite };
place at end of IRAM1_region { block HSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
/* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */
".cy_boot_metadata" : place at start of FLASH_boot_meta { section .cy_boot_metadata };
keep { section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_sflash_toc_2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
section .cy_boot_metadata,
section .cy_boot_noinit,
section .cy_boot_noinit.appId,
};
/* EOF */

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/***************************************************************************//**
* \file dfu_cm4.ld
* \version 3.0
*
* The linker file for the GNU C compiler.
* Used for DFU SDK core1 firmware projects.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case, you may see warnings during the
* build process. In your project, simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/*
* Forces symbol to be added to the output file.
* Otherwise linker may remove it if founds that it is not used in the project.
* This command has the same effect as the -u command-line option.
*/
EXTERN(Reset_Handler)
/*******************************************************************************
* Start of CM4 and CM0+ linker script common region
*******************************************************************************/
/*
* Memory regions, for each application and MCU core.
*/
MEMORY
{
flash_app0_core0 (rx) : ORIGIN = 0x10000000, LENGTH = 0x10000
flash_app0_core1 (rx) : ORIGIN = 0x10010000, LENGTH = 0x30000
flash_app1_core0 (rx) : ORIGIN = 0x10040000, LENGTH = 0x30000
flash_app1_core1 (rx) : ORIGIN = 0x10070000, LENGTH = 0x50000
flash_storage (rw) : ORIGIN = 0x100D0000, LENGTH = 0x1000
flash_boot_meta (rw) : ORIGIN = 0x100FFA00, LENGTH = 0x400
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x400
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000
ram_common (rwx) : ORIGIN = 0x08000000, LENGTH = 0x0100
/* note: all the ram_appX_core0 regions has to be 0x100 aligned */
/* and the ram_appX_core1 regions has to be 0x400 aligned */
/* as they contain Interrupt Vector Table Remapped at the start */
ram_app0_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00
ram_app0_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x8000
ram_app1_core0 (rwx) : ORIGIN = 0x08000100, LENGTH = 0x7F00
ram_app1_core1 (rwx) : ORIGIN = 0x08008000, LENGTH = 0x30000
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x08000000
}
/* Regions parameters */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* The DFU SDK metadata limits */
__cy_boot_metadata_addr = ORIGIN(flash_boot_meta);
__cy_boot_metadata_length = __cy_memory_0_row_size;
/* The Product ID, used by CyMCUElfTool to generate a updating file */
__cy_product_id = 0x01020304;
/* The checksum type used by CyMCUElfTool to generate a updating file */
__cy_checksum_type = 0x00;
/* Used by the DFU SDK application to set the metadata */
__cy_app0_verify_start = ORIGIN(flash_app0_core0);
__cy_app0_verify_length = LENGTH(flash_app0_core0) + LENGTH(flash_app0_core1) - __cy_boot_signature_size;
__cy_app1_verify_start = ORIGIN(flash_app1_core0);
__cy_app1_verify_length = LENGTH(flash_app1_core0) + LENGTH(flash_app1_core1) - __cy_boot_signature_size;
/*
* The size of the application signature.
* E.g. 4 for CRC-32,
* 32 for SHA256,
* 256 for RSA 2048.
*/
__cy_boot_signature_size = 256;
/*******************************************************************************
* End of CM4 and CM0+ linker script common region
*******************************************************************************/
/*
* DFU SDK specific: aliases regions, so the rest of code does not use
* application specific memory region names
*/
REGION_ALIAS("flash_core0", flash_app0_core0);
REGION_ALIAS("flash", flash_app0_core1);
REGION_ALIAS("ram", ram_app0_core1);
/* DFU SDK specific: sets an app Id */
__cy_app_id = 0;
/* DFU SDK specific */
/* CyMCUElfTool uses these ELF symbols to generate an application signature */
__cy_app_verify_start = ORIGIN(flash_core0);
__cy_app_verify_length = LENGTH(flash_core0) + LENGTH(flash) - __cy_boot_signature_size;
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* The linker script defines how to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* This linker script defines the symbols, which can be used by code without a definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*
* For the DFU SDK, these additional symbols are defined:
* __cy_app_id
* __cy_product_id
* __cy_checksum_type
* __cy_app_core1_start_addr
* __cy_boot_metadata_addr
* __cy_boot_metadata_length
*/
SECTIONS
{
/* DFU SDK specific */
/* The noinit section, used across all the applications */
.cy_boot_noinit (NOLOAD) :
{
KEEP(*(.cy_boot_noinit));
} > ram_common
/* The last byte of the section is used for AppId to be shared between all the applications */
.cy_boot_noinit.appId ORIGIN(ram_common) + LENGTH(ram_common) - 1 (NOLOAD) :
{
KEEP(*(.cy_boot_noinit.appId));
} > ram_common
/* App0 uses it to initialize DFU SDK metadata, in the dfu_user.c file */
.cy_boot_metadata :
{
KEEP(*(.cy_boot_metadata))
} > flash_boot_meta
.text :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to the RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_{device}_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_{device}_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
/*
* The DFU SDK section for an app verification signature.
* Must be placed at the end of the application.
* In this case, last N bytes of the last Flash row inside the application.
*/
.cy_app_signature ABSOLUTE(ORIGIN(flash) + LENGTH(flash) - __cy_boot_signature_size) :
{
KEEP(*(.cy_app_signature))
} > flash = 0
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells the linker that the .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes the linker: A) not allocate the section in memory;
* B) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get the PROGBITS type.
* This makes the linker: A) allocate the zeroed section in memory; B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > ram
/* The .stack_dummy section doesn't contain any symbols. It is only
* used for the linker to calculate the size of the stack sections, and assign
* values to the stack symbols later */
.stack_dummy (NOLOAD):
{
KEEP(*(.stack*))
} > ram
/* Set the stack top to the end of RAM, and the stack limit move down by
* the size of the stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Places the code in the Execute in the Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* EOF */

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#! armcc -E
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file dfu_cm4.scat
;* \version 3.0
;*
;* The linker file for the ARMCC.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case, you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;******************************************************************************/
;* DFU SDK specific: includes defines common across all the applications
#include "dfu_mdk_common.h"
;* DFU SDK specific: defines the memory regions
;* Make sure the correct app no. is entered here
; Flash
#define FLASH_START CY_APP0_CORE1_FLASH_ADDR
#define FLASH_SIZE CY_APP0_CORE1_FLASH_LENGTH
; Flash Toc
#define FLASH_TOC_START CY_TOC_START
#define FLASH_TOC_SIZE CY_TOC_SIZE
; Emulated EEPROM Flash area
#define EM_EEPROM_START CY_APP0_CORE1_EM_EEPROM_ADDR
#define EM_EEPROM_SIZE CY_APP0_CORE1_EM_EEPROM_LENGTH
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000400
; External memory
#define XIP_START CY_APP0_CORE1_SMIF_ADDR
#define XIP_SIZE CY_APP0_CORE1_SMIF_LENGTH
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; RAM
#define RAM_START CY_APP0_CORE1_RAM_ADDR
#define RAM_SIZE CY_APP0_CORE1_RAM_LENGTH
LR_FLASH FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_COMMON CY_APP_RAM_COMMON_ADDR UNINIT
{
* (.cy_boot_noinit.appId)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
ER_RAM_DATA +0
{
* (.cy_ramfunc)
.ANY (+RW, +ZI)
}
; Place variables in the section that should not be initialized during
; a device startup.
ER_RAM_NOINIT_DATA +0 UNINIT
{
* (.noinit)
}
; Used for the digital signature of the secure application and the
; DFU SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - CY_BOOT_SIGNATURE_SIZE) FIXED
{
* (.cy_app_signature)
}
}
; App0 uses it to initialize DFU SDK metadata, in dfu_user.c file
LR_CY_BOOT_METADATA CY_BOOT_META_FLASH_ADDR CY_BOOT_META_FLASH_LENGTH
{
.cy_boot_metadata + 0
{
* (.cy_boot_metadata)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory Flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory Flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory Flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory Flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
.cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* [] END OF FILE */

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/*******************************************************************************
* \file dfu_mdk_common.h
* \version 3.0
*
* This file provides only macro definitions to use for
* project configuration.
* They may be used in both scatter files and source code files.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#ifndef DFU_MDK_COMMON_H_
#define DFU_MDK_COMMON_H_
/* DFU SDK parameters */
/* The user application may either update them or leave the defaults if they fit */
#define CY_BOOT_METADATA_ADDR 0x100FFA00
#define CY_BOOT_METADATA_LENGTH 0x200
#define CY_PRODUCT_ID 0x01020304
#define CY_CHECKSUM_TYPE 0x00
/*
* The size of the section .cy_app_signature.
* 1,2, or 4 for a checksum
* 4 for CRC-32
* 20 for SHA1
* 32 for SHA256
* 256 for RSASSA-PKCS1-v1.5 with the 2048 bit RSA key.
*
* SHA1 must be used.
*/
#define CY_BOOT_SIGNATURE_SIZE 4
/* For the MDK linker script, defines TOC parameters */
/* Update per device series to be in the last Flash row */
#define CY_TOC_START 0x16007C00
#define CY_TOC_SIZE 0x400
/* Memory region ranges per core and app */
#define CY_APP0_CORE0_FLASH_ADDR 0x10000000
#define CY_APP0_CORE0_FLASH_LENGTH 0x10000
#define CY_APP0_CORE1_FLASH_ADDR 0x10010000
#define CY_APP0_CORE1_FLASH_LENGTH 0x10000
#define CY_APP1_CORE0_FLASH_ADDR 0x10040000
#define CY_APP1_CORE0_FLASH_LENGTH 0x10000
#define CY_APP1_CORE1_FLASH_ADDR 0x10050000
#define CY_APP1_CORE1_FLASH_LENGTH 0x10000
/* DFU SDK metadata address range in Flash */
#define CY_BOOT_META_FLASH_ADDR 0x100FFA00
#define CY_BOOT_META_FLASH_LENGTH 0x200
/* Application ranges in emulated EEPROM */
#define CY_APP0_CORE0_EM_EEPROM_ADDR 0x14000000
#define CY_APP0_CORE0_EM_EEPROM_LENGTH 0x00000000
#define CY_APP0_CORE1_EM_EEPROM_ADDR (CY_APP0_CORE0_EM_EEPROM_ADDR + CY_APP0_CORE0_EM_EEPROM_LENGTH)
#define CY_APP0_CORE1_EM_EEPROM_LENGTH 0x0000
#define CY_APP1_CORE0_EM_EEPROM_ADDR 0x14000000
#define CY_APP1_CORE0_EM_EEPROM_LENGTH 0x00000000
#define CY_APP1_CORE1_EM_EEPROM_ADDR (CY_APP1_CORE0_EM_EEPROM_ADDR + CY_APP1_CORE0_EM_EEPROM_LENGTH)
#define CY_APP1_CORE1_EM_EEPROM_LENGTH 0x00000000
/* Application ranges in SMIF XIP */
#define CY_APP0_CORE0_SMIF_ADDR 0x18000000
#define CY_APP0_CORE0_SMIF_LENGTH 0x00000000
#define CY_APP0_CORE1_SMIF_ADDR (CY_APP0_CORE0_SMIF_ADDR + CY_APP0_CORE0_SMIF_LENGTH)
#define CY_APP0_CORE1_SMIF_LENGTH 0x00000000
#define CY_APP1_CORE0_SMIF_ADDR 0x14000200
#define CY_APP1_CORE0_SMIF_LENGTH 0x00000000
#define CY_APP1_CORE1_SMIF_ADDR (CY_APP1_CORE0_SMIF_ADDR + CY_APP1_CORE0_SMIF_LENGTH)
#define CY_APP1_CORE1_SMIF_LENGTH 0x00000000
/* Application ranges in RAM */
#define CY_APP_RAM_COMMON_ADDR 0x08000000
#define CY_APP_RAM_COMMON_LENGTH 0x00000100
/* note: all the CY_APPX_CORE0_RAM regions has to be 0x100 aligned */
/* and the CY_APPX_CORE1_RAM regions has to be 0x400 aligned */
/* as they contain Interrupt Vector Table Remapped at the start */
#define CY_APP0_CORE0_RAM_ADDR 0x08000100
#define CY_APP0_CORE0_RAM_LENGTH 0x00001F00
#define CY_APP0_CORE1_RAM_ADDR (CY_APP0_CORE0_RAM_ADDR + CY_APP0_CORE0_RAM_LENGTH)
#define CY_APP0_CORE1_RAM_LENGTH 0x00008000
#define CY_APP1_CORE0_RAM_ADDR CY_APP0_CORE0_RAM_ADDR
#define CY_APP1_CORE0_RAM_LENGTH 0x00001F00
#define CY_APP1_CORE1_RAM_ADDR (CY_APP1_CORE0_RAM_ADDR + CY_APP1_CORE0_RAM_LENGTH)
#define CY_APP1_CORE1_RAM_LENGTH 0x00008000
__asm void cy_DFU_mdkAsmDummy(void);
#endif /* DFU_MDK_COMMON_H_ */
/* [] END OF FILE */

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/*******************************************************************************
* \file dfu_mdk_symbols.c
* \version 3.0
*
* This file provides symbols to add to an ELF file required by
* CyMCUElfTool to generate correct HEX and CYACD2 files.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "dfu_mdk_common.h"
/*******************************************************************************
* Function Name: cy_DFU_mdkAsmDummy
********************************************************************************
* This function provides ELF file symbols through
* the inline assembly.
* The inline assembly in the *.c file is chosen, because it allows using
* #include <mdk_linker_common.h> where the user configuration is updated.
*
* Note that this function does not have code, so no additional memory
* is allocated for it.
*******************************************************************************/
__asm void cy_DFU_mdkAsmDummy(void)
{
EXPORT __cy_boot_metadata_addr
EXPORT __cy_boot_metadata_length
EXPORT __cy_app_core1_start_addr
EXPORT __cy_product_id
EXPORT __cy_checksum_type
EXPORT __cy_app_id
EXPORT __cy_app_verify_start
EXPORT __cy_app_verify_length
/* Used by all DFU SDK applications to switch to another app */
__cy_boot_metadata_addr EQU __cpp(CY_BOOT_METADATA_ADDR)
/* Used by CyMCUElfTool to update DFU SDK metadata with CRC-32C */
__cy_boot_metadata_length EQU __cpp(CY_BOOT_METADATA_LENGTH)
/* Used by CM0+ to start CM4 core in the DFU SDK applications. */
/* Make sure the correct app no. is entered here */
__cy_app_core1_start_addr EQU __cpp(CY_APP0_CORE1_FLASH_ADDR)
/* Used by CyMCUElfTool to generate ProductID */
__cy_product_id EQU __cpp(CY_PRODUCT_ID)
/* Used by CyMCUElfTool to generate ChecksumType */
__cy_checksum_type EQU __cpp(CY_CHECKSUM_TYPE)
/* Application number (ID) */
__cy_app_id EQU 0
/* CyMCUElfTool uses these to generate an application signature */
/* The size of the default signature (CRC-32C) is 4 bytes */
__cy_app_verify_start EQU __cpp(CY_APP0_CORE0_FLASH_ADDR)
__cy_app_verify_length EQU __cpp(CY_APP0_CORE0_FLASH_LENGTH + CY_APP0_CORE1_FLASH_LENGTH - CY_BOOT_SIGNATURE_SIZE)
}
/* [] END OF FILE */

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/***************************************************************************//**
* \file dfu_user.c
* \version 3.0
*
* This file provides the custom API for a firmware application with
* DFU SDK.
* - Cy_DFU_ReadData (address, length, ctl, params) - to read the NVM block
* - Cy_DFU_WriteData(address, length, ctl, params) - to write the NVM block
*
* - Cy_DFU_TransportStart() to start a communication interface
* - Cy_DFU_TransportStop () to stop a communication interface
* - Cy_DFU_TransportReset() to reset a communication interface
* - Cy_DFU_TransportRead (buffer, size, count, timeout)
* - Cy_DFU_TransportWrite(buffer, size, count, timeout)
*
********************************************************************************
* \copyright
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <string.h>
#include "transport_ble.h"
#include "cy_syslib.h"
#include "cy_flash.h"
#include "cy_dfu.h"
/*
* The DFU SDK metadata initial value is placed here
* Note: the number of elements equal to the number of the app multiplies by 2
* because of the two fields per app plus one element for the CRC-32C field.
*/
CY_SECTION(".cy_boot_metadata") __USED
static const uint32_t cy_dfu_metadata[CY_FLASH_SIZEOF_ROW / sizeof(uint32_t)] =
{
CY_DFU_APP0_VERIFY_START, CY_DFU_APP0_VERIFY_LENGTH, /* The App0 base address and length */
CY_DFU_APP1_VERIFY_START, CY_DFU_APP1_VERIFY_LENGTH, /* The App1 base address and length */
0u /* The rest does not matter */
};
static uint32_t IsMultipleOf(uint32_t value, uint32_t multiple);
static void GetStartEndAddress(uint32_t appId, uint32_t *startAddress, uint32_t *endAddress);
/*******************************************************************************
* Function Name: IsMultipleOf
****************************************************************************//**
*
* This internal function check if value parameter is a multiple of parameter
* multiple
*
* \param value value that will be checked
* \param multiple value with which value is checked
*
* \return 1 - value is multiple of parameter multiple, else 0
*
*******************************************************************************/
static uint32_t IsMultipleOf(uint32_t value, uint32_t multiple)
{
return ( ((value % multiple) == 0u)? 1ul : 0ul);
}
/*******************************************************************************
* Function Name: GetStartEndAddress
****************************************************************************//**
*
* This internal function returns start and end address of application
*
* \param appId The application number
* \param startAddress The pointer to a variable where an application start
* address is stored
* \param endAddress The pointer to a variable where a size of application
* area is stored.
*
*******************************************************************************/
static void GetStartEndAddress(uint32_t appId, uint32_t *startAddress, uint32_t *endAddress)
{
uint32_t verifyStart;
uint32_t verifySize;
(void)Cy_DFU_GetAppMetadata(appId, &verifyStart, &verifySize);
#if (CY_DFU_APP_FORMAT == CY_DFU_SIMPLIFIED_APP)
*startAddress = verifyStart - CY_DFU_SIGNATURE_SIZE;
*endAddress = verifyStart + verifySize;
#else
*startAddress = verifyStart;
*endAddress = verifyStart + verifySize + CY_DFU_SIGNATURE_SIZE;
#endif
}
/*******************************************************************************
* Function Name: Cy_DFU_WriteData
****************************************************************************//**
*
* This function documentation is part of the DFU SDK API, see the
* cy_dfu.h file or DFU SDK API Reference Manual for details.
*
*******************************************************************************/
cy_en_dfu_status_t Cy_DFU_WriteData (uint32_t address, uint32_t length, uint32_t ctl,
cy_stc_dfu_params_t *params)
{
/* User Flash Limits */
/* Note that App0 is out of range */
const uint32_t minUFlashAddress = CY_FLASH_BASE + CY_DFU_APP0_VERIFY_LENGTH;
const uint32_t maxUFlashAddress = CY_FLASH_BASE + CY_FLASH_SIZE;
/* EM_EEPROM Limits*/
const uint32_t minEmEepromAddress = CY_EM_EEPROM_BASE;
const uint32_t maxEmEepromAddress = CY_EM_EEPROM_BASE + CY_EM_EEPROM_SIZE;
cy_en_dfu_status_t status = CY_DFU_SUCCESS;
uint32_t app = Cy_DFU_GetRunningApp();
uint32_t startAddress;
uint32_t endAddress;
GetStartEndAddress(app, &startAddress, &endAddress);
/* Check if the address and length are valid
* Note Length = 0 is valid for erase command */
if ( (IsMultipleOf(address, CY_FLASH_SIZEOF_ROW) == 0u) ||
( (length != CY_FLASH_SIZEOF_ROW) && ( (ctl & CY_DFU_IOCTL_ERASE) == 0u) ) )
{
status = CY_DFU_ERROR_LENGTH;
}
/* Refuse to write to a row within a range of the current application */
if ( (startAddress <= address) && (address < endAddress) )
{ /* It is forbidden to overwrite the currently running application */
status = CY_DFU_ERROR_ADDRESS;
}
#if CY_DFU_OPT_GOLDEN_IMAGE
if (status == CY_DFU_SUCCESS)
{
uint8_t goldenImages[] = { CY_DFU_GOLDEN_IMAGE_IDS() };
uint32_t count = sizeof(goldenImages) / sizeof(goldenImages[0]);
uint32_t idx;
for (idx = 0u; idx < count; ++idx)
{
app = goldenImages[idx];
GetStartEndAddress(app, &startAddress, &endAddress);
if ( (startAddress <= address) && (address < endAddress) )
{
status = Cy_DFU_ValidateApp(app, params);
status = (status == CY_DFU_SUCCESS) ? CY_DFU_ERROR_ADDRESS : CY_DFU_SUCCESS;
break;
}
}
}
#endif /* #if CY_DFU_OPT_GOLDEN_IMAGE != 0 */
/* Check if the address is inside the valid range */
if ( ( (minUFlashAddress <= address) && (address < maxUFlashAddress) )
|| ( (minEmEepromAddress <= address) && (address < maxEmEepromAddress) ) )
{ /* Do nothing, this is an allowed memory range to update to */
}
else
{
status = CY_DFU_ERROR_ADDRESS;
}
if (status == CY_DFU_SUCCESS)
{
if ((ctl & CY_DFU_IOCTL_ERASE) != 0u)
{
(void) memset(params->dataBuffer, 0, CY_FLASH_SIZEOF_ROW);
}
cy_en_flashdrv_status_t fstatus = Cy_Flash_WriteRow(address, (uint32_t*)params->dataBuffer);
status = (fstatus == CY_FLASH_DRV_SUCCESS) ? CY_DFU_SUCCESS : CY_DFU_ERROR_DATA;
}
return (status);
}
/*******************************************************************************
* Function Name: Cy_DFU_ReadData
****************************************************************************//**
*
* This function documentation is part of the DFU SDK API, see the
* cy_dfu.h file or DFU SDK API Reference Manual for details.
*
*******************************************************************************/
cy_en_dfu_status_t Cy_DFU_ReadData (uint32_t address, uint32_t length, uint32_t ctl,
cy_stc_dfu_params_t *params)
{
/* User Flash Limits */
/* Note that App0 is out of range */
const uint32_t minUFlashAddress = CY_FLASH_BASE + CY_DFU_APP0_VERIFY_LENGTH;
const uint32_t maxUFlashAddress = CY_FLASH_BASE + CY_FLASH_SIZE;
/* EM_EEPROM Limits*/
const uint32_t minEmEepromAddress = CY_EM_EEPROM_BASE;
const uint32_t maxEmEepromAddress = CY_EM_EEPROM_BASE + CY_EM_EEPROM_SIZE;
cy_en_dfu_status_t status = CY_DFU_SUCCESS;
/* Check if the length is valid */
if (IsMultipleOf(length, CY_FLASH_SIZEOF_ROW) == 0u)
{
status = CY_DFU_ERROR_LENGTH;
}
/* Check if the address is inside the valid range */
if ( ( (minUFlashAddress <= address) && (address < maxUFlashAddress) )
|| ( (minEmEepromAddress <= address) && (address < maxEmEepromAddress) ) )
{ /* Do nothing, this is an allowed memory range to update to */
}
else
{
status = CY_DFU_ERROR_ADDRESS;
}
/* Read or Compare */
if (status == CY_DFU_SUCCESS)
{
if ((ctl & CY_DFU_IOCTL_COMPARE) == 0u)
{
(void) memcpy(params->dataBuffer, (const void *)address, length);
status = CY_DFU_SUCCESS;
}
else
{
status = ( memcmp(params->dataBuffer, (const void *)address, length) == 0 )
? CY_DFU_SUCCESS : CY_DFU_ERROR_VERIFY;
}
}
return (status);
}
/*******************************************************************************
* Function Name: Cy_DFU_TransportRead
****************************************************************************//**
*
* This function documentation is part of the DFU SDK API, see the
* cy_dfu.h file or DFU SDK API Reference Manual for details.
*
*******************************************************************************/
cy_en_dfu_status_t Cy_DFU_TransportRead (uint8_t *buffer, uint32_t size, uint32_t *count, uint32_t timeout)
{
return (CyBLE_CyBtldrCommRead(buffer, size, count, timeout));
}
/*******************************************************************************
* Function Name: Cy_DFU_TransportWrite
****************************************************************************//**
*
* This function documentation is part of the DFU SDK API, see the
* cy_dfu.h file or DFU SDK API Reference Manual for details.
*
*******************************************************************************/
cy_en_dfu_status_t Cy_DFU_TransportWrite(uint8_t *buffer, uint32_t size, uint32_t *count, uint32_t timeout)
{
return (CyBLE_CyBtldrCommWrite(buffer, size, count, timeout));
}
/*******************************************************************************
* Function Name: Cy_DFU_TransportReset
****************************************************************************//**
*
* This function documentation is part of the DFU SDK API, see the
* cy_dfu.h file or DFU SDK API Reference Manual for details.
*
*******************************************************************************/
void Cy_DFU_TransportReset(void)
{
CyBLE_CyBtldrCommReset();
}
/*******************************************************************************
* Function Name: Cy_DFU_TransportStart
****************************************************************************//**
*
* This function documentation is part of the DFU SDK API, see the
* cy_dfu.h file or DFU SDK API Reference Manual for details.
*
*******************************************************************************/
void Cy_DFU_TransportStart(void)
{
CyBLE_CyBtldrCommStart();
}
/*******************************************************************************
* Function Name: Cy_DFU_TransportStop
****************************************************************************//**
*
* This function documentation is part of the DFU SDK API, see the
* cy_dfu.h file or DFU SDK API Reference Manual for details.
*
*******************************************************************************/
void Cy_DFU_TransportStop(void)
{
CyBLE_CyBtldrCommStop();
}
/* [] END OF FILE */

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/***************************************************************************//**
* \file dfu_user.h
* \version 3.0
*
* This file provides declarations that can be modified by the user but
* are used by the DFU SDK.
*
********************************************************************************
* \copyright
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(DFU_USER_H)
#define DFU_USER_H
#include <stdint.h>
#include "cy_flash.h"
/**
* \addtogroup group_dfu_macro_config
* \{
*/
/** The size of a buffer to hold DFU commands */
/* 16 bytes is a maximum overhead of a DFU packet and additional data for the Program Data command */
#define CY_DFU_SIZEOF_CMD_BUFFER (CY_FLASH_SIZEOF_ROW + 16u)
/** The size of a buffer to hold an NVM row of data to write or verify */
#define CY_DFU_SIZEOF_DATA_BUFFER (CY_FLASH_SIZEOF_ROW + 16u)
/**
* Set to non-zero for the DFU SDK Program Data command to check
* if the Golden image is going to be overwritten while updating.
*/
#define CY_DFU_OPT_GOLDEN_IMAGE (0)
/**
* List of Golden Image Application IDs.
* Here "Golden Image Application" means an application that cannot be changed with
* CommandProgramData()
*
* Usage. Define the list of Golden Image Application IDs without enclosing
* parenthesis, e.g.
* \code #define CY_DFU_GOLDEN_IMAGE_IDS() 0u, 1u, 3u \endcode
* later it is used in cy_dfu.c file:
* \code uint8_t goldenImages[] = { CY_DFU_GOLDEN_IMAGE_IDS() }; \endcode
*/
#define CY_DFU_GOLDEN_IMAGE_IDS() 0u
/**
* The number of applications in the metadata,
* for 512 bytes in a Flash row - 63 is the maximum possible value,
* because 4 bytes are reserved for the entire metadata CRC.
*
* The smallest metadata size if CY_DFU_MAX_APPS * 8 (bytes per one app) + 4 (bytes for CRC-32C)
*/
#define CY_DFU_MAX_APPS (2u)
/** A non-zero value enables the Verify Data DFU command */
#define CY_DFU_OPT_VERIFY_DATA (1)
/** A non-zero value enables the Erase Data DFU command */
#define CY_DFU_OPT_ERASE_DATA (1)
/** A non-zero value enables the Verify App DFU command */
#define CY_DFU_OPT_VERIFY_APP (1)
/**
* A non-zero value enables the Send Data DFU command.
* If the "Send Data" DFU command is enabled, \c packetBuffer and \c dataBuffer
* must be non-overlapping.
*
* Else, \c dataBuffer must be inside \c packetBuffer with an offset of
* \c CY_DFU_PACKET_DATA_IDX, typically 4 bytes. \n
* <code>params->dataBuffer = &packetBuffer[4];</code> \n
* \note that \c packetBuffer in this case must be 4 bytes aligned, as
* \c dataBuffer is required to be 4 bytes aligned.
*/
#define CY_DFU_OPT_SEND_DATA (1)
/** A non-zero value enables the Get Metadata DFU command */
#define CY_DFU_OPT_GET_METADATA (1)
/** A non-zero value enables the Set EI Vector DFU command */
#define CY_DFU_OPT_SET_EIVECTOR (0)
/**
* A non-zero value allows writing metadata
* with the Set App Metadata DFU command.
*/
#define CY_DFU_METADATA_WRITABLE (1)
/** Non-zero value enables the usage of hardware Crypto API */
#define CY_DFU_OPT_CRYPTO_HW (1)
/** A non-zero value enables the usage of CRC-16 for DFU packet verification */
#define CY_DFU_OPT_PACKET_CRC (0)
/** Set the default application-format-possible values defined in \ref group_dfu_macro_app_type */
#define CY_DFU_APP_FORMAT (CY_DFU_CYPRESS_APP)
/** Set the default secure application-verification-type possible values
* defined in \ref group_dfu_macro_ver_type */
#define CY_DFU_SEC_APP_VERIFY_TYPE (CY_DFU_VERIFY_FAST)
/** \} group_dfu_macro_config */
#if !defined(CY_DOXYGEN)
#if defined(__GNUC__) || defined(__ICCARM__)
/*
* These variables are defined in the linker scripts, the values of their addresses define
* corresponding applications start address and length.
*/
extern uint8_t __cy_app0_verify_start;
extern uint8_t __cy_app0_verify_length;
extern uint8_t __cy_app1_verify_start;
extern uint8_t __cy_app1_verify_length;
extern uint8_t __cy_boot_signature_size;
#define CY_DFU_APP0_VERIFY_START ( (uint32_t)&__cy_app0_verify_start )
#define CY_DFU_APP0_VERIFY_LENGTH ( (uint32_t)&__cy_app0_verify_length )
#define CY_DFU_APP1_VERIFY_START ( (uint32_t)&__cy_app1_verify_start )
#define CY_DFU_APP1_VERIFY_LENGTH ( (uint32_t)&__cy_app1_verify_length )
#define CY_DFU_SIGNATURE_SIZE ( (uint32_t)&__cy_boot_signature_size )
#elif defined(__ARMCC_VERSION)
#include "dfu_mdk_common.h"
#define CY_DFU_APP0_VERIFY_START ( CY_APP0_CORE0_FLASH_ADDR )
#define CY_DFU_APP0_VERIFY_LENGTH ( CY_APP0_CORE0_FLASH_LENGTH + CY_APP0_CORE1_FLASH_LENGTH \
- CY_BOOT_SIGNATURE_SIZE)
#define CY_DFU_APP1_VERIFY_START ( CY_APP1_CORE0_FLASH_ADDR )
#define CY_DFU_APP1_VERIFY_LENGTH ( CY_APP1_CORE0_FLASH_LENGTH + CY_APP1_CORE1_FLASH_LENGTH \
- CY_BOOT_SIGNATURE_SIZE)
#define CY_DFU_SIGNATURE_SIZE CY_BOOT_SIGNATURE_SIZE
#else
#error "Not implemented for this compiler"
#endif /* defined(__GNUC__) || defined(__ICCARM__) */
#endif /* !defined(CY_DOXYGEN) */
#endif /* !defined(DFU_USER_H) */
/* [] END OF FILE */

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/**************************************************************************//**
* @file startup_psoc6_01_cm0plus.S
* @brief CMSIS Core Device Startup File for
* ARMCM0plus Device Series
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Address of the NMI handler */
#define CY_NMI_HANLDER_ADDR 0x0000000D
/* The CPU VTOR register */
#define CY_CPU_VTOR_ADDR 0xE000ED08
/* Copy flash vectors and data section to RAM */
#define __STARTUP_COPY_MULTIPLE
/* Clear single BSS section */
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts Description */
.long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
.long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
.long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
.long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
.long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
.long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
.long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
.long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
.long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
.long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
.long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
.long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
.long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
.long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
.long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
.long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
.long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
.long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
.long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
.long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
.long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
.long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
.long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
.long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
.long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
.long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
.long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
.long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
.long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
.long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
.long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
.long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
.size __Vectors, . - __Vectors
.equ __VectorsSize, . - __Vectors
.section .ram_vectors
.align 2
.globl __ramVectors
__ramVectors:
.space __VectorsSize
.size __ramVectors, . - __ramVectors
.text
.thumb
.thumb_func
.align 2
/*
* Device startup customization
*
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
* because this function is executed as the first instruction in the ResetHandler.
* The PDL is also not initialized to use the proper register offsets.
* The user of this function is responsible for initializing the PDL and resources before using them.
*/
.weak Cy_OnResetUser
.func Cy_OnResetUser, Cy_OnResetUser
.type Cy_OnResetUser, %function
Cy_OnResetUser:
bx lr
.size Cy_OnResetUser, . - Cy_OnResetUser
.endfunc
/* Reset handler */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
blt .L_loop0_0_done
ldr r0, [r1, r3]
str r0, [r2, r3]
b .L_loop0_0
.L_loop0_0_done:
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .L_loop1_done
.L_loop1:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
blt .L_loop2_0_done
str r0, [r1, r2]
b .L_loop2_0
.L_loop2_0_done:
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Update Vector Table Offset Register. */
ldr r0, =__ramVectors
ldr r1, =CY_CPU_VTOR_ADDR
str r0, [r1]
dsb 0xF
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
bl main
/* Should never get here */
b .
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.weak Cy_SysLib_FaultHandler
.type Cy_SysLib_FaultHandler, %function
Cy_SysLib_FaultHandler:
b .
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
.type Fault_Handler, %function
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
.macro def_fault_Handler fault_handler_name
.weak \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_fault_Handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
.end
/* [] END OF FILE */

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@ -0,0 +1,635 @@
/**************************************************************************//**
* @file startup_psoc6_01_cm4.S
* @brief CMSIS Core Device Startup File for
* ARMCM4 Device Series
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Address of the NMI handler */
#define CY_NMI_HANLDER_ADDR 0x0000000D
/* The CPU VTOR register */
#define CY_CPU_VTOR_ADDR 0xE000ED08
/* Copy flash vectors and data section to RAM */
#define __STARTUP_COPY_MULTIPLE
/* Clear single BSS section */
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts Description */
.long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
.long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
.long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
.long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
.long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
.long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
.long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
.long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
.long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
.long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
.long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
.long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
.long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
.long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
.long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
.long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
.long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
.long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
.long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
.long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
.long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
.long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
.long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
.long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
.long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
.long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
.long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
.long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
.long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
.long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
.long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
.long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
.long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
.long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
.long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
.long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
.long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
.long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
.long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
.long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
.long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
.long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
.long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
.long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
.long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
.long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
.long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
.long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
.long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
.long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
.long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
.long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
.long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
.long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
.long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
.long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
.long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
.long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
.long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
.long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
.long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
.long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
.long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
.long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
.long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
.long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
.long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
.long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
.long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
.long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
.long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
.long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
.long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
.long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
.long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
.long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
.long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
.long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
.long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
.long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
.long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
.long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
.long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
.long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
.long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
.long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
.long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
.long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
.long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
.long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
.long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
.long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
.long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
.long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
.long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
.long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
.long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
.long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
.long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
.long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
.long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
.long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
.long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
.long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
.long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
.long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
.long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
.long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
.long usb_interrupt_med_IRQHandler /* USB Interrupt */
.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
.long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
.size __Vectors, . - __Vectors
.equ __VectorsSize, . - __Vectors
.section .ram_vectors
.align 2
.globl __ramVectors
__ramVectors:
.space __VectorsSize
.size __ramVectors, . - __ramVectors
.text
.thumb
.thumb_func
.align 2
/*
* Device startup customization
*
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
* because this function is executed as the first instruction in the ResetHandler.
* The PDL is also not initialized to use the proper register offsets.
* The user of this function is responsible for initializing the PDL and resources before using them.
*/
.weak Cy_OnResetUser
.func Cy_OnResetUser, Cy_OnResetUser
.type Cy_OnResetUser, %function
Cy_OnResetUser:
bx lr
.size Cy_OnResetUser, . - Cy_OnResetUser
.endfunc
/* Reset handler */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Update Vector Table Offset Register. */
ldr r0, =__ramVectors
ldr r1, =CY_CPU_VTOR_ADDR
str r0, [r1]
dsb 0xF
/* Enable the FPU if used */
bl Cy_SystemInitFpuEnable
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
bl main
/* Should never get here */
b .
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.weak Cy_SysLib_FaultHandler
.type Cy_SysLib_FaultHandler, %function
Cy_SysLib_FaultHandler:
b .
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
.type Fault_Handler, %function
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
.macro def_fault_Handler fault_handler_name
.weak \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_fault_Handler HardFault_Handler
def_fault_Handler MemManage_Handler
def_fault_Handler BusFault_Handler
def_fault_Handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
.end
/* [] END OF FILE */

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;/**************************************************************************//**
; * @file startup_psoc6_01_cm0plus.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0plus Device Series
; * @version V5.00
; * @date 08. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec_ram:DATA:NOROOT(2)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
EXTERN __iar_data_init3
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
PUBLIC __ramVectors
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD 0x0000000D ; NMI_Handler is defined in ROM code
DCD HardFault_Handler
DCD 0
DCD 0
DCD 0
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD 0
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External interrupts Power Mode Description
DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10
DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11
DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12
DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13
DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14
DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15
DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16
DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17
DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18
DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19
DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20
DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21
DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22
DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23
DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24
DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25
DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26
DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27
DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28
DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29
DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30
DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
__ramVectors
DS32 __Vectors_Size
THUMB
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default handlers
;;
PUBWEAK Default_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Default_Handler
B Default_Handler
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Weak function for startup customization
;;
;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
;; because this function is executed as the first instruction in the ResetHandler.
;; The PDL is also not initialized to use the proper register offsets.
;; The user of this function is responsible for initializing the PDL and resources before using them.
;;
PUBWEAK Cy_OnResetUser
SECTION .text:CODE:REORDER:NOROOT(2)
Cy_OnResetUser
BX LR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Define strong version to return zero for
;; __iar_program_start to skip data sections
;; initialization.
;;
PUBLIC __low_level_init
SECTION .text:CODE:REORDER:NOROOT(2)
__low_level_init
MOVS R0, #0
BX LR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
; Define strong function for startup customization
LDR R0, =Cy_OnResetUser
BLX R0
; Disable global interrupts
CPSID I
; Copy vectors from ROM to RAM
LDR r1, =__vector_table
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
intvec_copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE intvec_copy
; Update Vector Table Offset Register
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb
; Initialize data sections
LDR R0, =__iar_data_init3
BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BLX R0
; Should never get here
Cy_Main_Exited
B Cy_Main_Exited
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK Cy_SysLib_FaultHandler
SECTION .text:CODE:REORDER:NOROOT(1)
Cy_SysLib_FaultHandler
B Cy_SysLib_FaultHandler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
IMPORT Cy_SysLib_FaultHandler
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
b L_API_call
L_MSP
mrs r0, MSP
L_API_call
; Storing LR content for Creator call stack trace
push {LR}
bl Cy_SysLib_FaultHandler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
; External interrupts
PUBWEAK NvicMux0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux0_IRQHandler
B NvicMux0_IRQHandler
PUBWEAK NvicMux1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux1_IRQHandler
B NvicMux1_IRQHandler
PUBWEAK NvicMux2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux2_IRQHandler
B NvicMux2_IRQHandler
PUBWEAK NvicMux3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux3_IRQHandler
B NvicMux3_IRQHandler
PUBWEAK NvicMux4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux4_IRQHandler
B NvicMux4_IRQHandler
PUBWEAK NvicMux5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux5_IRQHandler
B NvicMux5_IRQHandler
PUBWEAK NvicMux6_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux6_IRQHandler
B NvicMux6_IRQHandler
PUBWEAK NvicMux7_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux7_IRQHandler
B NvicMux7_IRQHandler
PUBWEAK NvicMux8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux8_IRQHandler
B NvicMux8_IRQHandler
PUBWEAK NvicMux9_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux9_IRQHandler
B NvicMux9_IRQHandler
PUBWEAK NvicMux10_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux10_IRQHandler
B NvicMux10_IRQHandler
PUBWEAK NvicMux11_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux11_IRQHandler
B NvicMux11_IRQHandler
PUBWEAK NvicMux12_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux12_IRQHandler
B NvicMux12_IRQHandler
PUBWEAK NvicMux13_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux13_IRQHandler
B NvicMux13_IRQHandler
PUBWEAK NvicMux14_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux14_IRQHandler
B NvicMux14_IRQHandler
PUBWEAK NvicMux15_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux15_IRQHandler
B NvicMux15_IRQHandler
PUBWEAK NvicMux16_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux16_IRQHandler
B NvicMux16_IRQHandler
PUBWEAK NvicMux17_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux17_IRQHandler
B NvicMux17_IRQHandler
PUBWEAK NvicMux18_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux18_IRQHandler
B NvicMux18_IRQHandler
PUBWEAK NvicMux19_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux19_IRQHandler
B NvicMux19_IRQHandler
PUBWEAK NvicMux20_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux20_IRQHandler
B NvicMux20_IRQHandler
PUBWEAK NvicMux21_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux21_IRQHandler
B NvicMux21_IRQHandler
PUBWEAK NvicMux22_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux22_IRQHandler
B NvicMux22_IRQHandler
PUBWEAK NvicMux23_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux23_IRQHandler
B NvicMux23_IRQHandler
PUBWEAK NvicMux24_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux24_IRQHandler
B NvicMux24_IRQHandler
PUBWEAK NvicMux25_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux25_IRQHandler
B NvicMux25_IRQHandler
PUBWEAK NvicMux26_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux26_IRQHandler
B NvicMux26_IRQHandler
PUBWEAK NvicMux27_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux27_IRQHandler
B NvicMux27_IRQHandler
PUBWEAK NvicMux28_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux28_IRQHandler
B NvicMux28_IRQHandler
PUBWEAK NvicMux29_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux29_IRQHandler
B NvicMux29_IRQHandler
PUBWEAK NvicMux30_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux30_IRQHandler
B NvicMux30_IRQHandler
PUBWEAK NvicMux31_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
NvicMux31_IRQHandler
B NvicMux31_IRQHandler
END
; [] END OF FILE

1142
2020TPCApp0.cydsn/iar/startup_psoc6_01_cm4.s Normal file
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62
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/*******************************************************************************
* File Name: ias.c
*
* Description:
* This file contains Immediate Alert Service callback handler function.
*
********************************************************************************
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "ias.h"
/* IAS alert level value */
volatile uint8_t alertLevel = 0;
/******************************************************************************
* Function Name: IasInit
*******************************************************************************
*
* Summary:
* Registers the IAS CallBack.
*
******************************************************************************/
void IasInit(void)
{
Cy_BLE_IAS_RegisterAttrCallback(IasEventHandler);
}
/*******************************************************************************
* Function Name: IasEventHandler
********************************************************************************
*
* Summary:
* This is an event callback function to receive events from the BLE Component,
* which are specific to Immediate Alert Service.
*
* Parameters:
* event: Write Command event from the BLE component.
* eventParams: A structure instance of CY_BLE_GATT_HANDLE_VALUE_PAIR_T type.
*
*******************************************************************************/
void IasEventHandler(uint32 event, void *eventParam)
{
(void) eventParam;
uint8_t alert;
/* Alert Level Characteristic write event */
if(event == CY_BLE_EVT_IASS_WRITE_CHAR_CMD)
{
/* Read the updated Alert Level value from the GATT database */
Cy_BLE_IASS_GetCharacteristicValue(CY_BLE_IAS_ALERT_LEVEL, sizeof(alert), &alert);
alertLevel = alert;
}
}
/* [] END OF FILE */

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/*******************************************************************************
* File Name: ias.h
*
* Description:
* Contains the function prototypes and references for the Immediate Alert
* Service of the Bluetooth Component.
*
********************************************************************************
* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "project.h"
/***************************************
* Function Prototypes
***************************************/
void IasInit(void);
void IasEventHandler(uint32_t event, void *eventParam);
/***************************************
* External data references
***************************************/
extern volatile uint8_t alertLevel;
/* [] END OF FILE */

78
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:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
::
:: File Name: key_copy.bat
::
:: Version: 1.01
::
:: Description:
:: Simple script to copy generated key files to a persistent location
::
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
:: Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
:: This software is owned by Cypress Semiconductor Corporation and is protected
:: by and subject to worldwide patent and copyright laws and treaties.
:: Therefore, you may use this software only as provided in the license agreement
:: accompanying the software package from which you obtained this software.
:: CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
:: WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT,
:: IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
@echo off
set OUT_DIR="..\Keys"
set LOCAL_DIR=keys_generated
set SRC_PRIV_NAME=rsa_private_generated.txt
set SRC_PUB_NAME=rsa_public_generated.txt
set SRC_AES_NAME=aes_private_generated.txt
set SRC_EIV_NAME=aes_eiv_generated.txt
set PRIV_NAME=rsa_private.txt
set PUB_NAME=rsa_public.txt
set AES_NAME=aes_private.txt
set EIV_NAME=aes_eiv.txt
:: File Check
set ALLOK=1
IF NOT EXIST %LOCAL_DIR%\%SRC_PRIV_NAME% (
echo File %SRC_PRIV_NAME% does not exist.
set ALLOK=0
)
IF NOT EXIST %LOCAL_DIR%\%SRC_PUB_NAME% (
echo File %SRC_PUB_NAME% does not exist.
set ALLOK=0
)
IF NOT EXIST %LOCAL_DIR%\%SRC_AES_NAME% (
echo File %SRC_AES_NAME% does not exist.
set ALLOK=0
)
IF NOT EXIST %LOCAL_DIR%\%SRC_EIV_NAME% (
echo File %SRC_EIV_NAME% does not exist.
set ALLOK=0
)
IF %ALLOK% == 0 (
echo Please run the keygen batch file to generate the keys.
echo.
goto :end
)
IF NOT EXIST %OUT_DIR% mkdir %OUT_DIR%
:choice
cls
echo Warning: The keys used in the application will be overwritten.
set /P c=Are you sure you want to continue [Y/N]?
if /I "%c%" EQU "Y" goto :cont
if /I "%c%" EQU "N" goto :end
goto :choice
:: Copy files to persistent location, renaming them in the process
:cont
COPY /y %LOCAL_DIR%\%SRC_PRIV_NAME% %OUT_DIR%\%PRIV_NAME%
COPY /y %LOCAL_DIR%\%SRC_PUB_NAME% %OUT_DIR%\%PUB_NAME%
COPY /y %LOCAL_DIR%\%SRC_AES_NAME% %OUT_DIR%\%AES_NAME%
COPY /y %LOCAL_DIR%\%SRC_EIV_NAME% %OUT_DIR%\%EIV_NAME%
:end
pause

143
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:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
::
:: File Name: keygen.bat
::
:: Version: 1.0
::
:: Description:
:: Simple script to generate the RSA-2048 public and private keys using OpenSSL.
:: Once created, the script calls a python script to print out the public key
:: modulus that is ready to be inserted into cy_publicKey struct in
:: cy_si_keyStorage.c.
:: The script also generates a 128 bit random number to be used for the AES
:: private key and EIV.
::
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
:: Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
:: This software is owned by Cypress Semiconductor Corporation and is protected
:: by and subject to worldwide patent and copyright laws and treaties.
:: Therefore, you may use this software only as provided in the license agreement
:: accompanying the software package from which you obtained this software.
:: CYPRESS AND ITS SUPPLIERS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
:: WITH REGARD TO THIS SOFTWARE, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT,
:: IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
@echo off
set OUT_DIR="%~dp0\keys_generated"
set LOCAL_DIR=keys_generated
set PRIV_NAME=rsa_private_generated.txt
set PUB_NAME=rsa_public_generated.txt
set MOD_NAME=rsa_to_c_generated.txt
set AES_TEMP=aes_private_generated_temp.txt
set EIV_TEMP=aes_eiv_generated_temp.txt
set AES_NAME=aes_private_generated.txt
set EIV_NAME=aes_eiv_generated.txt
set AES_ARRAY=aes_private_array_generated.txt
:: Check if OpenSSL and Python are correctly installed
set ALLOK=1
CALL :testOpenSSL
CALL :testPython
IF %ALLOK% == 0 (
echo.
pause
goto :end
)
IF NOT EXIST %OUT_DIR% mkdir %OUT_DIR%
:: Delete temp files
IF EXIST %OUT_DIR%\%AES_TEMP% DEL /F %OUT_DIR%\%AES_TEMP%
IF EXIST %OUT_DIR%\%EIV_TEMP% DEL /F %OUT_DIR%\%EIV_TEMP%
:: Generate the RSA-2048 public and private keys
openssl genrsa -out %OUT_DIR%\%PRIV_NAME% 2048
openssl rsa -in %OUT_DIR%\%PRIV_NAME% -outform PEM -pubout -out %OUT_DIR%\%PUB_NAME%
:: Generate a 128bit random number
openssl rand -hex -out %OUT_DIR%\%AES_TEMP% 16
openssl rand -hex -out %OUT_DIR%\%EIV_TEMP% 16
:: Check if files exist before processing
IF NOT EXIST %LOCAL_DIR%\%AES_TEMP% (
echo Could not find OpenSSL generated files. If the error persists, check OpenSSL installation and permissions.
echo.
pause
goto :end
)
IF NOT EXIST %LOCAL_DIR%\%AES_TEMP% (
echo Could not find OpenSSL generated files. If the error persists, check OpenSSL installation and permissions.
echo.
pause
goto :end
)
IF EXIST %OUT_DIR%\%AES_NAME% DEL /F %OUT_DIR%\%AES_NAME%
IF EXIST %OUT_DIR%\%EIV_NAME% DEL /F %OUT_DIR%\%EIV_NAME%
IF EXIST %OUT_DIR%\%AES_ARRAY% DEL /F %OUT_DIR%\%AES_ARRAY%
:: Remove new line characters from AES and EIV files
FOR /F "Usebackq Tokens=*" %%@ IN ("%LOCAL_DIR%\%AES_TEMP%") DO (
<NUL Set /P "=%%@"
) >> %LOCAL_DIR%\%AES_NAME%
FOR /F "Usebackq Tokens=*" %%@ IN ("%LOCAL_DIR%\%EIV_TEMP%") DO (
<NUL Set /P "=%%@"
) >> %LOCAL_DIR%\%EIV_NAME%
:: Delete temp files
IF EXIST %OUT_DIR%\%AES_TEMP% DEL /F %OUT_DIR%\%AES_TEMP%
IF EXIST %OUT_DIR%\%EIV_TEMP% DEL /F %OUT_DIR%\%EIV_TEMP%
:: Generate a C array with the AES private key
setlocal enableDelayedExpansion
set /p str=<%LOCAL_DIR%\%AES_NAME%
set counter=1
set "out="
for /f delims^=^ eol^= %%A in ('cmd /u /v:on /c echo(^^!str^^!^|more') do (
IF "!counter!" == "1" (
set "out=!out!, 0x^%%A"
set "counter=0"
) ELSE (
set "out=!out!%%A"
set "counter=1"
)
)
set "out=!out:~2!"
echo static const uint8_t AES128_Key[16] = {!out!}; >> %OUT_DIR%\%AES_ARRAY%
:: Create C-code ready public key
%~dp0\rsa_to_c.py %OUT_DIR%\%PUB_NAME% > %OUT_DIR%\%MOD_NAME%
goto :end
:testOpenSSL
openssl version >nul 2>nul
IF ERRORLEVEL 1 CALL :errOpenSSL
EXIT /B
:testPython
python --version >nul 2>nul
IF ERRORLEVEL 1 CALL :errPython
EXIT /B
:errOpenSSL
echo.
echo OpenSSL could not be found.
echo If OpenSSL is installed, add the OpenSSL binaries directory to the system Path variable.
echo A restart may be required.
set ALLOK=0
EXIT /B
:errPython
echo.
echo Python could not be found.
echo Python is required to generate the RSA public key C array.
echo Please install Python or check that it is included in the system Path variable.
set ALLOK=0
EXIT /B
:end
pause

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/*******************************************************************************
* File Name: main_cm0p.c
*
* Version: 1.30
*
* Description: This file provides the source code for the DFU (App0)
* running on the core CM0+ (core0).
* App0 core0 firmware does the following:
* - Switches to the App1 on reset if it was scheduled.
* - Else starts App0 core1 firmware.
*
* Related Document: Code example CE216767.pdf
*
* Hardware Dependency: CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit
* CY5677 CySmart USB Dongle
*
******************************************************************************
* Copyright (2019), Cypress Semiconductor Corporation.
******************************************************************************
* This software is owned by Cypress Semiconductor Corporation (Cypress) and is
* protected by and subject to worldwide patent protection (United States and
* foreign), United States copyright laws and international treaty provisions.
* Cypress hereby grants to licensee a personal, non-exclusive, non-transferable
* license to copy, use, modify, create derivative works of, and compile the
* Cypress Source Code and derivative works for the sole purpose of creating
* custom software in support of licensee product to be used only in conjunction
* with a Cypress integrated circuit as specified in the applicable agreement.
* Any reproduction, modification, translation, compilation, or representation of
* this software except as specified above is prohibited without the express
* written permission of Cypress.
*
* Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
* REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
* Cypress reserves the right to make changes without further notice to the
* materials described herein. Cypress does not assume any liability arising out
* of the application or use of any product or circuit described herein. Cypress
* does not authorize its products for use as critical components in life-support
* systems where a malfunction or failure may reasonably be expected to result in
* significant injury to the user. The inclusion of Cypress' product in a life-
* support systems application implies that the manufacturer assumes all risk of
* such use and in doing so indemnifies Cypress against all charges. Use may be
* limited by and subject to the applicable Cypress software license agreement.
*******************************************************************************/
#include "dfu/cy_dfu.h"
#include "project.h"
#include "cy_si_config.h"
/*
* Set this define to any value different than 0, to use a standard TOC2,
* erase the public key, and enable the device to run code generated by other projects.
*/
#define UNLOCK_SYSTEM (1u)
#if CY_DFU_OPT_CRYPTO_HW != 0
#define MY_CHAN_CRYPTO (uint32_t)(3u) /* IPC data channel for the Crypto */
#define MY_INTR_CRYPTO_SRV (uint32_t)(1u) /* IPC interrupt structure for the Crypto server */
#define MY_INTR_CRYPTO_CLI (uint32_t)(2u) /* IPC interrupt structure for the Crypto client */
#define MY_INTR_CRYPTO_SRV_MUX (IRQn_Type)(2u) /* CM0+ IPC interrupt mux number the Crypto server */
#define MY_INTR_CRYPTO_CLI_MUX (IRQn_Type)(3u) /* CM0+ IPC interrupt mux number the Crypto client */
#define MY_INTR_CRYPTO_ERR_MUX (IRQn_Type)(4u) /* CM0+ ERROR interrupt mux number the Crypto server */
const cy_stc_crypto_config_t cryptoConfig =
{
/* .ipcChannel */ MY_CHAN_CRYPTO,
/* .acquireNotifierChannel */ MY_INTR_CRYPTO_SRV,
/* .releaseNotifierChannel */ MY_INTR_CRYPTO_CLI,
/* .releaseNotifierConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ MY_INTR_CRYPTO_CLI_MUX,
/* .cm0pSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */
#else
/* .intrSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */
#endif
/* .intrPriority */ 2u,
},
/* .userCompleteCallback */ NULL,
/* .userGetDataHandler */ NULL,
/* .userErrorHandler */ NULL,
/* .acquireNotifierConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ MY_INTR_CRYPTO_SRV_MUX, /* to use with DeepSleep mode should be in DeepSleep capable muxer's range */
/* .cm0pSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */
#else
/* .intrSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */
#endif
/* .intrPriority */ 2u,
},
/* .cryptoErrorIntrConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ MY_INTR_CRYPTO_ERR_MUX,
/* .cm0pSrc */ cpuss_interrupt_crypto_IRQn,
#else
/* .intrSrc */ cpuss_interrupt_crypto_IRQn,
#endif
/* .intrPriority */ 2u,
}
};
cy_stc_crypto_server_context_t cryptoServerContext;
cy_en_crypto_status_t cryptoStatus;
#endif
#if UNLOCK_SYSTEM == (0u)
/* Flashboot parameters */
#define CY_SI_FLASHBOOT_FLAGS ((CY_SI_FLASHBOOT_VALIDATE_YES << CY_SI_TOC_FLAGS_APP_VERIFY_POS) \
| (CY_SI_FLASHBOOT_WAIT_20MS << CY_SI_TOC_FLAGS_DELAY_POS) \
| (CY_SI_FLASHBOOT_CLK_25MHZ << CY_SI_TOC_FLAGS_CLOCKS_POS))
/* TOC Part 2 Definition */
CY_SECTION(".cy_toc_part2") __USED
const cy_stc_si_toc_t cy_toc2 =
{
.objSize = sizeof(cy_stc_si_toc_t) - sizeof(uint32_t), /**< Object Size (Bytes) excluding CRC */
.magicNum = CY_SI_TOC2_MAGICNUMBER, /**< TOC2 ID (magic number) */
.userKeyAddr = (uint32_t) &CySecureKeyStorage, /**< User key storage address */
.smifCfgAddr = 0UL, /**< SMIF config list pointer */
.appAddr1 = CY_DFU_APP0_VERIFY_START, /**< App0 start address */
.appFormat1 = CY_DFU_CYPRESS_APP, /**< App0 Format */
.shashObj = 1UL, /**< Include public key in the SECURE HASH */
.sigKeyAddr = (uint32_t)&SFLASH->PUBLIC_KEY, /**< Address of signature verification key */
.tocFlags = CY_SI_FLASHBOOT_FLAGS, /**< Flashboot flags stored in TOC2 */
.crc = 0UL, /**< CRC populated by cymcuelftool */
};
/* Assuming App0 is located at start of flash, change define if different */
#define APP0_START_ADDRESS CY_FLASH_BASE
/* Cypress Standard Application Format Header */
CY_SECTION(".cy_app_header") __USED
const cy_stc_user_appheader_t applicationHeader =
{
.objSize = CY_DFU_APP0_VERIFY_LENGTH, /* Application Size (Bytes) excluding hash */
.appId = CY_SI_APP_VERSION, /* App ID */
.appAttributes = 0UL, /* Reserved */
.numCores = 2UL, /* CM0+ and CM4 */
.core0Vt = (uint32_t)(&__Vectors[0]) - APP0_START_ADDRESS - offsetof(cy_stc_user_appheader_t, core0Vt), /* Offset to CM0+ Vector Table in flash */
.core1Vt = (uint32_t)(&__cy_app_core1_start_addr) - APP0_START_ADDRESS - offsetof(cy_stc_user_appheader_t, core1Vt), /* Offset to CM4 Vector Table in flash */
.core0Id = CY_ARM_CM0P_CPUID, /* ARM CM0+ CPU ID */
.core1Id = CY_ARM_CM4_CPUID, /* ARM CM4 CPU ID */
};
#endif /* UNLOCK_SYSTEM == (0u) */
#if UNLOCK_SYSTEM != (0u)
/* Flashboot parameters */
#define CY_SI_FLASHBOOT_FLAGS ((CY_SI_FLASHBOOT_VALIDATE_NO << CY_SI_TOC_FLAGS_APP_VERIFY_POS) \
| (CY_SI_FLASHBOOT_WAIT_20MS << CY_SI_TOC_FLAGS_DELAY_POS) \
| (CY_SI_FLASHBOOT_CLK_25MHZ << CY_SI_TOC_FLAGS_CLOCKS_POS))
/* Standard TOC Part 2 Definition */
CY_SECTION(".cy_toc_part2") __USED
const cy_stc_si_toc_t cy_toc2 =
{
.objSize = sizeof(cy_stc_si_toc_t) - sizeof(uint32_t), /**< Object Size (Bytes) excluding CRC */
.magicNum = CY_SI_TOC2_MAGICNUMBER, /**< TOC2 ID (magic number) */
.userKeyAddr = 0UL, /**< User key storage address */
.smifCfgAddr = 0UL, /**< SMIF config list pointer */
.appAddr1 = CY_FLASH_BASE, /**< Main Flash base address */
.appFormat1 = CY_DFU_BASIC_APP, /**< Basic format */
.shashObj = 0UL,
.sigKeyAddr = 0UL, /**< Address of signature verification key */
.tocFlags = CY_SI_FLASHBOOT_FLAGS, /**< Flashboot flags stored in TOC2 */
.crc = 0UL, /**< CRC populated by cymcuelftool */
};
#endif /* UNLOCK_SYSTEM != 0UL */
/*******************************************************************************
* Function Name: main
********************************************************************************
*
* Summary:
* Main function of App0 core0. Unfreezes IO and sets up the user button (SW2)
* as the hibernate wakeup source. Afterwards initializes core1 (CM4) and goes
* into deep sleep.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
int main(void)
{
/* Unfreeze IO after Hibernate */
if(Cy_SysPm_GetIoFreezeStatus())
{
Cy_SysPm_IoUnfreeze();
}
/* Set SW2 as hibernate wakeup pin */
Cy_SysPm_SetHibWakeupSource(CY_SYSPM_HIBPIN1_LOW);
/* enable global interrupts */
__enable_irq();
#if CY_DFU_OPT_CRYPTO_HW != 0
/* Start the Crypto Server */
Cy_Crypto_Server_Start(&cryptoConfig, &cryptoServerContext);
#endif
/* Enable CM4 with the CM4 start address defined in the
DFU SDK linker script */
Cy_SysEnableCM4( (uint32_t)(&__cy_app_core1_start_addr) );
for (;;)
{
/* Process crypto server requests */
Cy_Crypto_Server_Process();
//Go into Deep Sleep
Cy_SysPm_DeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
}
}
/*******************************************************************************
* Function Name: Cy_OnResetUser
********************************************************************************
*
* Summary:
* This function is called at the start of Reset_Handler(). It is a weak function
* that may be redefined by user code.
* DFU SDK requires it to call Cy_DFU_OnResetApp0().
* Checks if an App switch has been scheduled and transfers control to it.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Cy_OnResetUser(void)
{
Cy_DFU_OnResetApp0();
}
/* [] END OF FILE */

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/*******************************************************************************
* File Name: main_cm4.c
*
* Version: 1.30
*
* Description: This file provides the source code for the DFU (App0)
* running on the core CM4 (core1).
* App0 core1 firmware does the following:
* - Downloads App1 firmware image
* - Switches to App1 if App1 image has successfully downloaded
* and is valid
* - Switches to existing App1 if button is pressed
* - Turn on an LED depending on status
* - Hibernates on timeout
*******************************************************************************
* Related Document: CE216767.pdf
*
* Hardware Dependency: CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit
* CY5677 CySmart USB Dongle
*
******************************************************************************
* Copyright (2019), Cypress Semiconductor Corporation.
******************************************************************************
* This software is owned by Cypress Semiconductor Corporation (Cypress) and is
* protected by and subject to worldwide patent protection (United States and
* foreign), United States copyright laws and international treaty provisions.
* Cypress hereby grants to licensee a personal, non-exclusive, non-transferable
* license to copy, use, modify, create derivative works of, and compile the
* Cypress Source Code and derivative works for the sole purpose of creating
* custom software in support of licensee product to be used only in conjunction
* with a Cypress integrated circuit as specified in the applicable agreement.
* Any reproduction, modification, translation, compilation, or representation of
* this software except as specified above is prohibited without the express
* written permission of Cypress.
*
* Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
* REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
* Cypress reserves the right to make changes without further notice to the
* materials described herein. Cypress does not assume any liability arising out
* of the application or use of any product or circuit described herein. Cypress
* does not authorize its products for use as critical components in life-support
* systems where a malfunction or failure may reasonably be expected to result in
* significant injury to the user. The inclusion of Cypress' product in a life-
* support systems application implies that the manufacturer assumes all risk of
* such use and in doing so indemnifies Cypress against all charges. Use may be
* limited by and subject to the applicable Cypress software license agreement.
*******************************************************************************/
#include <string.h>
#include "project.h"
#include "debug.h"
#include "ias.h"
#include "transport_ble.h"
#if CY_DFU_OPT_CRYPTO_HW != 0
#define MY_CHAN_CRYPTO (uint32_t)(3u) /* IPC data channel for the Crypto */
#define MY_INTR_CRYPTO_SRV (uint32_t)(1u) /* IPC interrupt structure for the Crypto server */
#define MY_INTR_CRYPTO_CLI (uint32_t)(2u) /* IPC interrupt structure for the Crypto client */
#define MY_INTR_CRYPTO_SRV_MUX (IRQn_Type)(2u) /* CM0+ IPC interrupt mux number the Crypto server */
#define MY_INTR_CRYPTO_CLI_MUX (IRQn_Type)(3u) /* CM0+ IPC interrupt mux number the Crypto client */
#define MY_INTR_CRYPTO_ERR_MUX (IRQn_Type)(4u) /* CM0+ ERROR interrupt mux number the Crypto server */
const cy_stc_crypto_config_t cryptoConfig =
{
/* .ipcChannel */ MY_CHAN_CRYPTO,
/* .acquireNotifierChannel */ MY_INTR_CRYPTO_SRV,
/* .releaseNotifierChannel */ MY_INTR_CRYPTO_CLI,
/* .releaseNotifierConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ MY_INTR_CRYPTO_CLI_MUX,
/* .cm0pSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */
#else
/* .intrSrc */ cpuss_interrupts_ipc_2_IRQn, /* depends on selected releaseNotifierChannel value */
#endif
/* .intrPriority */ 2u,
},
/* .userCompleteCallback */ NULL,
/* .userGetDataHandler */ NULL,
/* .userErrorHandler */ NULL,
/* .acquireNotifierConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ MY_INTR_CRYPTO_SRV_MUX, /* to use with DeepSleep mode should be in DeepSleep capable muxer's range */
/* .cm0pSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */
#else
/* .intrSrc */ cpuss_interrupts_ipc_1_IRQn, /* depends on selected acquireNotifierChannel value */
#endif
/* .intrPriority */ 2u,
},
/* .cryptoErrorIntrConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ MY_INTR_CRYPTO_ERR_MUX,
/* .cm0pSrc */ cpuss_interrupt_crypto_IRQn,
#else
/* .intrSrc */ cpuss_interrupt_crypto_IRQn,
#endif
/* .intrPriority */ 2u,
}
};
cy_stc_crypto_context_t cryptoContext;
cy_en_crypto_status_t cryptoStatus;
#endif
/* BLE GAPP Connection Settings */
#define CYBLE_GAPP_CONNECTION_INTERVAL_MIN (0x000Cu) /* 15 ms - (N * 1,25)*/
#define CYBLE_GAPP_CONNECTION_INTERVAL_MAX (0x000Cu) /* 15 ms */
#define CYBLE_GAPP_CONNECTION_SLAVE_LATENCY (0x0000u)
#define CYBLE_GAPP_CONNECTION_TIME_OUT (0x00C8u) /* 2000 ms */
/* BLE Callback function, defined in this file */
void AppCallBack(uint32 event, void* eventParam);
/* Local functions */
static cy_en_dfu_status_t CopyRow(uint32_t dest, uint32_t src, uint32_t rowSize, cy_stc_dfu_params_t * params);
static cy_en_dfu_status_t HandleMetadata(cy_stc_dfu_params_t *params);
static bool IsButtonPressed(uint16_t timeoutInMilis);
static uint32_t counterTimeoutSeconds(uint32_t seconds, uint32_t timeout);
/* This section is used to verify an application signature
For sha256 verification, set the number of elements in the array to 64, and
in bootload_common.ld set __cy_boot_signature_size = 256.
*/
CY_SECTION(".cy_app_signature") __USED static const uint32_t cy_bootload_appSignature[64];
/*******************************************************************************
* Function Name: main
********************************************************************************
*
* Summary:
* Main function of the DFU application (App0).
* 1. If application started from non-software reset it validates App1
* 1.1. If App1 is valid it switches to App1, else goto #2.
* 2. Start DFU communication.
* 3. If updated application has been received it validates this app.
* 4. If App1 is valid it switches to it, else wait for new application.
* 5. If 300 seconds have passed and no new application has been received
* then validate App1, if it is valid then switch to it, else hibernate
* (Happens in the BLE AppCallBack).
*
*******************************************************************************/
int main(void)
{
/* timeout for Cy_DFU_Continue(), in milliseconds */
const uint32_t paramsTimeout = 20u;
/* used to configure DFU */
static cy_stc_dfu_params_t dfuParams;
/* Status codes from DFU SDK API */
cy_en_dfu_status_t status;
/* SW2 released after deciding to stay in App0 */
bool buttonReleased = false;
/*
* DFU state, one of
* - CY_DFU_STATE_NONE
* - CY_DFU_STATE_UPDATING
* - CY_DFU_STATE_FINISHED
* - CY_DFU_STATE_FAILED
*/
uint32_t state = CY_DFU_STATE_NONE;
cy_en_ble_api_result_t apiResult;
cy_stc_ble_stack_lib_version_t stackVersion;
/*
* Used to count seconds, to convert counts to seconds use
* counterTimeoutSeconds(SECONDS, paramsTimeout)
*/
uint32_t count = 0;
uint32_t ledTimer = 0;
#if CY_DFU_OPT_CRYPTO_HW != 0
cy_en_crypto_status_t cryptoStatus;
#endif
/* Buffer to store DFU commands */
CY_ALIGN(4) static uint8_t buffer[CY_DFU_SIZEOF_DATA_BUFFER];
/* Buffer for DFU packets for Transport API */
CY_ALIGN(4) static uint8_t packet[CY_DFU_SIZEOF_CMD_BUFFER];
/* Enable global interrupts */
__enable_irq();
/* Start UART Services */
UART_START();
/* Initializes LEDs */
InitLED();
#if CY_DFU_OPT_CRYPTO_HW != 0
/* Initialize the Crypto Client code */
cryptoStatus = Cy_Crypto_Init(&cryptoConfig, &cryptoContext);
if (cryptoStatus != CY_CRYPTO_SUCCESS)
{
/* Crypto not initialized; debug what is the problem */
Cy_SysLib_Halt(0x00u);
}
cryptoStatus = Cy_Crypto_Enable();
if (cryptoStatus != CY_CRYPTO_SUCCESS)
{
/* Crypto not enabled; debug what is the problem */
Cy_SysLib_Halt(0x00u);
}
#endif /* CY_DFU_OPT_CRYPTO_HW != 0 */
/* Initialize dfuParams structure and DFU SDK state */
dfuParams.timeout = paramsTimeout;
dfuParams.dataBuffer = &buffer[0];
dfuParams.packetBuffer = &packet[0];
status = Cy_DFU_Init(&state, &dfuParams);
/* Ensure DFU Metadata is valid */
status = HandleMetadata(&dfuParams);
if (status != CY_DFU_SUCCESS)
{
Cy_SysLib_Halt(0x00u);
}
/*
* In the case of non-software reset and user does not
* want to stay in App0, check if there is a valid app image.
* If there is - switch to it.
*/
if ((Cy_SysLib_GetResetReason() != CY_SYSLIB_RESET_SOFT) && (IsButtonPressed(2000u) == false))
{
status = Cy_DFU_ValidateApp(1u, &dfuParams);
if (status == CY_DFU_SUCCESS)
{
/*
* Clear reset reason because Cy_DFU_ExecuteApp() performs
* a software reset.
* Without clearing two reset reasons would be present.
*/
do
{
Cy_SysLib_ClearResetReason();
}while(Cy_SysLib_GetResetReason() != 0);
/* Never returns */
Cy_DFU_ExecuteApp(1u);
}
}
/* Initialize DFU communication */
Cy_DFU_TransportStart();
/* Initializes the Immediate Alert Service */
IasInit();
/* Output current stack version to UART */
apiResult = Cy_BLE_GetStackLibraryVersion(&stackVersion);
if(apiResult != CY_BLE_SUCCESS)
{
DBG_PRINTF("CyBle_GetStackLibraryVersion API Error: 0x%2.2x \r\n", apiResult);
}
else
{
DBG_PRINTF("Stack Version: %d.%d.%d.%d \r\n", stackVersion.majorVersion,
stackVersion.minorVersion, stackVersion.patch, stackVersion.buildNumber);
}
for(;;)
{
/* CyBle_ProcessEvents() allows BLE stack to process pending events */
Cy_BLE_ProcessEvents();
/* Process DFU commands */
status = Cy_DFU_Continue(&state, &dfuParams);
++count;
switch(state)
{
case CY_DFU_STATE_FINISHED:
/* Finished downloading the application image */
/* Validate downloaded application, if it is valid then switch to it */
status = Cy_DFU_ValidateApp(1u, &dfuParams);
if (status == CY_DFU_SUCCESS)
{
Cy_DFU_TransportStop();
/*
* Clear reset reason because Cy_DFU_ExecuteApp() performs
* a software reset.
* Without clearing two reset reasons would be present.
*/
do
{
Cy_SysLib_ClearResetReason();
}while(Cy_SysLib_GetResetReason() != 0);
/* Never returns */
Cy_DFU_ExecuteApp(1u);
}
else if (status == CY_DFU_ERROR_VERIFY)
{
/*
* Restarts DFU, alternatives are to Halt MCU here
* or switch to the other app if it is valid.
* Error code may be handled here, i.e. print to debug UART.
*/
status = Cy_DFU_Init(&state, &dfuParams);
/* Reset LED */
ConnectedLED();
ledTimer = 0;
Cy_DFU_TransportReset();
}
break;
case CY_DFU_STATE_FAILED:
/* Handle error here */
DBG_PRINTF("Downloading has failed with error code 0x%x, try again\r\n", status);
/* In this Code Example just restart DFU process */
status = Cy_DFU_Init(&state, &dfuParams);
/* Reset LED */
ConnectedLED();
ledTimer = 0;
Cy_DFU_TransportReset();
break;
case CY_DFU_STATE_UPDATING:
/* Reset timeout counter, if a command was correctly received */
if (status == CY_DFU_SUCCESS)
{
count = 0u;
}
else if (status == CY_DFU_ERROR_TIMEOUT)
{
/*
* if no command has been received during 5 seconds when DFU
* has started then restart DFU.
*/
if (count >= counterTimeoutSeconds(5u, paramsTimeout))
{
count = 0u;
Cy_DFU_Init(&state, &dfuParams);
/* Reset LED */
ConnectedLED();
ledTimer = 0;
Cy_DFU_TransportReset();
}
}
else
{
count = 0u;
/* Delay because Transport still may be sending error response to a host */
Cy_SysLib_Delay(paramsTimeout);
Cy_DFU_Init(&state, &dfuParams);
Cy_DFU_TransportReset();
}
break;
}
/* LED logic, constant values are optimized out. */
/* Reset timer after 2 seconds */
if(ledTimer == (2000u / paramsTimeout)) ledTimer = 0;
/* Every 100 miliseconds */
if(!(ledTimer % (100u / paramsTimeout)))
{
/* Generates two 100 miliseconds pulses, every 2 seconds */
if((state == CY_DFU_STATE_UPDATING) && (ledTimer < (400u / paramsTimeout)))
{
BlinkLED();
}
/* Generates one 100 miliseconds pulse, every 2 seconds */
else if ((Cy_BLE_GetAdvertisementState() == CY_BLE_ADV_STATE_ADVERTISING)
&& (ledTimer < (200u / paramsTimeout)))
{
BlinkLED();
}
else
{
/* Remain OFF */
ConnectedLED();
}
}
++ledTimer;
/* Check if a switch to the other app is requested and perform the switch if it is */
if((buttonReleased == true) && (state == CY_DFU_STATE_NONE))
{
bool switchRequested = false;
if (alertLevel != 0)
{
switchRequested = true;
}
else if(IsButtonPressed(500u) == true)
{
switchRequested = true;
buttonReleased = false;
}
if (switchRequested)
{
/* Validate and switch to App1 */
cy_en_dfu_status_t status = Cy_DFU_ValidateApp(1u, &dfuParams);
if (status == CY_DFU_SUCCESS)
{
Cy_DFU_TransportStop();
/*
* Clear reset reason because Cy_DFU_ExecuteApp() performs
* a software reset.
* Without clearing two reset reasons would be present.
*/
do
{
Cy_SysLib_ClearResetReason();
}while(Cy_SysLib_GetResetReason() != 0);
/* Never returns */
Cy_DFU_ExecuteApp(1u);
}
}
}
else
{
buttonReleased = Cy_GPIO_Read(PIN_SW2_PORT, PIN_SW2_NUM);
}
}
}
/*******************************************************************************
* Function Name: IsButtonPressed
********************************************************************************
* Checks if button is pressed for a 'timeoutInMilis' time.
*
* Params:
* timeout: Amount of time to check if button was pressed. Broken into
* 20 miliseconds steps.
* Returns:
* true if button is pressed for specified amount.
* false otherwise.
*******************************************************************************/
static bool IsButtonPressed(uint16_t timeoutInMilis)
{
uint16_t buttonTime = 0;
bool buttonPressed = false;
timeoutInMilis /= 20;
while(Cy_GPIO_Read(PIN_SW2_PORT, PIN_SW2_NUM) == 0u)
{
Cy_SysLib_Delay(20u);
if(++buttonTime == timeoutInMilis)
{
/* time has passed */
buttonPressed = true;
break;
}
}
return buttonPressed;
}
/*******************************************************************************
* Function Name: counterTimeoutSeconds
********************************************************************************
* Returns number of counts that correspond to number of seconds passed as
* a parameter.
* E.g. comparing counter with 300 seconds is like this.
* ---
* uint32_t counter = 0u;
* for (;;)
* {
* Cy_SysLib_Delay(UART_TIMEOUT);
* ++count;
* if (count >= counterTimeoutSeconds(seconds: 300u, timeout: UART_TIMEOUT))
* {
* count = 0u;
* DoSomething();
* }
* }
* ---
*
* Both parameters are required to be compile time constants,
* so this function gets optimized out to single constant value.
*
* Parameters:
* seconds Number of seconds to pass. Must be less that 4_294_967 seconds.
* timeout Timeout for Cy_DFU_Continue() function, in milliseconds.
* Must be greater than zero.
* It is recommended to be a value that produces no reminder
* for this function to be precise.
* Return:
* See description.
*******************************************************************************/
static uint32_t counterTimeoutSeconds(uint32_t seconds, uint32_t timeout)
{
return (seconds * 1000ul) / timeout;
}
/*******************************************************************************
* Function Name: CopyRow
********************************************************************************
* Copies data from a "src" address to a flash row with the address "dest".
* If "src" data is the same as "dest" data then no copy is needed.
*
* Parameters:
* dest Destination address. Has to be an address of the start of flash row.
* src Source address. Has to be properly aligned.
* rowSize Size of flash row.
*
* Returns:
* CY_DFU_SUCCESS if operation is successful.
* Error code in a case of failure.
*******************************************************************************/
static cy_en_dfu_status_t CopyRow(uint32_t dest, uint32_t src, uint32_t rowSize, cy_stc_dfu_params_t * params)
{
cy_en_dfu_status_t status;
/* Save params->dataBuffer value */
uint8_t *buffer = params->dataBuffer;
/* Compare "dest" and "src" content */
params->dataBuffer = (uint8_t *)src;
status = Cy_DFU_ReadData(dest, rowSize, CY_DFU_IOCTL_COMPARE, params);
/* Restore params->dataBuffer */
params->dataBuffer = buffer;
/* If "dest" differs from "src" then copy "src" to "dest" */
if (status != CY_DFU_SUCCESS)
{
(void) memcpy((void *) params->dataBuffer, (const void*)src, rowSize);
status = Cy_DFU_WriteData(dest, rowSize, CY_DFU_IOCTL_WRITE, params);
}
/* Restore params->dataBuffer */
params->dataBuffer = buffer;
return (status);
}
/*******************************************************************************
* Function Name: HandleMetadata
********************************************************************************
* The goal of this function is to make DFU SDK metadata (MD) valid.
* The following algorithm is used (in C-like pseudocode):
* ---
* if (isValid(MD) == true)
* { if (MDC != MD)
* MDC = MD;
* } else
* { if(isValid(MDC) )
* MD = MDC;
* #if MD Writeable
* else
* MD = INITIAL_VALUE;
* #endif
* }
* ---
* Here MD is metadata flash row, MDC is flash row with metadata copy,
* INITIAL_VALUE is known initial value.
*
* In this code example MDC is placed in the next flash row after the MD, and
* INITIAL_VALUE is MD with only CRC, App0 start and size initialized,
* all the other fields are not touched. This is only done if metadata is
* writeable when downloading.
*
* Parameters:
* params A pointer to a DFU SDK parameters structure.
*
* Returns:
* - CY_DFU_SUCCESS when finished normally.
* - Any other status code on error.
*******************************************************************************/
static cy_en_dfu_status_t HandleMetadata(cy_stc_dfu_params_t *params)
{
const uint32_t MD = (uint32_t)(&__cy_boot_metadata_addr ); /* MD address */
const uint32_t mdSize = (uint32_t)(&__cy_boot_metadata_length ); /* MD size, assumed to be one flash row */
const uint32_t MDC = MD + mdSize; /* MDC address */
cy_en_dfu_status_t status = CY_DFU_SUCCESS;
status = Cy_DFU_ValidateMetadata(MD, params);
if (status == CY_DFU_SUCCESS)
{
/* Checks if MDC equals to DC, if no then copies MD to MDC */
status = CopyRow(MDC, MD, mdSize, params);
}
else
{
status = Cy_DFU_ValidateMetadata(MDC, params);
if (status == CY_DFU_SUCCESS)
{
/* Copy MDC to MD */
status = CopyRow(MD, MDC, mdSize, params);
}
#if CY_DFU_METADATA_WRITABLE != 0
if (status != CY_DFU_SUCCESS)
{
const uint32_t elfStartAddress = 0x10000000;
const uint32_t elfAppSize = 0x40000;
/* Set MD to INITIAL_VALUE */
status = Cy_DFU_SetAppMetadata(0u, elfStartAddress, elfAppSize, params);
}
#endif /* CY_DFU_METADATA_WRITABLE != 0 */
}
return (status);
}
/*******************************************************************************
* Function Name: AppCallBack()
********************************************************************************
*
* Summary:
* This is an event callback function to receive events from the BLE Component.
* Used in Cy_DFU_TransportStart()
*
* event - the event code
* *eventParam - the event parameters
*
*******************************************************************************/
void AppCallBack(uint32 event, void* eventParam)
{
cy_en_ble_api_result_t apiResult;
static cy_stc_ble_gap_sec_key_info_t keyInfo =
{
.localKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST |
CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST |
CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST,
.exchangeKeysFlag = CY_BLE_GAP_SMP_INIT_ENC_KEY_DIST |
CY_BLE_GAP_SMP_INIT_IRK_KEY_DIST |
CY_BLE_GAP_SMP_INIT_CSRK_KEY_DIST |
CY_BLE_GAP_SMP_RESP_ENC_KEY_DIST |
CY_BLE_GAP_SMP_RESP_IRK_KEY_DIST |
CY_BLE_GAP_SMP_RESP_CSRK_KEY_DIST,
};
switch (event)
{
/**********************************************************
* General Events
***********************************************************/
/* This event received when BLE communication starts */
case CY_BLE_EVT_STACK_ON:
/* Enter into discoverable mode so that remote can search it. */
apiResult = Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, 0u);
if(apiResult != CY_BLE_SUCCESS)
{
}
apiResult = Cy_BLE_GAP_GenerateKeys(&keyInfo);
if(apiResult != CY_BLE_SUCCESS)
{
DBG_PRINTF("CyBle_GapGenerateKeys API Error: %d \r\n", apiResult);
}
break;
/* This event indicates that some internal HW error has occurred. */
case CY_BLE_EVT_HARDWARE_ERROR:
DBG_PRINTF("CYBLE_EVT_HARDWARE_ERROR\r\n");
break;
/**********************************************************
* GAP Events
***********************************************************/
case CY_BLE_EVT_GAP_AUTH_REQ:
DBG_PRINTF("CYBLE_EVT_AUTH_REQ: security=%x, bonding=%x, ekeySize=%x, err=%x \r\n",
(*(cy_stc_ble_gap_auth_info_t *)eventParam).security,
(*(cy_stc_ble_gap_auth_info_t *)eventParam).bonding,
(*(cy_stc_ble_gap_auth_info_t*)eventParam).ekeySize,
(*(cy_stc_ble_gap_auth_info_t *)eventParam).authErr );
if ( cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].security
== (CY_BLE_GAP_SEC_MODE_1 | CY_BLE_GAP_SEC_LEVEL_1) )
{
cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].authErr =
CY_BLE_GAP_AUTH_ERROR_PAIRING_NOT_SUPPORTED;
}
cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX].bdHandle =
((cy_stc_ble_gap_auth_info_t *)eventParam)->bdHandle;
apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]);
if(apiResult != CY_BLE_SUCCESS)
{
Cy_BLE_GAP_RemoveOldestDeviceFromBondedList();
apiResult = Cy_BLE_GAPP_AuthReqReply(&cy_ble_configPtr->authInfo[CY_BLE_SECURITY_CONFIGURATION_0_INDEX]);
if(apiResult != CY_BLE_SUCCESS)
{
DBG_PRINTF("CyBle_GappAuthReqReply API Error: %d \r\n", apiResult);
}
}
break;
case CY_BLE_EVT_GAP_PASSKEY_ENTRY_REQUEST:
DBG_PRINTF("CYBLE_EVT_PASSKEY_ENTRY_REQUEST press 'p' to enter passkey \r\n");
break;
case CY_BLE_EVT_GAP_PASSKEY_DISPLAY_REQUEST:
DBG_PRINTF("CYBLE_EVT_PASSKEY_DISPLAY_REQUEST %6.6d \r\n", *(int *)eventParam);
break;
case CY_BLE_EVT_GAP_KEYINFO_EXCHNGE_CMPLT:
DBG_PRINTF("CYBLE_EVT_GAP_KEYINFO_EXCHNGE_CMPLT \r\n");
break;
case CY_BLE_EVT_GAP_AUTH_COMPLETE:
DBG_PRINTF("AUTH_COMPLETE \r\n");
break;
case CY_BLE_EVT_GAP_AUTH_FAILED:
DBG_PRINTF("CYBLE_EVT_AUTH_FAILED: %x \r\n", *(uint8 *)eventParam);
break;
case CY_BLE_EVT_GAP_DEVICE_CONNECTED:
DBG_PRINTF("CYBLE_EVT_GAP_DEVICE_CONNECTED: %d \r\n", appConnHandle.bdHandle);
if ( ((*(cy_stc_ble_gap_connected_param_t *)eventParam).connIntv
< CYBLE_GAPP_CONNECTION_INTERVAL_MIN ) || (
(*(cy_stc_ble_gap_connected_param_t *)eventParam).connIntv
> CYBLE_GAPP_CONNECTION_INTERVAL_MAX ) )
{
cy_stc_ble_gap_conn_update_param_info_t connUpdateParam;
/* If connection settings do not match expected ones - request parameter update */
connUpdateParam.connIntvMin = CYBLE_GAPP_CONNECTION_INTERVAL_MIN;
connUpdateParam.connIntvMax = CYBLE_GAPP_CONNECTION_INTERVAL_MAX;
connUpdateParam.connLatency = CYBLE_GAPP_CONNECTION_SLAVE_LATENCY;
connUpdateParam.supervisionTO = CYBLE_GAPP_CONNECTION_TIME_OUT;
connUpdateParam.bdHandle = appConnHandle.bdHandle;
apiResult = Cy_BLE_L2CAP_LeConnectionParamUpdateRequest(&connUpdateParam);
DBG_PRINTF("Cy_BLE_L2CAP_LeConnectionParamUpdateRequest API: 0x%2.2x \r\n", apiResult);
}
keyInfo.SecKeyParam.bdHandle = (*(cy_stc_ble_gap_connected_param_t *)eventParam).bdHandle;
apiResult = Cy_BLE_GAP_SetSecurityKeys(&keyInfo);
if(apiResult != CY_BLE_SUCCESS)
{
DBG_PRINTF("CyBle_GapSetSecurityKeys API Error: %d \r\n", apiResult);
}
break;
case CY_BLE_EVT_L2CAP_CONN_PARAM_UPDATE_RSP:
DBG_PRINTF("CY_BLE_EVT_L2CAP_CONN_PARAM_UPDATE_RSP, result = %d\r\n",
(*(cy_stc_ble_l2cap_conn_update_rsp_param_t *)eventParam).result);
break;
case CY_BLE_EVT_GAP_KEYS_GEN_COMPLETE:
DBG_PRINTF("CYBLE_EVT_GAP_KEYS_GEN_COMPLETE \r\n");
keyInfo.SecKeyParam = (*(cy_stc_ble_gap_sec_key_param_t *)eventParam);
Cy_BLE_GAP_SetIdAddress(&cy_ble_deviceAddress);
break;
case CY_BLE_EVT_GAP_DEVICE_DISCONNECTED:
DBG_PRINTF("CYBLE_EVT_GAP_DEVICE_DISCONNECTED\r\n");
/* Put the device into discoverable mode so that a remote can search it. */
apiResult = Cy_BLE_GAPP_StartAdvertisement(CY_BLE_ADVERTISING_FAST, CY_BLE_PERIPHERAL_CONFIGURATION_0_INDEX);
if(apiResult != CY_BLE_SUCCESS)
{
DBG_PRINTF("StartAdvertisement API Error: %d \r\n", apiResult);
}
break;
case CY_BLE_EVT_GAP_ENCRYPT_CHANGE:
DBG_PRINTF("CYBLE_EVT_GAP_ENCRYPT_CHANGE: %x \r\n", *(uint8 *)eventParam);
break;
case CY_BLE_EVT_GAP_CONNECTION_UPDATE_COMPLETE:
DBG_PRINTF("CYBLE_EVT_CONNECTION_UPDATE_COMPLETE: %x \r\n", *(uint8 *)eventParam);
break;
case CY_BLE_EVT_GAPP_ADVERTISEMENT_START_STOP:
if(Cy_BLE_GetAdvertisementState() == CY_BLE_ADV_STATE_STOPPED)
{
/* Fast and slow advertising period complete, go to low power
* mode (Hibernate mode) and wait for an external
* user event to wake up the device again */
/* Stop DFU communication */
Cy_DFU_TransportStop();
/* Check if app is valid, if it is then switch to it */
uint32_t status = Cy_DFU_ValidateApp(1u, NULL);
if (status == CY_DFU_SUCCESS)
{
/*
* Clear reset reason because Cy_DFU_ExecuteApp() performs
* a software reset.
* Without clearing two reset reasons would be present.
*/
do
{
Cy_SysLib_ClearResetReason();
}while(Cy_SysLib_GetResetReason() != 0);
/* Never returns */
Cy_DFU_ExecuteApp(1u);
}
/* 300 seconds has passed and App is invalid. Hibernate */
HibernateLED();
Cy_SysPm_Hibernate();
}
break;
/**********************************************************
* GATT Events
***********************************************************/
case CY_BLE_EVT_GATT_CONNECT_IND:
appConnHandle = *(cy_stc_ble_conn_handle_t *)eventParam;
DBG_PRINTF("CYBLE_EVT_GATT_CONNECT_IND: %d \r\n", appConnHandle.bdHandle);
break;
case CY_BLE_EVT_GATT_DISCONNECT_IND:
DBG_PRINTF("CYBLE_EVT_GATT_DISCONNECT_IND: %d \r\n", ((cy_stc_ble_conn_handle_t *)eventParam)->bdHandle);
break;
case CY_BLE_EVT_GATTS_WRITE_CMD_REQ:
DBG_PRINTF("CYBLE_EVT_GATTS_WRITE_CMD_REQ\r\n");
break;
default:
break;
}
}
/* [] END OF FILE */

321
2020TPCApp0.cydsn/mdk/startup_psoc6_01_cm0plus.s Normal file
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@ -0,0 +1,321 @@
;/**************************************************************************//**
; * @file startup_psoc6_01_cm0plus.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM0plus Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00001000
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External interrupts Description
DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10
DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11
DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12
DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13
DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14
DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15
DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16
DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17
DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18
DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19
DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20
DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21
DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22
DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23
DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24
DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25
DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26
DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27
DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28
DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29
DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30
DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
EXPORT __ramVectors
AREA RESET_RAM, READWRITE, NOINIT
__ramVectors SPACE __Vectors_Size
AREA |.text|, CODE, READONLY
; Weak function for startup customization
;
; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
; because this function is executed as the first instruction in the ResetHandler.
; The PDL is also not initialized to use the proper register offsets.
; The user of this function is responsible for initializing the PDL and resources before using them.
;
Cy_OnResetUser PROC
EXPORT Cy_OnResetUser [WEAK]
BX LR
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
; Define strong function for startup customization
BL Cy_OnResetUser
; Disable global interrupts
CPSID I
; Copy vectors from ROM to RAM
LDR r1, =__Vectors
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
Vectors_Copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE Vectors_Copy
; Update Vector Table Offset Register. */
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb 0xF
LDR R0, =__main
BLX R0
; Should never get here
B .
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
Cy_SysLib_FaultHandler PROC
EXPORT Cy_SysLib_FaultHandler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
bl L_API_call
L_MSP
mrs r0, MSP
L_API_call
bl Cy_SysLib_FaultHandler
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT Default_Handler [WEAK]
EXPORT NvicMux0_IRQHandler [WEAK]
EXPORT NvicMux1_IRQHandler [WEAK]
EXPORT NvicMux2_IRQHandler [WEAK]
EXPORT NvicMux3_IRQHandler [WEAK]
EXPORT NvicMux4_IRQHandler [WEAK]
EXPORT NvicMux5_IRQHandler [WEAK]
EXPORT NvicMux6_IRQHandler [WEAK]
EXPORT NvicMux7_IRQHandler [WEAK]
EXPORT NvicMux8_IRQHandler [WEAK]
EXPORT NvicMux9_IRQHandler [WEAK]
EXPORT NvicMux10_IRQHandler [WEAK]
EXPORT NvicMux11_IRQHandler [WEAK]
EXPORT NvicMux12_IRQHandler [WEAK]
EXPORT NvicMux13_IRQHandler [WEAK]
EXPORT NvicMux14_IRQHandler [WEAK]
EXPORT NvicMux15_IRQHandler [WEAK]
EXPORT NvicMux16_IRQHandler [WEAK]
EXPORT NvicMux17_IRQHandler [WEAK]
EXPORT NvicMux18_IRQHandler [WEAK]
EXPORT NvicMux19_IRQHandler [WEAK]
EXPORT NvicMux20_IRQHandler [WEAK]
EXPORT NvicMux21_IRQHandler [WEAK]
EXPORT NvicMux22_IRQHandler [WEAK]
EXPORT NvicMux23_IRQHandler [WEAK]
EXPORT NvicMux24_IRQHandler [WEAK]
EXPORT NvicMux25_IRQHandler [WEAK]
EXPORT NvicMux26_IRQHandler [WEAK]
EXPORT NvicMux27_IRQHandler [WEAK]
EXPORT NvicMux28_IRQHandler [WEAK]
EXPORT NvicMux29_IRQHandler [WEAK]
EXPORT NvicMux30_IRQHandler [WEAK]
EXPORT NvicMux31_IRQHandler [WEAK]
NvicMux0_IRQHandler
NvicMux1_IRQHandler
NvicMux2_IRQHandler
NvicMux3_IRQHandler
NvicMux4_IRQHandler
NvicMux5_IRQHandler
NvicMux6_IRQHandler
NvicMux7_IRQHandler
NvicMux8_IRQHandler
NvicMux9_IRQHandler
NvicMux10_IRQHandler
NvicMux11_IRQHandler
NvicMux12_IRQHandler
NvicMux13_IRQHandler
NvicMux14_IRQHandler
NvicMux15_IRQHandler
NvicMux16_IRQHandler
NvicMux17_IRQHandler
NvicMux18_IRQHandler
NvicMux19_IRQHandler
NvicMux20_IRQHandler
NvicMux21_IRQHandler
NvicMux22_IRQHandler
NvicMux23_IRQHandler
NvicMux24_IRQHandler
NvicMux25_IRQHandler
NvicMux26_IRQHandler
NvicMux27_IRQHandler
NvicMux28_IRQHandler
NvicMux29_IRQHandler
NvicMux30_IRQHandler
NvicMux31_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, =Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, =(Heap_Mem + Heap_Size)
LDR R3, =Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
; [] END OF FILE

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@ -0,0 +1,696 @@
;/**************************************************************************//**
; * @file startup_psoc6_01_cm4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00001000
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External interrupts Power Mode Description
DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms)
DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4
DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0
DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1
DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2
DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3
DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4
DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5
DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6
DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7
DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8
DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9
DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10
DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11
DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12
DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13
DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14
DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15
DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
DCD usb_interrupt_med_IRQHandler ; USB Interrupt
DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
EXPORT __ramVectors
AREA RESET_RAM, READWRITE, NOINIT
__ramVectors SPACE __Vectors_Size
AREA |.text|, CODE, READONLY
; Weak function for startup customization
;
; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
; because this function is executed as the first instruction in the ResetHandler.
; The PDL is also not initialized to use the proper register offsets.
; The user of this function is responsible for initializing the PDL and resources before using them.
;
Cy_OnResetUser PROC
EXPORT Cy_OnResetUser [WEAK]
BX LR
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT Cy_SystemInitFpuEnable
IMPORT __main
; Define strong function for startup customization
BL Cy_OnResetUser
; Disable global interrupts
CPSID I
; Copy vectors from ROM to RAM
LDR r1, =__Vectors
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
Vectors_Copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE Vectors_Copy
; Update Vector Table Offset Register. */
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb 0xF
; Enable the FPU if used
LDR R0, =Cy_SystemInitFpuEnable
BLX R0
LDR R0, =__main
BLX R0
; Should never get here
B .
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
Cy_SysLib_FaultHandler PROC
EXPORT Cy_SysLib_FaultHandler [WEAK]
B .
ENDP
HardFault_Wrapper\
PROC
EXPORT HardFault_Wrapper [WEAK]
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
bl L_API_call
L_MSP
mrs r0, MSP
L_API_call
bl Cy_SysLib_FaultHandler
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B HardFault_Wrapper
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT Default_Handler [WEAK]
EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK]
EXPORT ioss_interrupt_gpio_IRQHandler [WEAK]
EXPORT ioss_interrupt_vdd_IRQHandler [WEAK]
EXPORT lpcomp_interrupt_IRQHandler [WEAK]
EXPORT scb_8_interrupt_IRQHandler [WEAK]
EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK]
EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
EXPORT srss_interrupt_backup_IRQHandler [WEAK]
EXPORT srss_interrupt_IRQHandler [WEAK]
EXPORT pass_interrupt_ctbs_IRQHandler [WEAK]
EXPORT bless_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK]
EXPORT scb_0_interrupt_IRQHandler [WEAK]
EXPORT scb_1_interrupt_IRQHandler [WEAK]
EXPORT scb_2_interrupt_IRQHandler [WEAK]
EXPORT scb_3_interrupt_IRQHandler [WEAK]
EXPORT scb_4_interrupt_IRQHandler [WEAK]
EXPORT scb_5_interrupt_IRQHandler [WEAK]
EXPORT scb_6_interrupt_IRQHandler [WEAK]
EXPORT scb_7_interrupt_IRQHandler [WEAK]
EXPORT csd_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
EXPORT cpuss_interrupt_fm_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
EXPORT udb_interrupts_0_IRQHandler [WEAK]
EXPORT udb_interrupts_1_IRQHandler [WEAK]
EXPORT udb_interrupts_2_IRQHandler [WEAK]
EXPORT udb_interrupts_3_IRQHandler [WEAK]
EXPORT udb_interrupts_4_IRQHandler [WEAK]
EXPORT udb_interrupts_5_IRQHandler [WEAK]
EXPORT udb_interrupts_6_IRQHandler [WEAK]
EXPORT udb_interrupts_7_IRQHandler [WEAK]
EXPORT udb_interrupts_8_IRQHandler [WEAK]
EXPORT udb_interrupts_9_IRQHandler [WEAK]
EXPORT udb_interrupts_10_IRQHandler [WEAK]
EXPORT udb_interrupts_11_IRQHandler [WEAK]
EXPORT udb_interrupts_12_IRQHandler [WEAK]
EXPORT udb_interrupts_13_IRQHandler [WEAK]
EXPORT udb_interrupts_14_IRQHandler [WEAK]
EXPORT udb_interrupts_15_IRQHandler [WEAK]
EXPORT pass_interrupt_sar_IRQHandler [WEAK]
EXPORT audioss_interrupt_i2s_IRQHandler [WEAK]
EXPORT audioss_interrupt_pdm_IRQHandler [WEAK]
EXPORT profile_interrupt_IRQHandler [WEAK]
EXPORT smif_interrupt_IRQHandler [WEAK]
EXPORT usb_interrupt_hi_IRQHandler [WEAK]
EXPORT usb_interrupt_med_IRQHandler [WEAK]
EXPORT usb_interrupt_lo_IRQHandler [WEAK]
EXPORT pass_interrupt_dacs_IRQHandler [WEAK]
ioss_interrupts_gpio_0_IRQHandler
ioss_interrupts_gpio_1_IRQHandler
ioss_interrupts_gpio_2_IRQHandler
ioss_interrupts_gpio_3_IRQHandler
ioss_interrupts_gpio_4_IRQHandler
ioss_interrupts_gpio_5_IRQHandler
ioss_interrupts_gpio_6_IRQHandler
ioss_interrupts_gpio_7_IRQHandler
ioss_interrupts_gpio_8_IRQHandler
ioss_interrupts_gpio_9_IRQHandler
ioss_interrupts_gpio_10_IRQHandler
ioss_interrupts_gpio_11_IRQHandler
ioss_interrupts_gpio_12_IRQHandler
ioss_interrupts_gpio_13_IRQHandler
ioss_interrupts_gpio_14_IRQHandler
ioss_interrupt_gpio_IRQHandler
ioss_interrupt_vdd_IRQHandler
lpcomp_interrupt_IRQHandler
scb_8_interrupt_IRQHandler
srss_interrupt_mcwdt_0_IRQHandler
srss_interrupt_mcwdt_1_IRQHandler
srss_interrupt_backup_IRQHandler
srss_interrupt_IRQHandler
pass_interrupt_ctbs_IRQHandler
bless_interrupt_IRQHandler
cpuss_interrupts_ipc_0_IRQHandler
cpuss_interrupts_ipc_1_IRQHandler
cpuss_interrupts_ipc_2_IRQHandler
cpuss_interrupts_ipc_3_IRQHandler
cpuss_interrupts_ipc_4_IRQHandler
cpuss_interrupts_ipc_5_IRQHandler
cpuss_interrupts_ipc_6_IRQHandler
cpuss_interrupts_ipc_7_IRQHandler
cpuss_interrupts_ipc_8_IRQHandler
cpuss_interrupts_ipc_9_IRQHandler
cpuss_interrupts_ipc_10_IRQHandler
cpuss_interrupts_ipc_11_IRQHandler
cpuss_interrupts_ipc_12_IRQHandler
cpuss_interrupts_ipc_13_IRQHandler
cpuss_interrupts_ipc_14_IRQHandler
cpuss_interrupts_ipc_15_IRQHandler
scb_0_interrupt_IRQHandler
scb_1_interrupt_IRQHandler
scb_2_interrupt_IRQHandler
scb_3_interrupt_IRQHandler
scb_4_interrupt_IRQHandler
scb_5_interrupt_IRQHandler
scb_6_interrupt_IRQHandler
scb_7_interrupt_IRQHandler
csd_interrupt_IRQHandler
cpuss_interrupts_dw0_0_IRQHandler
cpuss_interrupts_dw0_1_IRQHandler
cpuss_interrupts_dw0_2_IRQHandler
cpuss_interrupts_dw0_3_IRQHandler
cpuss_interrupts_dw0_4_IRQHandler
cpuss_interrupts_dw0_5_IRQHandler
cpuss_interrupts_dw0_6_IRQHandler
cpuss_interrupts_dw0_7_IRQHandler
cpuss_interrupts_dw0_8_IRQHandler
cpuss_interrupts_dw0_9_IRQHandler
cpuss_interrupts_dw0_10_IRQHandler
cpuss_interrupts_dw0_11_IRQHandler
cpuss_interrupts_dw0_12_IRQHandler
cpuss_interrupts_dw0_13_IRQHandler
cpuss_interrupts_dw0_14_IRQHandler
cpuss_interrupts_dw0_15_IRQHandler
cpuss_interrupts_dw1_0_IRQHandler
cpuss_interrupts_dw1_1_IRQHandler
cpuss_interrupts_dw1_2_IRQHandler
cpuss_interrupts_dw1_3_IRQHandler
cpuss_interrupts_dw1_4_IRQHandler
cpuss_interrupts_dw1_5_IRQHandler
cpuss_interrupts_dw1_6_IRQHandler
cpuss_interrupts_dw1_7_IRQHandler
cpuss_interrupts_dw1_8_IRQHandler
cpuss_interrupts_dw1_9_IRQHandler
cpuss_interrupts_dw1_10_IRQHandler
cpuss_interrupts_dw1_11_IRQHandler
cpuss_interrupts_dw1_12_IRQHandler
cpuss_interrupts_dw1_13_IRQHandler
cpuss_interrupts_dw1_14_IRQHandler
cpuss_interrupts_dw1_15_IRQHandler
cpuss_interrupts_fault_0_IRQHandler
cpuss_interrupts_fault_1_IRQHandler
cpuss_interrupt_crypto_IRQHandler
cpuss_interrupt_fm_IRQHandler
cpuss_interrupts_cm0_cti_0_IRQHandler
cpuss_interrupts_cm0_cti_1_IRQHandler
cpuss_interrupts_cm4_cti_0_IRQHandler
cpuss_interrupts_cm4_cti_1_IRQHandler
tcpwm_0_interrupts_0_IRQHandler
tcpwm_0_interrupts_1_IRQHandler
tcpwm_0_interrupts_2_IRQHandler
tcpwm_0_interrupts_3_IRQHandler
tcpwm_0_interrupts_4_IRQHandler
tcpwm_0_interrupts_5_IRQHandler
tcpwm_0_interrupts_6_IRQHandler
tcpwm_0_interrupts_7_IRQHandler
tcpwm_1_interrupts_0_IRQHandler
tcpwm_1_interrupts_1_IRQHandler
tcpwm_1_interrupts_2_IRQHandler
tcpwm_1_interrupts_3_IRQHandler
tcpwm_1_interrupts_4_IRQHandler
tcpwm_1_interrupts_5_IRQHandler
tcpwm_1_interrupts_6_IRQHandler
tcpwm_1_interrupts_7_IRQHandler
tcpwm_1_interrupts_8_IRQHandler
tcpwm_1_interrupts_9_IRQHandler
tcpwm_1_interrupts_10_IRQHandler
tcpwm_1_interrupts_11_IRQHandler
tcpwm_1_interrupts_12_IRQHandler
tcpwm_1_interrupts_13_IRQHandler
tcpwm_1_interrupts_14_IRQHandler
tcpwm_1_interrupts_15_IRQHandler
tcpwm_1_interrupts_16_IRQHandler
tcpwm_1_interrupts_17_IRQHandler
tcpwm_1_interrupts_18_IRQHandler
tcpwm_1_interrupts_19_IRQHandler
tcpwm_1_interrupts_20_IRQHandler
tcpwm_1_interrupts_21_IRQHandler
tcpwm_1_interrupts_22_IRQHandler
tcpwm_1_interrupts_23_IRQHandler
udb_interrupts_0_IRQHandler
udb_interrupts_1_IRQHandler
udb_interrupts_2_IRQHandler
udb_interrupts_3_IRQHandler
udb_interrupts_4_IRQHandler
udb_interrupts_5_IRQHandler
udb_interrupts_6_IRQHandler
udb_interrupts_7_IRQHandler
udb_interrupts_8_IRQHandler
udb_interrupts_9_IRQHandler
udb_interrupts_10_IRQHandler
udb_interrupts_11_IRQHandler
udb_interrupts_12_IRQHandler
udb_interrupts_13_IRQHandler
udb_interrupts_14_IRQHandler
udb_interrupts_15_IRQHandler
pass_interrupt_sar_IRQHandler
audioss_interrupt_i2s_IRQHandler
audioss_interrupt_pdm_IRQHandler
profile_interrupt_IRQHandler
smif_interrupt_IRQHandler
usb_interrupt_hi_IRQHandler
usb_interrupt_med_IRQHandler
usb_interrupt_lo_IRQHandler
pass_interrupt_dacs_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
; [] END OF FILE

42
2020TPCApp0.cydsn/post_build_core1.bat Normal file
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@rem Usage:
@rem Call post_build_core1.bat <tool> <output_dir> <project_short_name>
@rem E.g. in PSoC Creator 4.2:
@rem post_build_core1.bat creator ${OutputDir} ${ProjectShortName}
@echo ------------------------------------------
@echo Post-build commands for Cortex-M4 core
@echo ------------------------------------------
@rem Set proper path to your PDL 3.x and above installation
@set PDL_PATH="C:\Program Files (x86)\Cypress\PDL\3.1.7"
@set CY_MCU_ELF_TOOL=%PDL_PATH%"\tools\win\elf\cymcuelftool.exe"
@set IDE=%1
@if "%IDE%" == "creator" (
@set OUTPUT_DIR=%2
@set PRJ_NAME=%3
@set ELF_EXT=.elf
)
@if "%IDE%" == "uvision" (
@set OUTPUT_DIR=%2
@set PRJ_NAME=%3
@set ELF_EXT=.axf
)
@if "%IDE%" == "iar" (
@set OUTPUT_DIR=%2
@set PRJ_NAME=%3
@set ELF_EXT=.out
)
@if "%IDE%" == "eclipse" (
@set OUTPUT_DIR=%2
@set PRJ_NAME=%3
@set ELF_EXT=
)
@rem Sign the application with the RSA private key
%CY_MCU_ELF_TOOL% -S %OUTPUT_DIR%\%PRJ_NAME%%ELF_EXT% SHA256 --encrypt RSASSA-PKCS --key ..\Keys\rsa_private.txt --output %OUTPUT_DIR%\%PRJ_NAME%_RSA%ELF_EXT% --hex %OUTPUT_DIR%\%PRJ_NAME%.hex

254
2020TPCApp0.cydsn/rsa_to_c.py Normal file
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#!/usr/bin/env python3
""" This script may be used to generate RSA public key modulus, exponent, and
additional coefficients. Additional coefficients are optional and are used
only to increase RSA calculation performance up to 4 times.
The format of output may be defined by command line arguments and is either
the raw HEX data, or the array.
Copyright (C) 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
You may use this file only in accordance with the license, terms, conditions,
disclaimers, and limitations in the end user license agreement accompanying
the software package with which this file was provided.
"""
import sys, subprocess, os
if sys.version_info < (3,):
integer_types = (int, long,)
## Used in convert_hexstr_to_list
else:
integer_types = (int,)
def main():
""" Main function
Build the strings to print out the public key modulus and exponent.
"""
if len(sys.argv) < 2:
print("Usage: %s <public_key_file_name> [-norev] [-out <file_name>]" % sys.argv[0])
return 1
isReverse = True
out_file_name = ''
for idx in range(len(sys.argv)):
if "-norev" == sys.argv[idx]:
isReverse = False
if "-out" == sys.argv[idx]:
out_file_name = sys.argv[idx+1]
modulus_list = [] # list to collect bytes of modulus
rsaExp = "" # string that will contain the parsed RSA exponent
key_len = 0 # containt the length in bits of an RSA modulus
try:
# build openssl command line
cmd_line = ['openssl', 'rsa', '-text', '-pubin', '-in',
sys.argv[1],
'-noout']
output, error = subprocess.Popen(
cmd_line, universal_newlines=True,
stdout=subprocess.PIPE, stderr=subprocess.PIPE).communicate()
# check for errors (warnings ignored)
lines = error.split("\n")
error_lines = []
for line in lines:
if (len(line) != 0) and (("WARNING:" in line) == False):
error_lines.append(line)
if len(error_lines) != 0:
print ("OpenSSL call failed" + "\n" + " ".join(cmd_line) + "\n" + str(error_lines) )
return 1
modulus_found = False
for line in output.split("\n"):
if "Public-Key" in line:
# get length of RSA modulus
key_len = int(line.split(" ")[1].replace("(", ''))
if "Modulus" in line:
# modulus record is found
modulus_found = True; continue
if "Exponent" in line:
modulus_found = False
# Exponent record is found
rsaExp = line.split(" ")[2][1:-1]
if modulus_found:
# Collect bytes of modulus to list
modulus_list = modulus_list + line.strip().split(":")
except subprocess.CalledProcessError as err:
print ("OpenSSL call failed with errorcode=" + str(err.returncode) \
+ "\n" + str(err.cmd) + "\n" + str(err.output))
return 1
#normalize data
# remove empty strings from modulus_list
modulus_list = [i for i in modulus_list if i]
if (len(modulus_list) == key_len // 8 + 1) and (int(modulus_list[0]) == 0):
# remove first zero byte
modulus_list.pop(0)
# Check parsed data
if not key_len:
print ("Key length was not gotten by parsing." )
return 1
if len(modulus_list) != (key_len // 8):
print ("Length of parsed Modulus (%s) is not equal to Key length (%s)." % (key_len, len(modulus_list) * 8))
return 1
modulus_hex_str = "".join(modulus_list)
(barret, inv_modulo, r_bar) = calculate_additional_rsa_key_coefs(modulus_hex_str)
barret_list = convert_hexstr_to_list(barret, isReverse)
# add three zero bytes
barret_list = ([0]*3 + barret_list) if not isReverse else (barret_list + [0]*3)
barret_str = build_returned_string(barret_list)
barret_str = ".barrettData =\n{\n%s\n}," % barret_str
inv_modulo_list = convert_hexstr_to_list(inv_modulo, isReverse)
inv_modulo_str = build_returned_string(inv_modulo_list)
inv_modulo_str = ".inverseModuloData =\n{\n%s\n}," % inv_modulo_str
r_bar_list = convert_hexstr_to_list(r_bar, isReverse)
r_bar_str = build_returned_string(r_bar_list)
r_bar_str = ".rBarData =\n{\n%s\n}," % r_bar_str
rsaExp_list = convert_hexstr_to_list(rsaExp, isReverse)
rsaExp_list_len = len(rsaExp_list)
if rsaExp_list_len % 4 != 0:
rsaExp_list = ([0]*(4-(rsaExp_list_len % 4)) + rsaExp_list) if not isReverse \
else (rsaExp_list + [0]*(4-(rsaExp_list_len % 4)))
rsaExp_str = build_returned_string(rsaExp_list)
rsaExp_str = ".expData =\n{\n%s\n}," % rsaExp_str
# Check and apply isReverse flag
if isReverse:
modulus_list.reverse()
modulus_str = build_returned_string(modulus_list)
modulus_str = ".moduloData =\n{\n%s\n}," % modulus_str
if not out_file_name:
print(modulus_str)
print(rsaExp_str)
print(barret_str)
print(inv_modulo_str)
print(r_bar_str)
else:
with open(out_file_name, 'w') as outfile:
outfile.write(modulus_str + "\n")
outfile.write(rsaExp_str + "\n")
outfile.write(barret_str + "\n")
outfile.write(inv_modulo_str + "\n")
outfile.write(r_bar_str + "\n")
return 0
def extended_euclid(modulo):
''' Calculate greatest common divisor (GCD) of two values.
Link: https://en.wikipedia.org/wiki/Extended_Euclidean_algorithm
formula to calculate: ax + by - gcd(a,b)
parameters:
a, b - two values witch is calculated GCD for.
return:
absolute values of x and y coefficients
NOTE: pseudo-code of operation:
x, lastX = 0, 1
y, lastY = 1, 0
while (b != 0):
q = a // b
a, b = b, a % b
x, lastX = lastX - q * x, x
y, lastY = lastY - q * y, y
return (abs(lastX), abs(lastY))
'''
rInv = 1;
nInv = 0;
modulo_bit_size = modulo.bit_length()
for i in range(modulo_bit_size):
if not (rInv % 2):
rInv = rInv // 2
nInv = nInv // 2
else:
rInv = rInv + modulo;
rInv = rInv // 2;
nInv = nInv // 2;
nInv = nInv + (1 << (modulo_bit_size - 1));
return rInv, nInv
def calculate_additional_rsa_key_coefs(modulo):
''' Calculate three additional coefficients for modulo value of RSA key
1. barret_coef - Barrett coefficient. Equation is: barretCoef = floor((2 << (2 * k)) / n);
Main article is here: https://en.wikipedia.org/wiki/Barrett_reduction
2. r_bar - pre-calculated value. Equation is: r_bar = (1 << k) mod n;
3. inverse_modulo - coefficient. It satisfying rr' - nn' = 1, where r = 1 << k;
Main article is here: https://en.wikipedia.org/wiki/Extended_Euclidean_algorithm
parameter:
modulo - part of RSA key
return:
tuple( barret_coef, r_bar, inverse_modulo ) as reversed byte arrays;
'''
if isinstance(modulo, str):
modulo = int(modulo, 16)
if modulo <= 0:
raise ValueError("Modulus must be positive")
if modulo & (modulo - 1) == 0:
raise ValueError("Modulus must not be a power of 2")
modulo_len = modulo.bit_length()
barret_coef = (1 << (modulo_len * 2)) // modulo
r_bar = (1 << modulo_len) % modulo
inverse_modulo = extended_euclid(modulo)
ret_arrays = (
barret_coef,
inverse_modulo[1],
r_bar
)
return ret_arrays
def convert_hexstr_to_list(s, reversed=False):
''' Converts a string likes '0001aaff...' to list [0, 1, 170, 255].
Also an input parameter can be an integer, in this case it will be
converted to a hex string.
parameter:
s - string to convert
reversed - a returned list have to be reversed
return:
a list of an integer values
'''
if isinstance(s, integer_types):
s = hex(s)
s = s[2 if s.lower().startswith("0x") else 0 : -1 if s.upper().endswith("L") else len(s)]
if len(s) % 2 != 0:
s = '0' + s
l = [int("0x%s" % s[i:i+2], 16) for i in range(0, len(s), 2)]
if reversed:
l.reverse()
return l
def build_returned_string(inp_list):
''' Converts a list to a C-style array of hexadecimal numbers string
'''
if isinstance(inp_list[0], int):
inp_list = ['%02X' % x for x in inp_list]
tmp_str = " "
for idx in range(0, len(inp_list)):
if (idx % 8 == 0) and (idx != 0):
tmp_str = tmp_str + "\n "
tmp_str = tmp_str + ( "0x%02Xu," % int(inp_list[idx], base=16) )
if (idx % 8 != 7) and (idx != len(inp_list) - 1):
tmp_str = tmp_str + " "
return tmp_str
if __name__ == "__main__":
main()

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2020TPCApp0.cydsn/system_psoc6.h Normal file
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/***************************************************************************//**
* \file system_psoc6.h
* \version 2.20
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#ifndef _SYSTEM_PSOC6_H_
#define _SYSTEM_PSOC6_H_
/**
* \addtogroup group_system_config
* \{
* Provides device startup, system configuration, and linker script files.
* The system startup provides the followings features:
* - See \ref group_system_config_device_initialization for the:
* * \ref group_system_config_dual_core_device_initialization
* * \ref group_system_config_single_core_device_initialization
* - \ref group_system_config_device_memory_definition
* - \ref group_system_config_heap_stack_config
* - \ref group_system_config_merge_apps
* - \ref group_system_config_default_handlers
* - \ref group_system_config_device_vector_table
* - \ref group_system_config_cm4_functions
*
* \section group_system_config_configuration Configuration Considerations
*
* \subsection group_system_config_device_memory_definition Device Memory Definition
* The flash and RAM allocation for each CPU is defined by the linker scripts.
* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
* For Single-Core devices the system reserves additional 80 bytes of RAM.
* Using the reserved memory area for other purposes will lead to unexpected behavior.
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see warnings during the build process. To eliminate build
* warnings in your project, you can simply comment out or remove the relevant
* code in the linker file.
*
* <b>ARM GCC</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM4() function call.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
* \endcode
* - 'xx_cm4_dual.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
* by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* <b>ARM MDK</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see the warnings during the build process:
* L6314W (no section matches pattern) and/or L6329W
* (pattern only matches removed unused sections). In your project, you can
* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
* the linker. You can also comment out or remove the relevant code in the linker
* file.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.scat', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08000000
* #define RAM_SIZE 0x00024000
* \endcode
* - 'xx_cm4_dual.scat', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10080000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08024000
* #define RAM_SIZE 0x00023800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
* value in the 'xx_cm4_dual.scat' file,
* where 'xx' is the device group. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* <b>IAR</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
* \endcode
* - 'xx_cm4_dual.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
* is the device group. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* \subsection group_system_config_device_initialization Device Initialization
* After a power-on-reset (POR), the boot process is handled by the boot code
* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
* code passes the control to the Cortex-M0+ startup code located in flash.
*
* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
* The Cortex-M0+ startup code performs the device initialization by a call to
* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
* See \ref group_system_config_cm4_functions for more details.
* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
* The function has a separate implementation on each core.
* Both function implementations unlock and disable the WDT.
* Therefore enable the WDT after both cores have been initialized.
*
* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
* The Cortex-M0+ core is not user-accessible on these devices. In this case the
* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
*
* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
* There are two ways to adjust heap and stack configurations:
* -# Editing source code files
* -# Specifying via command line
*
* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
*
* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* Change the heap and stack sizes by modifying the following lines:\n
* \code .equ Stack_Size, 0x00001000 \endcode
* \code .equ Heap_Size, 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the compiler:\n
* \code -D __STACK_SIZE=0x000000400 \endcode
* \code -D __HEAP_SIZE=0x000000100 \endcode
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the assembler:\n
* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
*
* \subsubsection group_system_config_heap_stack_config_iar IAR
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the
* linker (including quotation marks):\n
* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
*
* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
* The CM0+ project and linker script build the CM0+ application image. Similarly,
* the CM4 linker script builds the CM4 application image. Each specifies
* locations, sizes, and contents of sections in memory. See
* \ref group_system_config_device_memory_definition for the symbols and default
* values.
*
* The cymcuelftool is invoked by a post-build command. The precise project
* setting is IDE-specific.
*
* The cymcuelftool combines the two executables. The tool examines the
* executables to ensure that memory regions either do not overlap, or contain
* identical bytes (shared). If there are no problems, it creates a new ELF file
* with the merged image, without changing any of the addresses or data.
*
* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
* The default interrupt handler functions are defined as weak functions to a dummy
* handler in the startup file. The naming convention for the interrupt handler names
* is <interrupt_name>_IRQHandler. A default interrupt handler can be overwritten in
* user code by defining the handler function using the same name. For example:
* \code
* void scb_0_interrupt_IRQHandler(void)
*{
* ...
*}
* \endcode
*
* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
* This process uses memory sections defined in the linker script. The startup
* code actually defines the contents of the vector table and performs the copy.
* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
* It defines sections and locations in memory.\n
* Copy interrupt vectors from flash to RAM: \n
* From: \code LONG (__Vectors) \endcode
* To: \code LONG (__ram_vectors_start__) \endcode
* Size: \code LONG (__Vectors_End - __Vectors) \endcode
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* The code in these files copies the vector table from Flash to RAM.
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
* (RESET_RAM) shall be first in the RAM section.\n
* RESET_RAM represents the vector table. It is defined in the assembler startup
* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \subsubsection group_system_config_device_vector_table_iar IAR
* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* This file defines the .intvec_ram section and its location.
* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \section group_system_config_more_information More Information
* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
* more details.
*
* \section group_system_config_MISRA MISRA Compliance
*
* <table class="doxtable">
* <tr>
* <th>MISRA Rule</th>
* <th>Rule Class (Required/Advisory)</th>
* <th>Rule Description</th>
* <th>Description of Deviation(s)</th>
* </tr>
* <tr>
* <td>2.3</td>
* <td>R</td>
* <td>The character sequence // shall not be used within a comment.</td>
* <td>The comments provide a useful WEB link to the documentation.</td>
* </tr>
* </table>
*
* \section group_system_config_changelog Changelog
* <table class="doxtable">
* <tr>
* <th>Version</th>
* <th>Changes</th>
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.20</td>
* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
* <td>Changed the IPC driver configuration method from compile time to run time.</td>
* </tr>
* <tr>
* <td rowspan="2"> 2.10</td>
* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
* Removed $Sub$$main symbol for ARM MDK compiler.
* </td>
* <td>uVision Debugger support.</td>
* </tr>
* <tr>
* <td>Updated description of the Startup behavior for Single-Core Devices. \n
* Added note about WDT disabling by SystemInit() function.
* </td>
* <td>Documentation improvement.</td>
* </tr>
* <tr>
* <td rowspan="4"> 2.0</td>
* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
* Single core device support.
* </td>
* <td></td>
* </tr>
* <tr>
* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
* Renamed 'wflash' memory region to 'em_eeprom'.
* </td>
* <td>Linker scripts usability improvement.</td>
* </tr>
* <tr>
* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
* <td>Reserved system resources for internal operations.</td>
* </tr>
* <tr>
* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
* </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
*
* \defgroup group_system_config_macro Macro
* \{
* \defgroup group_system_config_system_macro System
* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
* \defgroup group_system_config_user_settings_macro User Settings
* \}
* \defgroup group_system_config_functions Functions
* \{
* \defgroup group_system_config_system_functions System
* \defgroup group_system_config_cm4_functions Cortex-M4 Control
* \}
* \defgroup group_system_config_globals Global Variables
*
* \}
*/
/**
* \addtogroup group_system_config_system_functions
* \{
* \details
* The following system functions implement CMSIS Core functions.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* \}
*/
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Include files
*******************************************************************************/
#include <stdint.h>
/*******************************************************************************
* Global preprocessor symbols/macros ('define')
*******************************************************************************/
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
#define CY_SYSTEM_CPU_CM0P 1UL
#else
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
* START OF USER SETTINGS HERE
* ===========================
*
* All lines with '<<<' can be set by user.
*
*******************************************************************************/
/**
* \addtogroup group_system_config_user_settings_macro
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CORTEX_M4_APPL_ADDR ( CY_FLASH_BASE + CY_FLASH_SIZE / 2U) /* <<< Half of flash is reserved for the Cortex-M0+ application */
/***************************************************************************//**
* \brief IPC Semaphores allocation ([value]UL).
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
/***************************************************************************//**
* \brief IPC Pipe definitions ([value]UL).
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
/*******************************************************************************
*
* END OF USER SETTINGS HERE
* =========================
*
*******************************************************************************/
/** \} group_system_config_user_settings_macro */
/**
* \addtogroup group_system_config_system_macro
* \{
*/
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
/** The Cortex-M0+ startup driver identifier */
#define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
/** The Cortex-M4 startup driver identifier */
#define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
/** \} group_system_config_system_macro */
/**
* \addtogroup group_system_config_system_functions
* \{
*/
#if defined(__ARMCC_VERSION)
extern void SystemInit(void) __attribute__((constructor));
#else
extern void SystemInit(void);
#endif /* (__ARMCC_VERSION) */
extern void SystemCoreClockUpdate(void);
/** \} group_system_config_system_functions */
/**
* \addtogroup group_system_config_cm4_functions
* \{
*/
extern uint32_t Cy_SysGetCM4Status(void);
extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
extern void Cy_SysDisableCM4(void);
extern void Cy_SysRetainCM4(void);
extern void Cy_SysResetCM4(void);
/** \} group_system_config_cm4_functions */
/** \cond */
extern void Default_Handler (void);
void Cy_SysIpcPipeIsrCm0(void);
void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
/** \endcond */
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
/**
* \addtogroup group_system_config_cm4_status_macro
* \{
*/
#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
/** \} group_system_config_cm4_status_macro */
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
/*******************************************************************************
* IPC Configuration
* =========================
*******************************************************************************/
/* IPC CY_PIPE default configuration */
#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
/*
* The System pipe configuration defines the IPC channel number, interrupt
* number, and the pipe interrupt mask for the endpoint.
*
* The format of the endPoint configuration
* Bits[31:16] Interrupt Mask
* Bits[15:8 ] IPC interrupt
* Bits[ 7:0 ] IPC channel
*/
/* System Pipe addresses */
/* CyPipe defines */
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
/** \addtogroup group_system_config_globals
* \{
*/
extern uint32_t SystemCoreClock;
extern uint32_t cy_BleEcoClockFreqHz;
extern uint32_t cy_Hfclk0FreqHz;
extern uint32_t cy_PeriClkFreqHz;
/** \} group_system_config_globals */
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
/* BWC defines for functions related to enter/exit critical section */
#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
/** \endcond */
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_PSOC6_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file system_psoc6_cm0plus.c
* \version 2.20
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <stdbool.h>
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
#include "cy_ipc_pipe.h"
#include "cy_ipc_drv.h"
#if defined(CY_DEVICE_PSOC6ABLE2)
#include "cy_flash.h"
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
/*******************************************************************************
* SystemCoreClockUpdate()
*******************************************************************************/
/** Default HFClk frequency in Hz */
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL)
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL)
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
* which is the system clock frequency supplied to the SysTick timer and the
* processor core clock.
* This variable implements CMSIS Core global variable.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* This variable can be used by debuggers to query the frequency
* of the debug timer or to configure the trace clock speed.
*
* \attention Compilers must be configured to avoid removing this variable in case
* the application program is not using it. Debugging systems require the variable
* to be physically present in memory so that it can be examined to configure the debugger. */
uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/*******************************************************************************
* SystemInit()
*******************************************************************************/
/* CLK_FLL_CONFIG default values */
#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/*******************************************************************************
* SystemCoreClockUpdate (void)
*******************************************************************************/
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
/*******************************************************************************
* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
*******************************************************************************/
#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
/*******************************************************************************
* Function Name: SystemInit
****************************************************************************//**
*
* Initializes the system:
* - Restores FLL registers to the default state.
* - Unlocks and disables WDT.
* - Calls Cy_PDL_Init() function to define the driver library.
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
* - Calls \ref SystemCoreClockUpdate().
*
*******************************************************************************/
void SystemInit(void)
{
Cy_PDL_Init(CY_DEVICE_CFG);
/* Restore FLL registers to the default state as they are not restored by the ROM code */
uint32_t copy = SRSS->CLK_FLL_CONFIG;
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
SRSS->CLK_FLL_CONFIG = copy;
copy = SRSS->CLK_ROOT_SELECT[0u];
copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
SRSS->CLK_ROOT_SELECT[0u] = copy;
SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
/* Unlock and disable WDT */
Cy_WDT_Unlock();
Cy_WDT_Disable();
Cy_SystemInit();
SystemCoreClockUpdate();
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
{
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
IPC_STRUCT7->DATA = 0UL;
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
IPC_STRUCT7->RELEASE = 0UL;
}
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/* Allocate and initialize semaphores for the system operations. */
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
/********************************************************************************
*
* Initializes the system pipes. The system pipes are used by BLE and Flash.
*
* If the default startup file is not used, or SystemInit() is not called in your
* project, call the following three functions prior to executing any flash or
* EmEEPROM write or erase operation:
* -# Cy_IPC_Sema_Init()
* -# Cy_IPC_Pipe_Config()
* -# Cy_IPC_Pipe_Init()
* -# Cy_Flash_Init()
*
*******************************************************************************/
/* Create an array of endpoint structures */
static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
{
/* .ep0ConfigData */
{
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
/* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
/* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
},
/* .ep1ConfigData */
{
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
/* .ipcNotifierMuxNumber */ 0u,
/* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
},
/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
/* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
}
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**
*
* The function is called during device startup. Once project compiled as part of
* the PSoC Creator project, the Cy_SystemInit() function is generated by the
* PSoC Creator.
*
* The function generated by PSoC Creator performs all of the necessary device
* configuration based on the design settings. This includes settings from the
* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
* configuration that is necessary.
*
*******************************************************************************/
__WEAK void Cy_SystemInit(void)
{
/* Empty weak function. The actual implementation to be in the PSoC Creator
* generated strong function.
*/
}
/*******************************************************************************
* Function Name: SystemCoreClockUpdate
****************************************************************************//**
*
* Gets core clock frequency and updates \ref SystemCoreClock, \ref
* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
*
* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
*
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t slowClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if (rootPath == 1UL)
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Slow Clock Divider */
slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
pathFreqHz = pathFreqHz / periClkDiv;
cy_PeriClkFreqHz = pathFreqHz;
pathFreqHz = pathFreqHz / slowClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
/*******************************************************************************
* Function Name: Cy_SysGetCM4Status
****************************************************************************//**
*
* Returns the Cortex-M4 core power mode.
*
* \return \ref group_system_config_cm4_status_macro
*
*******************************************************************************/
uint32_t Cy_SysGetCM4Status(void)
{
uint32_t regValue;
/* Get current power mode */
regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
return (regValue);
}
/*******************************************************************************
* Function Name: Cy_SysEnableCM4
****************************************************************************//**
*
* Sets vector table base address and enables the Cortex-M4 core.
*
* \note If the CPU is already enabled, it is reset and then enabled.
*
* \param vectorTableOffset The offset of the vector table base address from
* memory address 0x00000000. The offset should be multiple to 1024 bytes.
*
*******************************************************************************/
void Cy_SysEnableCM4(uint32_t vectorTableOffset)
{
uint32_t regValue;
uint32_t interruptState;
uint32_t cpuState;
CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
interruptState = Cy_SysLib_EnterCriticalSection();
cpuState = Cy_SysGetCM4Status();
if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
{
Cy_SysResetCM4();
}
CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM4_STATUS_ENABLED;
CPUSS->CM4_PWR_CTL = regValue;
while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
Cy_SysLib_ExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: Cy_SysDisableCM4
****************************************************************************//**
*
* Disables the Cortex-M4 core and waits for the mode to take the effect.
*
* \warning Do not call the function while the Cortex-M4 is executing because
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
* unexpected behavior in the system including a deadlock. Call the function
* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
* CPU.
*
*******************************************************************************/
void Cy_SysDisableCM4(void)
{
uint32_t interruptState;
uint32_t regValue;
interruptState = Cy_SysLib_EnterCriticalSection();
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM4_STATUS_DISABLED;
CPUSS->CM4_PWR_CTL = regValue;
while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
Cy_SysLib_ExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: Cy_SysRetainCM4
****************************************************************************//**
*
* Retains the Cortex-M4 core and exists without waiting for the mode to take
* effect.
*
* \note The retained mode can be entered only from the enabled mode.
*
* \warning Do not call the function while the Cortex-M4 is executing because
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
* unexpected behavior in the system including a deadlock. Call the function
* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
*
*******************************************************************************/
void Cy_SysRetainCM4(void)
{
uint32_t interruptState;
uint32_t regValue;
interruptState = Cy_SysLib_EnterCriticalSection();
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM4_STATUS_RETAINED;
CPUSS->CM4_PWR_CTL = regValue;
Cy_SysLib_ExitCriticalSection(interruptState);
}
/*******************************************************************************
* Function Name: Cy_SysResetCM4
****************************************************************************//**
*
* Resets the Cortex-M4 core and waits for the mode to take the effect.
*
* \note The reset mode can not be entered from the retained mode.
*
* \warning Do not call the function while the Cortex-M4 is executing because
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
* unexpected behavior in the system including a deadlock. Call the function
* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
*
*******************************************************************************/
void Cy_SysResetCM4(void)
{
uint32_t interruptState;
uint32_t regValue;
interruptState = Cy_SysLib_EnterCriticalSection();
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
regValue |= CY_SYS_CM4_STATUS_RESET;
CPUSS->CM4_PWR_CTL = regValue;
while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
{
/* Wait for the power mode to take effect */
}
Cy_SysLib_ExitCriticalSection(interruptState);
}
#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/*******************************************************************************
* Function Name: Cy_SysIpcPipeIsrCm0
****************************************************************************//**
*
* This is the interrupt service routine for the system pipe.
*
*******************************************************************************/
void Cy_SysIpcPipeIsrCm0(void)
{
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
}
#endif
/*******************************************************************************
* Function Name: Cy_MemorySymbols
****************************************************************************//**
*
* The intention of the function is to declare boundaries of the memories for the
* MDK compilers. For the rest of the supported compilers, this is done using
* linker configuration files. The following symbols used by the cymcuelftool.
*
*******************************************************************************/
#if defined (__ARMCC_VERSION)
__asm void Cy_MemorySymbols(void)
{
/* Flash */
EXPORT __cy_memory_0_start
EXPORT __cy_memory_0_length
EXPORT __cy_memory_0_row_size
/* Working Flash */
EXPORT __cy_memory_1_start
EXPORT __cy_memory_1_length
EXPORT __cy_memory_1_row_size
/* Supervisory Flash */
EXPORT __cy_memory_2_start
EXPORT __cy_memory_2_length
EXPORT __cy_memory_2_row_size
/* XIP */
EXPORT __cy_memory_3_start
EXPORT __cy_memory_3_length
EXPORT __cy_memory_3_row_size
/* eFuse */
EXPORT __cy_memory_4_start
EXPORT __cy_memory_4_length
EXPORT __cy_memory_4_row_size
/* Flash */
__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
__cy_memory_0_row_size EQU 0x200
/* Flash region for EEPROM emulation */
__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
__cy_memory_1_row_size EQU 0x200
/* Supervisory Flash */
__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
__cy_memory_2_row_size EQU 0x200
/* XIP */
__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
__cy_memory_3_row_size EQU 0x200
/* eFuse */
__cy_memory_4_start EQU __cpp(0x90700000)
__cy_memory_4_length EQU __cpp(0x100000)
__cy_memory_4_row_size EQU __cpp(1)
}
#endif /* defined (__ARMCC_VERSION) */
/* [] END OF FILE */

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/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.20
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <stdbool.h>
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
#include "cy_ipc_pipe.h"
#include "cy_ipc_drv.h"
#if defined(CY_DEVICE_PSOC6ABLE2)
#include "cy_flash.h"
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
/*******************************************************************************
* SystemCoreClockUpdate()
*******************************************************************************/
/** Default HFClk frequency in Hz */
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (150000000UL)
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (75000000UL)
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (75000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
* which is the system clock frequency supplied to the SysTick timer and the
* processor core clock.
* This variable implements CMSIS Core global variable.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* This variable can be used by debuggers to query the frequency
* of the debug timer or to configure the trace clock speed.
*
* \attention Compilers must be configured to avoid removing this variable in case
* the application program is not using it. Debugging systems require the variable
* to be physically present in memory so that it can be examined to configure the debugger. */
uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
/*******************************************************************************
* SystemInit()
*******************************************************************************/
/* CLK_FLL_CONFIG default values */
#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/*******************************************************************************
* SystemCoreClockUpdate (void)
*******************************************************************************/
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
/*******************************************************************************
* Function Name: SystemInit
****************************************************************************//**
* \cond
* Initializes the system:
* - Restores FLL registers to the default state for single core devices.
* - Unlocks and disables WDT.
* - Calls Cy_PDL_Init() function to define the driver library.
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
* - Calls \ref SystemCoreClockUpdate().
* \endcond
*******************************************************************************/
void SystemInit(void)
{
Cy_PDL_Init(CY_DEVICE_CFG);
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Restore FLL registers to the default state as they are not restored by the ROM code */
uint32_t copy = SRSS->CLK_FLL_CONFIG;
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
SRSS->CLK_FLL_CONFIG = copy;
copy = SRSS->CLK_ROOT_SELECT[0u];
copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
SRSS->CLK_ROOT_SELECT[0u] = copy;
SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
/* Unlock and disable WDT */
Cy_WDT_Unlock();
Cy_WDT_Disable();
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
Cy_SystemInit();
SystemCoreClockUpdate();
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Allocate and initialize semaphores for the system operations. */
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
#else
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
#endif /* (__CM0P_PRESENT) */
#else
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
#endif /* __CM0P_PRESENT */
/********************************************************************************
*
* Initializes the system pipes. The system pipes are used by BLE and Flash.
*
* If the default startup file is not used, or SystemInit() is not called in your
* project, call the following three functions prior to executing any flash or
* EmEEPROM write or erase operation:
* -# Cy_IPC_Sema_Init()
* -# Cy_IPC_Pipe_Config()
* -# Cy_IPC_Pipe_Init()
* -# Cy_Flash_Init()
*
*******************************************************************************/
/* Create an array of endpoint structures */
static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
{
/* .ep0ConfigData */
{
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
/* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
/* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
},
/* .ep1ConfigData */
{
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
/* .ipcNotifierMuxNumber */ 0u,
/* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
},
/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
/* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**
*
* The function is called during device startup. Once project compiled as part of
* the PSoC Creator project, the Cy_SystemInit() function is generated by the
* PSoC Creator.
*
* The function generated by PSoC Creator performs all of the necessary device
* configuration based on the design settings. This includes settings from the
* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
* configuration that is necessary.
*
*******************************************************************************/
__WEAK void Cy_SystemInit(void)
{
/* Empty weak function. The actual implementation to be in the PSoC Creator
* generated strong function.
*/
}
/*******************************************************************************
* Function Name: SystemCoreClockUpdate
****************************************************************************//**
*
* Gets core clock frequency and updates \ref SystemCoreClock, \ref
* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
*
* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
*
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if (rootPath == 1UL)
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[0UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[0UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[0UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
/*******************************************************************************
* Function Name: Cy_SystemInitFpuEnable
****************************************************************************//**
*
* Enables the FPU if it is used. The function is called from the startup file.
*
*******************************************************************************/
void Cy_SystemInitFpuEnable(void)
{
#if defined (__FPU_USED) && (__FPU_USED == 1U)
uint32_t interruptState;
interruptState = Cy_SysLib_EnterCriticalSection();
SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
__DSB();
__ISB();
Cy_SysLib_ExitCriticalSection(interruptState);
#endif /* (__FPU_USED) && (__FPU_USED == 1U) */
}
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/*******************************************************************************
* Function Name: Cy_SysIpcPipeIsrCm4
****************************************************************************//**
*
* This is the interrupt service routine for the system pipe.
*
*******************************************************************************/
void Cy_SysIpcPipeIsrCm4(void)
{
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
}
#endif
/*******************************************************************************
* Function Name: Cy_MemorySymbols
****************************************************************************//**
*
* The intention of the function is to declare boundaries of the memories for the
* MDK compilers. For the rest of the supported compilers, this is done using
* linker configuration files. The following symbols used by the cymcuelftool.
*
*******************************************************************************/
#if defined (__ARMCC_VERSION)
__asm void Cy_MemorySymbols(void)
{
/* Flash */
EXPORT __cy_memory_0_start
EXPORT __cy_memory_0_length
EXPORT __cy_memory_0_row_size
/* Working Flash */
EXPORT __cy_memory_1_start
EXPORT __cy_memory_1_length
EXPORT __cy_memory_1_row_size
/* Supervisory Flash */
EXPORT __cy_memory_2_start
EXPORT __cy_memory_2_length
EXPORT __cy_memory_2_row_size
/* XIP */
EXPORT __cy_memory_3_start
EXPORT __cy_memory_3_length
EXPORT __cy_memory_3_row_size
/* eFuse */
EXPORT __cy_memory_4_start
EXPORT __cy_memory_4_length
EXPORT __cy_memory_4_row_size
/* Flash */
__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
__cy_memory_0_row_size EQU 0x200
/* Flash region for EEPROM emulation */
__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
__cy_memory_1_row_size EQU 0x200
/* Supervisory Flash */
__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
__cy_memory_2_row_size EQU 0x200
/* XIP */
__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
__cy_memory_3_row_size EQU 0x200
/* eFuse */
__cy_memory_4_start EQU __cpp(0x90700000)
__cy_memory_4_length EQU __cpp(0x100000)
__cy_memory_4_row_size EQU __cpp(1)
}
#endif /* defined (__ARMCC_VERSION) */
/* [] END OF FILE */

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/***************************************************************************//**
* \file transport_ble.c
* \version 3.0
*
* This file provides the source code of the DFU communication APIs
* for the BLE Component.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "transport_ble.h"
#if defined(CY_PSOC_CREATOR_USED)
#include "BLE.h"
#else
#include "cy_flash.h"
#include "ble/cy_ble_gap.h"
#include "ble/cy_ble_stack.h"
#endif /* defined(CY_PSOC_CREATOR_USED) */
#include "ble/cy_ble_stack_host_error.h"
#include "ble/cy_ble_event_handler.h"
#include "ble/cy_ble_bts.h"
#if CY_BLE_HOST_CORE
static uint16_t cyBle_btsDataPacketIndex = 0u;
static uint8_t cyBle_cmdReceivedFlag = 0u;
static uint16_t cyBle_cmdLength = 0u;
static uint8_t *cyBle_btsBuffPtr;
static uint16_t cyBle_btsDataPacketSize = 0u;
static uint8_t cyBle_btsDataBuffer[CY_FLASH_SIZEOF_ROW + CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM];
/* Connection Handle */
cy_stc_ble_conn_handle_t appConnHandle;
/*******************************************************************************
* Function Name: CyBLE_CyBtldrCommStart
****************************************************************************//**
*
* Initializes DFU state for BLE communication.
*
*******************************************************************************/
void CyBLE_CyBtldrCommStart(void)
{
#if defined(CY_PSOC_CREATOR_USED)
/* Start BLE and register the callback function */
(void)Cy_BLE_Start(&AppCallBack);
/* Registers a callback function for DFU */
(void)Cy_BLE_BTS_RegisterAttrCallback(&DFUCallBack);
#endif /* defined(CY_PSOC_CREATOR_USED) */
cyBle_btsDataPacketIndex = 0u;
}
/*******************************************************************************
* Function Name: CyBLE_CyBtldrCommStop
****************************************************************************//**
*
* Disconnects from the peer device and stops BLE component.
*
******************************************************************************/
void CyBLE_CyBtldrCommStop(void)
{
cy_stc_ble_gap_disconnect_info_t disconnectInfoParam =
{
.bdHandle = appConnHandle.bdHandle,
.reason = CY_BLE_HCI_ERROR_OTHER_END_TERMINATED_USER
};
/* Initiate disconnection from the peer device*/
if(Cy_BLE_GAP_Disconnect(&disconnectInfoParam) == CY_BLE_SUCCESS)
{
/* Wait for disconnection event */
while(Cy_BLE_GetConnectionState(appConnHandle) == CY_BLE_CONN_STATE_CONNECTED)
{
/* Process BLE events */
Cy_BLE_ProcessEvents();
}
}
/* Stop BLE component. Ignores an error code because current function returns nothing */
(void) Cy_BLE_Disable();
}
/*******************************************************************************
* Function Name: CyBtldrCommReset
****************************************************************************//**
*
* Resets DFU state for BLE communication.
*
*******************************************************************************/
void CyBLE_CyBtldrCommReset(void)
{
cyBle_btsDataPacketIndex = 0u;
}
/*******************************************************************************
* Function Name: CyBLE_CyBtldrCommWrite
****************************************************************************//**
*
* Requests that the provided size (number of bytes) should be written from the
* input data buffer to the host device. This function in turn invokes the
* CyBle_GattsNotification() API to sent the data. If a notification is
* accepted, the function returns CYRET_SUCCESS. The timeOut parameter is ignored
* in this case.
*
* \param data The pointer to the buffer containing data to be written.
* \param size The number of bytes from the data buffer to write.
* \param count The pointer to where the BLE component will write the number
* of written bytes, generally the same as the size.
* \param timeOut Ignored. Used for consistency.
*
* \return
* The return value is of type \ref cy_en_dfu_status_t:
* - CY_DFU_SUCCESS - Indicates if a notification is successful.
* - CY_DFU_ERROR_UNKNOWN - Failed to send notification to the host.
*
*******************************************************************************/
cy_en_dfu_status_t CyBLE_CyBtldrCommWrite(const uint8_t pData[], uint32_t size, uint32_t *count, uint32_t timeout)
{
cy_en_dfu_status_t status = CY_DFU_ERROR_UNKNOWN;
if (timeout == 0u)
{
/* empty */
}
if(Cy_BLE_BTSS_SendNotification(appConnHandle, CY_BLE_BTS_BT_SERVICE, size, (const uint8 *)pData) == CY_BLE_SUCCESS)
{
*count = size;
status = CY_DFU_SUCCESS;
}
else
{
*count = 0u;
}
return (status);
}
/*******************************************************************************
* Function Name: CyBLE_CyBtldrCommRead
****************************************************************************//**
*
* Requests that the provided size (number of bytes) is read from the host device
* and stored in the provided data buffer. Once the read is done, the "count" is
* endorsed with the number of bytes written. The timeOut parameter is used to
* provide an upper bound on the time that the function is allowed to operate. If
* the read completes early, it should return success code as soon as possible.
* If the read was not successful before the allocated time has expired, it
* should return an error.
*
* \param data The pointer to the buffer to store data from the host controller.
* \param size The number of bytes to read into the data buffer.
* \param count The pointer to where the BLE component will write the number of
* read bytes.
* \param timeout The amount of time (in milliseconds) for which the
* BLE component should wait before indicating communication
* time out.
*
* \return
* The return value is of type \ref cy_en_dfu_status_t:
* - CY_DFU_SUCCESS - A command was successfully read.
* - CY_DFU_ERROR_DATA - The size of the command exceeds the buffer.
* - CY_DFU_ERROR_TIMEOUT - The host controller did not respond during
specified time out.
* \sideeffect
* \ref CyBle_ProcessEvents() is called as a part of this function.
*
*******************************************************************************/
cy_en_dfu_status_t CyBLE_CyBtldrCommRead(uint8_t pData[], uint32_t size, uint32_t *count, uint32_t timeout)
{
cy_en_dfu_status_t status = CY_DFU_ERROR_UNKNOWN;
if ((pData != NULL) && (size > 0u))
{
status = CY_DFU_ERROR_TIMEOUT;
while(timeout != 0u)
{
/* Process BLE events */
Cy_BLE_ProcessEvents();
if(cyBle_cmdReceivedFlag == 1u)
{
/* Clear command receive flag */
cyBle_cmdReceivedFlag = 0u;
if(cyBle_cmdLength < size)
{
(void) memcpy((void *) pData, (const void *) cyBle_btsBuffPtr, (uint32_t)cyBle_cmdLength);
/* Return actual received command length */
*count = cyBle_cmdLength;
status = CY_DFU_SUCCESS;
}
else
{
pData = NULL;
*count = 0u;
status = CY_DFU_ERROR_DATA;
}
break;
}
/* Wait 1 ms and update timeout counter */
Cy_SysLib_Delay(1u);
--timeout;
}
/* Process BLE events */
Cy_BLE_ProcessEvents();
}
return (status);
}
/*******************************************************************************
* Function Name: DFUCallBack
****************************************************************************//**
*
* Handles the events from the BLE stack for the DFU Service.
*
* \param eventCode Event code
* \param eventParam Event parameters
*
*******************************************************************************/
void DFUCallBack(uint32 event, void* eventParam)
{
/* To remove incorrect compiler warning */
(void)eventParam;
switch ((cy_en_ble_evt_t)event)
{
case CY_BLE_EVT_BTSS_NOTIFICATION_ENABLED:
break;
case CY_BLE_EVT_BTSS_NOTIFICATION_DISABLED:
break;
case CY_BLE_EVT_BTSS_EXEC_WRITE_REQ:
/* Check the execWriteFlag before execute or cancel write long operation */
if(((cy_stc_ble_gatts_exec_write_req_t *)eventParam)->execWriteFlag == CY_BLE_GATT_EXECUTE_WRITE_EXEC_FLAG)
{
cyBle_btsBuffPtr = ((cy_stc_ble_gatts_exec_write_req_t *)eventParam)->baseAddr[0u].handleValuePair.value.val;
/* Extract length of command data and add control bytes to data
* length to get command length.
*/
cyBle_cmdLength = (((uint16)(((uint16) cyBle_btsBuffPtr[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET + 1u]) << 8u)) |
(uint16) cyBle_btsBuffPtr[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET]) +
CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM;
if(cyBle_cmdLength > CYBLE_BTS_COMMAND_MAX_LENGTH)
{
cyBle_cmdLength = CYBLE_BTS_COMMAND_MAX_LENGTH;
}
/* Set flag for DFU to know that command is received from host */
cyBle_cmdReceivedFlag = 1u;
}
break;
case CY_BLE_EVT_BTSS_PREP_WRITE_REQ:
if(((cy_stc_ble_gatts_prep_write_req_param_t *)eventParam)->currentPrepWriteReqCount == 1u)
{
/* Send Prepare Write Response which identifies acknowledgement for
* long characteristic value write.
*/
cyBle_cmdLength = 0u;
}
break;
case CY_BLE_EVT_BTSS_WRITE_CMD_REQ:
{
uint8 *localDataBuffer = ((cy_stc_ble_bts_char_value_t *)eventParam)->value->val;
/* This is the beginning of the packet, let's read the size now */
if(cyBle_btsDataPacketIndex == 0u)
{
cyBle_btsDataPacketSize = (((uint16)(((uint16) localDataBuffer[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET + 1u]) << 8u)) |
(uint16) localDataBuffer[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET]) +
CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM;
}
(void) memcpy(&cyBle_btsDataBuffer[cyBle_btsDataPacketIndex], localDataBuffer, (uint32_t) ((cy_stc_ble_bts_char_value_t *)eventParam)->value->len);
cyBle_btsDataPacketIndex += ((cy_stc_ble_bts_char_value_t *)eventParam)->value->len;
if(cyBle_btsDataPacketIndex == cyBle_btsDataPacketSize)
{
cyBle_btsBuffPtr = &cyBle_btsDataBuffer[0];
cyBle_cmdLength = cyBle_btsDataPacketSize;
cyBle_cmdReceivedFlag = 1u;
cyBle_btsDataPacketIndex = 0u;
}
break;
}
case CY_BLE_EVT_BTSS_WRITE_REQ:
cyBle_btsBuffPtr =
CY_BLE_GATT_DB_ATTR_GET_ATTR_GEN_PTR(cy_ble_btsConfigPtr->btss->btServiceInfo[0u].btServiceCharHandle);
/* Extract length of command data and add control bytes to data
* length to get command length.
*/
cyBle_cmdLength = (((uint16)(((uint16) cyBle_btsBuffPtr[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET + 1u]) << 8u)) |
(uint16) cyBle_btsBuffPtr[CYBLE_BTS_COMMAND_DATA_LEN_OFFSET]) +
CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM;
/* Set flag for DFU to know that command is received from host */
cyBle_cmdReceivedFlag = 1u;
break;
default:
break;
}
}
#endif /* CY_BLE_HOST_CORE */
/* [] END OF FILE */

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/***************************************************************************//**
* \file transport_ble.h
* \version 3.0
*
* This file provides constants and parameter values of the DFU
* communication APIs for the BLE Component.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(TRANSPORT_BLE_H)
#define TRANSPORT_BLE_H
#include <stdint.h>
#include "cy_dfu.h"
#include "ble/cy_ble.h"
/***************************************
* Function Prototypes
***************************************/
/* BLE DFU physical layer functions */
void CyBLE_CyBtldrCommStart(void);
void CyBLE_CyBtldrCommStop (void);
void CyBLE_CyBtldrCommReset(void);
cy_en_dfu_status_t CyBLE_CyBtldrCommRead (uint8_t pData[], uint32_t size, uint32_t *count, uint32_t timeout);
cy_en_dfu_status_t CyBLE_CyBtldrCommWrite(const uint8_t pData[], uint32_t size, uint32_t *count, uint32_t timeout);
void DFUCallBack(uint32 event, void* eventParam);
/* BLE Callback */
extern void AppCallBack(uint32 event, void* eventParam);
/***************************************
* API Constants
***************************************/
#define CYBLE_BTS_COMMAND_DATA_LEN_OFFSET (2u)
#define CYBLE_BTS_COMMAND_CONTROL_BYTES_NUM (7u)
#define CYBLE_BTS_COMMAND_MAX_LENGTH (265u)
/***************************************
* Global variables declaration
***************************************/
extern cy_stc_ble_conn_handle_t appConnHandle;
#endif /* !defined(TRANSPORT_BLE_H) */
/* [] END OF FILE */