114 lines
4.1 KiB
C
114 lines
4.1 KiB
C
/*******************************************************************************
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* \file dfu_mdk_common.h
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* \version 3.0
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*
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* This file provides only macro definitions to use for
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* project configuration.
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* They may be used in both scatter files and source code files.
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* You may use this file only in accordance with the license, terms, conditions,
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* disclaimers, and limitations in the end user license agreement accompanying
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* the software package with which this file was provided.
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*******************************************************************************/
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#ifndef DFU_MDK_COMMON_H_
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#define DFU_MDK_COMMON_H_
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/* DFU SDK parameters */
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/* The user application may either update them or leave the defaults if they fit */
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#define CY_BOOT_METADATA_ADDR 0x100FFA00
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#define CY_BOOT_METADATA_LENGTH 0x200
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#define CY_PRODUCT_ID 0x01020304
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#define CY_CHECKSUM_TYPE 0x00
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/*
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* The size of the section .cy_app_signature.
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* 1,2, or 4 for a checksum
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* 4 for CRC-32
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* 20 for SHA1
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* 32 for SHA256
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* 256 for RSASSA-PKCS1-v1.5 with the 2048 bit RSA key.
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*
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* SHA1 must be used.
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*/
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#define CY_BOOT_SIGNATURE_SIZE 4
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/* For the MDK linker script, defines TOC parameters */
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/* Update per device series to be in the last Flash row */
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#define CY_TOC_START 0x16007C00
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#define CY_TOC_SIZE 0x400
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/* Memory region ranges per core and app */
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#define CY_APP0_CORE0_FLASH_ADDR 0x10000000
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#define CY_APP0_CORE0_FLASH_LENGTH 0x10000
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#define CY_APP0_CORE1_FLASH_ADDR 0x10010000
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#define CY_APP0_CORE1_FLASH_LENGTH 0x10000
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#define CY_APP1_CORE0_FLASH_ADDR 0x10040000
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#define CY_APP1_CORE0_FLASH_LENGTH 0x10000
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#define CY_APP1_CORE1_FLASH_ADDR 0x10050000
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#define CY_APP1_CORE1_FLASH_LENGTH 0x10000
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/* DFU SDK metadata address range in Flash */
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#define CY_BOOT_META_FLASH_ADDR 0x100FFA00
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#define CY_BOOT_META_FLASH_LENGTH 0x200
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/* Application ranges in emulated EEPROM */
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#define CY_APP0_CORE0_EM_EEPROM_ADDR 0x14000000
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#define CY_APP0_CORE0_EM_EEPROM_LENGTH 0x00000000
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#define CY_APP0_CORE1_EM_EEPROM_ADDR (CY_APP0_CORE0_EM_EEPROM_ADDR + CY_APP0_CORE0_EM_EEPROM_LENGTH)
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#define CY_APP0_CORE1_EM_EEPROM_LENGTH 0x0000
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#define CY_APP1_CORE0_EM_EEPROM_ADDR 0x14000000
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#define CY_APP1_CORE0_EM_EEPROM_LENGTH 0x00000000
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#define CY_APP1_CORE1_EM_EEPROM_ADDR (CY_APP1_CORE0_EM_EEPROM_ADDR + CY_APP1_CORE0_EM_EEPROM_LENGTH)
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#define CY_APP1_CORE1_EM_EEPROM_LENGTH 0x00000000
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/* Application ranges in SMIF XIP */
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#define CY_APP0_CORE0_SMIF_ADDR 0x18000000
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#define CY_APP0_CORE0_SMIF_LENGTH 0x00000000
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#define CY_APP0_CORE1_SMIF_ADDR (CY_APP0_CORE0_SMIF_ADDR + CY_APP0_CORE0_SMIF_LENGTH)
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#define CY_APP0_CORE1_SMIF_LENGTH 0x00000000
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#define CY_APP1_CORE0_SMIF_ADDR 0x14000200
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#define CY_APP1_CORE0_SMIF_LENGTH 0x00000000
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#define CY_APP1_CORE1_SMIF_ADDR (CY_APP1_CORE0_SMIF_ADDR + CY_APP1_CORE0_SMIF_LENGTH)
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#define CY_APP1_CORE1_SMIF_LENGTH 0x00000000
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/* Application ranges in RAM */
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#define CY_APP_RAM_COMMON_ADDR 0x08000000
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#define CY_APP_RAM_COMMON_LENGTH 0x00000100
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/* note: all the CY_APPX_CORE0_RAM regions has to be 0x100 aligned */
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/* and the CY_APPX_CORE1_RAM regions has to be 0x400 aligned */
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/* as they contain Interrupt Vector Table Remapped at the start */
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#define CY_APP0_CORE0_RAM_ADDR 0x08000100
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#define CY_APP0_CORE0_RAM_LENGTH 0x00001F00
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#define CY_APP0_CORE1_RAM_ADDR (CY_APP0_CORE0_RAM_ADDR + CY_APP0_CORE0_RAM_LENGTH)
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#define CY_APP0_CORE1_RAM_LENGTH 0x00008000
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#define CY_APP1_CORE0_RAM_ADDR CY_APP0_CORE0_RAM_ADDR
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#define CY_APP1_CORE0_RAM_LENGTH 0x00001F00
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#define CY_APP1_CORE1_RAM_ADDR (CY_APP1_CORE0_RAM_ADDR + CY_APP1_CORE0_RAM_LENGTH)
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#define CY_APP1_CORE1_RAM_LENGTH 0x00008000
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__asm void cy_DFU_mdkAsmDummy(void);
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#endif /* DFU_MDK_COMMON_H_ */
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/* [] END OF FILE */
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