/***************************************************************************//** * \file dfu_cm0p.icf * \version 3.0 * * The linker file for the the IAR compiler. * * \note The entry point is fixed and starts at 0x10000000. The valid application * image should be placed there. * * \note The linker files included with the PDL template projects must be generic * and handle all common use cases. Your project may not use every section * defined in the linker files. In that case, you may see warnings during the * build process. In your project, you can simply comment out or remove the * relevant code in the linker file. * ******************************************************************************** * \copyright * Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. *******************************************************************************/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ /******************************************************************************* * Start of CM4 and CM0+ linker script common region *******************************************************************************/ /*-Memory Regions-*/ /* Flash */ define exported symbol __cy_memory_0_start = 0x10000000; define exported symbol __cy_memory_0_length = 0x00100000; define exported symbol __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ define exported symbol __cy_memory_1_start = 0x14000000; define exported symbol __cy_memory_1_length = 0x8000; define exported symbol __cy_memory_1_row_size = 0x200; /* Supervisory Flash */ define exported symbol __cy_memory_2_start = 0x16000000; define exported symbol __cy_memory_2_length = 0x8000; define exported symbol __cy_memory_2_row_size = 0x200; /* XIP */ define exported symbol __cy_memory_3_start = 0x18000000; define exported symbol __cy_memory_3_length = 0x08000000; define exported symbol __cy_memory_3_row_size = 0x200; /* eFuse */ define exported symbol __cy_memory_4_start = 0x90700000; define exported symbol __cy_memory_4_length = 0x100000; define exported symbol __cy_memory_4_row_size = 1; define memory mem with size = 4G; /* Memory regions for all applications are defined here */ define region FLASH_app0_core0 = mem:[from 0x10000000 size 0x10000]; define region FLASH_app0_core1 = mem:[from 0x10010000 size 0x10000]; define region FLASH_app1_core0 = mem:[from 0x10040000 size 0x10000]; define region FLASH_app1_core1 = mem:[from 0x10050000 size 0x10000]; /* * The region for DFU SDK metadata * when it is outside of any application */ define region FLASH_boot_meta = mem:[from 0x100FFA00 size 0x200]; /* eFuse */ define region ROM_EFUSE = mem:[from 0x90700000 size 0x100000]; /* SFlash NAR */ define region SFLASH_NAR = mem:[from 0x16001A00 size 0x200]; /* SFlash User Data */ define region SFLASH_USER_DATA = mem:[from 0x16000800 size 0x800]; /* SFlash Public Key, 6 SFlash rows */ define region SFLASH_PUBLIC_KEY = mem:[from 0x16005A00 size 0xC00]; /* Table of Content part 2, two SFlash rows */ define region SFLASH_TOC = mem:[from 0x16007C00 size 0x400]; /* Emulated EEPROM app regions */ define region EM_EEPROM_app0_core0 = mem:[from 0x14000000 size 0x8000]; define region EM_EEPROM_app0_core1 = mem:[from 0x14000000 size 0x8000]; define region EM_EEPROM_app1_core0 = mem:[from 0x14000000 size 0x8000]; define region EM_EEPROM_app1_core1 = mem:[from 0x14000000 size 0x8000]; /* XIP/SMIF app regions */ define region EROM_app0_core0 = mem:[from 0x18000000 size 0x1000]; define region EROM_app0_core1 = mem:[from 0x18000000 size 0x1000]; define region EROM_app1_core0 = mem:[from 0x18000000 size 0x1000]; define region EROM_app1_core1 = mem:[from 0x18000000 size 0x1000]; /* used for RAM sharing across applications */ define region IRAM_common = mem:[from 0x08000000 size 0x0100]; /* note: all the IRAM_appX_core0 regions has to be 0x100 aligned */ /* and the IRAM_appX_core1 regions has to be 0x400 aligned */ /* as they contain Interrupt Vector Table Remapped at the start */ define region IRAM_app0_core0 = mem:[from 0x08000100 size 0x1F00]; define region IRAM_app0_core1 = mem:[from 0x08002000 size 0x8000]; define region IRAM_app1_core0 = mem:[from 0x08000100 size 0x1F00]; define region IRAM_app1_core1 = mem:[from 0x08002000 size 0x8000]; /* Used by all DFU SDK and CyMCUElfTool */ define exported symbol __cy_boot_metadata_addr = 0x100FFA00; define exported symbol __cy_boot_metadata_length = __cy_memory_0_row_size; /* Used by CyMCUElfTool to generate ProductID for DFU SDK apps */ define exported symbol __cy_product_id = 0x01020304; /* Used by CyMCUElfTool to generate ChecksumType for DFU SDK apps */ define exported symbol __cy_checksum_type = 0; /* * The size of the application signature. * E.g. 4 for CRC-32, * 32 for SHA256, * 256 for RSA 2048. */ define exported symbol __cy_boot_signature_size = 4; /* Used by DFU SDK projects, in dfu_user.c to fill in the metadata table */ define exported symbol __cy_app0_verify_start = start(FLASH_app0_core0); define exported symbol __cy_app0_verify_length = size (FLASH_app0_core0) + size (FLASH_app0_core1) - __cy_boot_signature_size; define exported symbol __cy_app1_verify_start = start(FLASH_app1_core0); define exported symbol __cy_app1_verify_length = size (FLASH_app1_core0) + size (FLASH_app1_core1) - __cy_boot_signature_size; /******************************************************************************* * End of CM4 and CM0+ linker script common region *******************************************************************************/ /* * Used by CM0+ to start the CM4 core in DFU SDK applications. * Make sure the correct app no. is entered here. */ define exported symbol __cy_app_core1_start_addr = start(FLASH_app0_core1); /* CyMCUElfTool uses this symbol to set a proper app number */ define exported symbol __cy_app_id = 0; /* CyMCUElfTool uses these to generate an application signature */ /* The size of the default signature (CRC-32C) is 4 bytes */ define exported symbol __cy_app_verify_start = start(FLASH_app0_core0); define exported symbol __cy_app_verify_length = size(FLASH_app0_core0) + size(FLASH_app0_core1) - __cy_boot_signature_size; /*-Sizes-*/ if (!isdefinedsymbol(__STACK_SIZE)) { define symbol __ICFEDIT_size_cstack__ = 0x1000; } else { define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE; } define symbol __ICFEDIT_size_proc_stack__ = 0x0; if (!isdefinedsymbol(__HEAP_SIZE)) { define symbol __ICFEDIT_size_heap__ = 0x0400; } else { define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; } define region IROM1_region = FLASH_app0_core0; /* Flash, user app */ define region IROM2_region = EM_EEPROM_app0_core0; /* Emulated EEPROM */ define region IROM3_region = SFLASH_USER_DATA; /* SFlash User Data */ define region IROM4_region = SFLASH_NAR; /* SFlash NAR */ define region IROM5_region = SFLASH_PUBLIC_KEY; /* SFlash Public Key */ define region IROM6_region = SFLASH_TOC; /* SFlash TOC part 2 */ define region IROM7_region = ROM_EFUSE; /* eFuse */ define region EROM1_region = EROM_app0_core0; /* XIP / SMIF */ define region IRAM1_region = IRAM_app0_core0; /* RAM */ define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK}; define block RO {first section .intvec, readonly}; /*-Initializations-*/ initialize by copy { readwrite }; do not initialize { section .noinit, section .intvec_ram, section .cy_boot_noinit.appId, section .cy_boot_noinit }; /*-Placement-*/ /* Flash */ ".cy_app_header" : place at start of IROM1_region { section .cy_app_header }; place in IROM1_region { block RO }; /* Emulated EEPROM Flash area */ ".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; /* Supervisory Flash - User Data */ ".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; /* Supervisory Flash - NAR */ ".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; /* Supervisory Flash - Public Key */ ".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; /* Supervisory Flash - TOC2 */ ".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; /* eFuse */ ".cy_efuse" : place at start of IROM7_region { section .cy_efuse }; /* Execute in Place (XIP). See the smif driver documentation for details. */ ".cy_xip" : place at start of EROM1_region { section .cy_xip }; /* RAM */ place at start of IRAM_common { readwrite section .cy_boot_noinit.appId }; place in IRAM_common { readwrite section .cy_boot_noinit }; place at start of IRAM1_region { readwrite section .intvec_ram}; place in IRAM1_region { readwrite }; place at end of IRAM1_region { block HSTACK }; /* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; keep { section .cy_app_header, section .cy_em_eeprom, section .cy_sflash_user_data, section .cy_sflash_nar, section .cy_sflash_public_key, section .cy_sflash_toc_2, section .cy_efuse, section .cy_xip, section .cymeta, section .cy_boot_noinit, section .cy_boot_noinit.appId, }; /* EOF */